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Reel/Frame:	045216/0020			Pages:	334
		Recorded:	02/01/2018
Attorney Dkt #:	43172.01200
Conveyance:	SECURITY INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 3463
Page 20 of 35
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35

Patent #:	6439972	Issue Dt:	08/27/2002	Application #:	09894117	Filing Dt:	06/28/2001
Publication #:	US20010036796	Pub Dt:	11/01/2001
Title:	POLISHING FLUID, POLISHING METHOD, SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE FABRICATION METHOD

Patent #:	6531932	Issue Dt:	03/11/2003	Application #:	09894210	Filing Dt:	06/27/2001
Title:	MICROSTRIP PACKAGE HAVING OPTIMIZED SIGNAL LINE IMPEDANCE CONTROL

Patent #:	6532577	Issue Dt:	03/11/2003	Application #:	09894618	Filing Dt:	06/27/2001
Title:	TIMING DRIVEN INTERCONNECT ANALYSIS

Patent #:	6611951	Issue Dt:	08/26/2003	Application #:	09895668	Filing Dt:	06/29/2001
Title:	METHOD FOR ESTIMATING CELL POROSITY OF HARDMACS

Patent #:	6812134	Issue Dt:	11/02/2004	Application #:	09896363	Filing Dt:	06/28/2001
Title:	DUAL LAYER BARRIER FILM TECHNIQUES TO PREVENT RESIST POISONING

Patent #:	6576506	Issue Dt:	06/10/2003	Application #:	09896669	Filing Dt:	06/29/2001
Publication #:	US20030001199	Pub Dt:	01/02/2003
Title:	ELECTROSTATIC DISCHARGE PROTECTION IN DOUBLE DIFFUSED MOS TRANSISTORS

Patent #:	6358806	Issue Dt:	03/19/2002	Application #:	09896958	Filing Dt:	06/29/2001
Title:	SILICON CARBIDE CMOS CHANNEL

Patent #:	6680243	Issue Dt:	01/20/2004	Application #:	09897517	Filing Dt:	06/29/2001
Title:	SHALLOW JUNCTION FORMATION

Patent #:	6673721	Issue Dt:	01/06/2004	Application #:	09898194	Filing Dt:	07/02/2001
Title:	PROCESS FOR REMOVAL OF PHOTORESIST MASK USED FOR MAKING VIAS IN LOW K CARBON-DOPED SILICON OXIDE DIELECTRIC MATERIAL, AND FOR REMOVAL OF ETCH RESIDUES FROM FORMATION OF VIAS AND REMOVAL OF PHOTORESIST MASK

Patent #:	6576981	Issue Dt:	06/10/2003	Application #:	09898267	Filing Dt:	07/03/2001
Title:	REDUCED PARTICULATE ETCHING

Patent #:	NONE	Issue Dt:		Application #:	09901073	Filing Dt:	07/09/2001
Publication #:	US20010043136	Pub Dt:	11/22/2001
Title:	Lateral high-Q inductor for semiconductor devices

Patent #:	6511872	Issue Dt:	01/28/2003	Application #:	09902358	Filing Dt:	07/10/2001
Publication #:	US20030013269	Pub Dt:	01/16/2003
Title:	DEVICE HAVING A HIGH DIELECTRIC CONSTANT MATERIAL AND A METHOD OF MANUFACTURE THEREOF

Patent #:	6432812	Issue Dt:	08/13/2002	Application #:	09906331	Filing Dt:	07/16/2001
Title:	METHOD OF COUPLING CAPACITANCE REDUCTION

Patent #:	6489231	Issue Dt:	12/03/2002	Application #:	09907424	Filing Dt:	07/17/2001
Title:	BARRIER AND SEED LAYER SYSTEM

Patent #:	6970622	Issue Dt:	11/29/2005	Application #:	09909175	Filing Dt:	07/19/2001
Title:	ARRANGEMENT AND METHOD FOR CONTROLLING THE TRANSMISSION OF A LIGHT SIGNAL BASED ON INTENSITY OF A RECEIVED LIGHT SIGNAL

Patent #:	6909150	Issue Dt:	06/21/2005	Application #:	09911035	Filing Dt:	07/23/2001
Publication #:	US20030015759	Pub Dt:	01/23/2003
Title:	MIXED SIGNAL INTEGRATED CIRCUIT WITH IMPROVED ISOLATION

Patent #:	6844236	Issue Dt:	01/18/2005	Application #:	09911364	Filing Dt:	07/23/2001
Publication #:	US20030015772	Pub Dt:	01/23/2003
Title:	METHOD AND STRUCTURE FOR DC AND RF SHIELDING OF INTEGRATED CIRCUITS

Patent #:	6951017	Issue Dt:	09/27/2005	Application #:	09916958	Filing Dt:	07/27/2001
Title:	DESIGN SYSTEM UPGRADE MIGRATION

Patent #:	6540974	Issue Dt:	04/01/2003	Application #:	09917365	Filing Dt:	07/27/2001
Publication #:	US20010040785	Pub Dt:	11/15/2001
Title:	PROCESS FOR MAKING MIXED METAL OXIDES

Patent #:	6710616	Issue Dt:	03/23/2004	Application #:	09918183	Filing Dt:	07/30/2001
Title:	WAFER LEVEL DYNAMIC BURN IN

Patent #:	6601008	Issue Dt:	07/29/2003	Application #:	09920890	Filing Dt:	08/02/2001
Title:	PARAMETRIC DEVICE SIGNATURE

Patent #:	6617866	Issue Dt:	09/09/2003	Application #:	09921028	Filing Dt:	08/02/2001
Title:	APPARATUS AND METHOD OF PROTECTING A PROBE CARD DURING A SORT SEQUENCE

Patent #:	6682962	Issue Dt:	01/27/2004	Application #:	09927194	Filing Dt:	08/10/2001
Publication #:	US20010050393	Pub Dt:	12/13/2001
Title:	GAAS MOSFET HAVING LOW CAPACITANCE AND ON-RESISTANCE AND METHOD OF MANUFACTURING THE SAME

Patent #:	6503793	Issue Dt:	01/07/2003	Application #:	09927752	Filing Dt:	08/10/2001
Title:	METHOD FOR CONCURRENTLY FORMING AN ESD PROTECTION DEVICE AND A SHALLOW TRENCH ISOLATION REGION

Patent #:	6534968	Issue Dt:	03/18/2003	Application #:	09928071	Filing Dt:	08/10/2001
Title:	INTEGRATED CIRCUIT TEST VEHICLE

Patent #:	6701511	Issue Dt:	03/02/2004	Application #:	09928471	Filing Dt:	08/13/2001
Title:	OPTICAL AND ETCH PROXIMITY CORRECTION

Patent #:	6743725	Issue Dt:	06/01/2004	Application #:	09928570	Filing Dt:	08/13/2001
Title:	HIGH SELECTIVITY SIC ETCH IN INTEGRATED CIRCUIT FABRICATION

Patent #:	6740922	Issue Dt:	05/25/2004	Application #:	09929188	Filing Dt:	08/14/2001
Publication #:	US20030036244	Pub Dt:	02/20/2003
Title:	INTERDIGITATED CAPACITOR AND METHOD OF MANUFACTURING THEREOF

Patent #:	6563198	Issue Dt:	05/13/2003	Application #:	09932307	Filing Dt:	08/17/2001
Title:	ADHESIVE PAD HAVING EMC SHIELDING CHARACTERISTICS

Patent #:	6723653	Issue Dt:	04/20/2004	Application #:	09932527	Filing Dt:	08/17/2001
Title:	PROCESS FOR REDUCING DEFECTS IN COPPER-FILLED VIAS AND/OR TRENCHES FORMED IN POROUS LOW-K DIELECTRIC MATERIAL

Patent #:	6759921	Issue Dt:	07/06/2004	Application #:	09932716	Filing Dt:	08/17/2001
Title:	CHARACTERISTIC IMPEDANCE EQUALIZER AND AN INTEGRATED CIRCUIT PACKAGE EMPLOYING THE SAME

Patent #:	6973421	Issue Dt:	12/06/2005	Application #:	09934051	Filing Dt:	08/21/2001
Title:	BZFLASH SUBCIRCUIT TO DYNAMICALLY SUPPLY BZ CODES FOR CONTROLLED IMPEDANCE BUFFER DEVELOPMENT, VERIFICATION AND SYSTEM LEVEL SIMULATIONS

Patent #:	6926841	Issue Dt:	08/09/2005	Application #:	09934283	Filing Dt:	08/21/2001
Publication #:	US20020001331	Pub Dt:	01/03/2002
Title:	STEPPED ETALON

Patent #:	6548906	Issue Dt:	04/15/2003	Application #:	09935241	Filing Dt:	08/22/2001
Publication #:	US20030038369	Pub Dt:	02/27/2003
Title:	METHOD FOR REDUCING A METAL SEAM IN AN INTERCONNECT STRUCTURE AND A DEVICE MANUFACTURED THEREBY

Patent #:	6573149	Issue Dt:	06/03/2003	Application #:	09940126	Filing Dt:	08/27/2001
Publication #:	US20020048893	Pub Dt:	04/25/2002
Title:	SEMICONDUCTOR DEVICE HAVING A METAL GATE WITH A WORK FUNCTION COMPATIBLE WITH A SEMICONDUCTOR DEVICE

Patent #:	6519844	Issue Dt:	02/18/2003	Application #:	09940130	Filing Dt:	08/27/2001
Title:	OVERMOLD INTEGRATED CIRCUIT PACKAGE

Patent #:	6587991	Issue Dt:	07/01/2003	Application #:	09941359	Filing Dt:	08/28/2001
Title:	OPTIMIZED METAL STACK STRATEGY

Patent #:	6898064	Issue Dt:	05/24/2005	Application #:	09942220	Filing Dt:	08/29/2001
Title:	SYSTEM AND METHOD FOR OPTIMIZING THE ELECTROSTATIC REMOVAL OF A WORKPIECE FROM A CHUCK

Patent #:	7578883	Issue Dt:	08/25/2009	Application #:	09942330	Filing Dt:	08/29/2001
Title:	ARRANGEMENT AND METHOD FOR ABATING EFFLUENT FROM A PROCESS

Patent #:	7601643	Issue Dt:	10/13/2009	Application #:	09943196	Filing Dt:	08/30/2001
Title:	ARRANGEMENT AND METHOD FOR FABRICATING A SEMICONDUCTOR WAFER

Patent #:	6521520	Issue Dt:	02/18/2003	Application #:	09943403	Filing Dt:	08/30/2001
Title:	SEMICONDUCTOR WAFER ARRANGEMENT AND METHOD OF PROCESSING A SEMICONDUCTOR WAFER

Patent #:	6648734	Issue Dt:	11/18/2003	Application #:	09943630	Filing Dt:	08/30/2001
Publication #:	US20030045220	Pub Dt:	03/06/2003
Title:	POLISHING HEAD FOR PRESSURIZED DELIVERY OF SLURRY

Patent #:	6696941	Issue Dt:	02/24/2004	Application #:	09944367	Filing Dt:	09/04/2001
Publication #:	US20030043034	Pub Dt:	03/06/2003
Title:	THEFT ALARM IN MOBILE DEVICE

Patent #:	6573113	Issue Dt:	06/03/2003	Application #:	09946033	Filing Dt:	09/04/2001
Title:	INTEGRATED CIRCUIT HAVING DEDICATED PROBE PADS FOR USE IN TESTING DENSELY PATTERNED BONDING PADS

Patent #:	6648743	Issue Dt:	11/18/2003	Application #:	09946253	Filing Dt:	09/05/2001
Title:	CHEMICAL MECHANICAL POLISHING PAD

Patent #:	6372524	Issue Dt:	04/16/2002	Application #:	09946895	Filing Dt:	09/05/2001
Title:	METHOD FOR CMP ENDPOINT DETECTION

Patent #:	6727107	Issue Dt:	04/27/2004	Application #:	09948808	Filing Dt:	09/07/2001
Title:	METHOD OF TESTING THE PROCESSING OF A SEMICONDUCTOR WAFER ON A CMP APPARATUS

Patent #:	6706622	Issue Dt:	03/16/2004	Application #:	09949207	Filing Dt:	09/07/2001
Title:	BONDING PAD INTERFACE

Patent #:	6664633	Issue Dt:	12/16/2003	Application #:	09950008	Filing Dt:	09/10/2001
Title:	ALKALINE COPPER PLATING

Patent #:	6690040	Issue Dt:	02/10/2004	Application #:	09950384	Filing Dt:	09/10/2001
Publication #:	US20030047749	Pub Dt:	03/13/2003
Title:	VERTICAL REPLACEMENT-GATE JUNCTION FIELD-EFFECT TRANSISTOR

Patent #:	6525358	Issue Dt:	02/25/2003	Application #:	09951178	Filing Dt:	09/13/2001
Publication #:	US20020074586	Pub Dt:	06/20/2002
Title:	CAPACITOR HAVING THE LOWER ELECTRODE FOR PREVENTING UNDESIRED DEFECTS AT THE SURFACE OF THE METAL PLUG

Patent #:	6620729	Issue Dt:	09/16/2003	Application #:	09952343	Filing Dt:	09/14/2001
Title:	ION BEAM DUAL DAMASCENE PROCESS

Patent #:	6794310	Issue Dt:	09/21/2004	Application #:	09952540	Filing Dt:	09/14/2001
Title:	METHOD AND APPARATUS FOR DETERMINING TEMPERATURE OF A SEMICONDUCTOR WAFER DURING FABRICATION THEREOF

Patent #:	6964924	Issue Dt:	11/15/2005	Application #:	09952790	Filing Dt:	09/11/2001
Title:	INTERGRATED CIRCUIT PROCESS MONITORING AND METROLOGY SYSTEM

Patent #:	6718524	Issue Dt:	04/06/2004	Application #:	09953667	Filing Dt:	09/17/2001
Title:	METHOD AND APPARATUS FOR ESTIMATING STATE-DEPENDENT GATE LEAKAGE IN AN INTEGRATED CIRCUIT

Patent #:	6524957	Issue Dt:	02/25/2003	Application #:	09953706	Filing Dt:	09/17/2001
Publication #:	US20020030282	Pub Dt:	03/14/2002
Title:	IN-SITU ELECTROPLATED OXIDE PASSIVATING FILM FOR CORROSION INHIBITION

Patent #:	6659846	Issue Dt:	12/09/2003	Application #:	09954341	Filing Dt:	09/17/2001
Publication #:	US20030054735	Pub Dt:	03/20/2003
Title:	PAD FOR CHEMICAL MECHANICAL POLISHING

Patent #:	6629304	Issue Dt:	09/30/2003	Application #:	09955698	Filing Dt:	09/19/2001
Title:	CELL PLACEMENT IN INTEGRATED CIRCUIT CHIPS TO REMOVE CELL OVERLAP, ROW OVERFLOW AND OPTIMAL PLACEMENT OF DUAL HEIGHT CELLS

Patent #:	NONE	Issue Dt:		Application #:	09956381	Filing Dt:	09/18/2001
Publication #:	US20030052365	Pub Dt:	03/20/2003
Title:	Structure and fabrication method for capacitors integratible with vertical replacement gate transistors

Patent #:	6759730	Issue Dt:	07/06/2004	Application #:	09956382	Filing Dt:	09/18/2001
Publication #:	US20030052721	Pub Dt:	03/20/2003
Title:	BIPOLAR JUNCTION TRANSISTOR COMPATIBLE WITH VERTICAL REPLACEMENT GATE TRANSISTORS

Patent #:	6701270	Issue Dt:	03/02/2004	Application #:	09957410	Filing Dt:	09/20/2001
Title:	METHOD FOR RELIABILITY TESTING LEAKAGE CHARACTERISTICS IN AN ELECTRONIC CIRCUIT AND A TESTING DEVICE FOR ACCOMPLISHING THE SAME

Patent #:	6641635	Issue Dt:	11/04/2003	Application #:	09957555	Filing Dt:	09/19/2001
Title:	LIQUID BASED AIR FILTRATION SYSTEM

Patent #:	6770505	Issue Dt:	08/03/2004	Application #:	09960441	Filing Dt:	09/21/2001
Title:	ARRANGEMENT FOR MEASURING PRESSURE ON A SEMICONDUCTOR WAFER AND AN ASSOCIATED METHOD FOR FABRICATING A SEMICONDUCTOR WAFER

Patent #:	6504219	Issue Dt:	01/07/2003	Application #:	09960765	Filing Dt:	09/21/2001
Title:	INDIUM FIELD IMPLANT FOR PUNCHTHROUGH PROTECTION IN SEMICONDUCTOR DEVICES

Patent #:	6686604	Issue Dt:	02/03/2004	Application #:	09961477	Filing Dt:	09/21/2001
Publication #:	US20030060015	Pub Dt:	03/27/2003
Title:	MULTIPLE OPERATING VOLTAGE VERTICAL REPLACEMENT-GATE (VRG) TRANSISTOR

Patent #:	6495875	Issue Dt:	12/17/2002	Application #:	09962641	Filing Dt:	09/25/2001
Publication #:	US20020017670	Pub Dt:	02/14/2002
Title:	METHOD OF FORMING METAL OXIDE METAL CAPACITORS USING MULTI-STEP RAPID MATERIAL THERMAL PROCESS AND A DEVICE FORMED THEREBY

Patent #:	6643832	Issue Dt:	11/04/2003	Application #:	09964011	Filing Dt:	09/26/2001
Title:	VIRTUAL TREE-BASED NETLIST MODEL AND METHOD OF DELAY ESTIMATION FOR AN INTEGRATED CIRCUIT DESIGN

Patent #:	7020589	Issue Dt:	03/28/2006	Application #:	09964030	Filing Dt:	09/26/2001
Title:	METHOD AND APPARATUS FOR ADAPTIVE TIMING OPTIMIZATION OF AN INTEGRATED CIRCUIT DESIGN

Patent #:	6737311	Issue Dt:	05/18/2004	Application #:	09964041	Filing Dt:	09/26/2001
Publication #:	US20030057494	Pub Dt:	03/27/2003
Title:	SEMICONDUCTOR DEVICE HAVING A BURIED LAYER FOR REDUCING LATCHUP AND A METHOD OF MANUFACTURE THEREFOR

Patent #:	6621146	Issue Dt:	09/16/2003	Application #:	09964157	Filing Dt:	09/26/2001
Title:	METHOD AND APPARATUS FOR THE USE OF EMBEDDED RESISTANCE TO LINEARIZE AND IMPROVE THE MATCHING PROPERTIES OF TRANSISTORS

Patent #:	6764930	Issue Dt:	07/20/2004	Application #:	09964227	Filing Dt:	09/26/2001
Publication #:	US20030057465	Pub Dt:	03/27/2003
Title:	METHOD AND STRUCTURE FOR MODULAR, HIGHLY LINEAR MOS CAPACITORS USING NITROGEN IMPLANTATION

Patent #:	6573183	Issue Dt:	06/03/2003	Application #:	09965739	Filing Dt:	09/28/2001
Publication #:	US20030064586	Pub Dt:	04/03/2003
Title:	METHOD AND APPARATUS FOR CONTROLLING CONTAMINATION DURING THE ELECTROPLATING DEPOSITION OF METALS ONTO A SEMICONDUCTOR WAFER SURFACE

Patent #:	6695572	Issue Dt:	02/24/2004	Application #:	09966156	Filing Dt:	09/28/2001
Publication #:	US20030063967	Pub Dt:	04/03/2003
Title:	METHOD AND APPARATUS FOR MINIMIZING SEMICONDUCTOR WAFER CONTAMINATION

Patent #:	6576544	Issue Dt:	06/10/2003	Application #:	09966464	Filing Dt:	09/28/2001
Title:	METHOD OF FABRICATING A LOCAL INTERCONNECT

Patent #:	6736953	Issue Dt:	05/18/2004	Application #:	09966651	Filing Dt:	09/28/2001
Title:	HIGH FREQUENCY ELECTROCHEMICAL DEPOSITION

Patent #:	6548422	Issue Dt:	04/15/2003	Application #:	09966779	Filing Dt:	09/27/2001
Publication #:	US20030060058	Pub Dt:	03/27/2003
Title:	METHOD AND STRUCTURE FOR OXIDE/SILICON NITRIDE INTERFACE SUBSTRUCTURE IMPROVEMENTS

Patent #:	6727165	Issue Dt:	04/27/2004	Application #:	09967074	Filing Dt:	09/28/2001
Title:	FABRICATION OF METAL CONTACTS FOR DEEP-SUBMICRON TECHNOLOGIES

Patent #:	7071563	Issue Dt:	07/04/2006	Application #:	09967094	Filing Dt:	09/28/2001
Publication #:	US20030062626	Pub Dt:	04/03/2003
Title:	BARRIER LAYER FOR INTERCONNECT STRUCTURES OF A SEMICONDUCTOR WAFER AND METHOD FOR DEPOSITING THE BARRIER LAYER

Patent #:	7039435	Issue Dt:	05/02/2006	Application #:	09967140	Filing Dt:	09/28/2001
Publication #:	US20030064732	Pub Dt:	04/03/2003
Title:	PROXIMITY REGULATION SYSTEM FOR USE WITH A PORTABLE CELL PHONE AND A METHOD OF OPERATION THEREOF

Patent #:	6496081	Issue Dt:	12/17/2002	Application #:	09967195	Filing Dt:	09/28/2001
Title:	TRANSMISSION EQUALIZATION SYSTEM AND AN INTEGRATED CIRCUIT PACKAGE EMPLOYING THE SAME

Patent #:	6641746	Issue Dt:	11/04/2003	Application #:	09967435	Filing Dt:	09/28/2001
Publication #:	US20030062339	Pub Dt:	04/03/2003
Title:	CONTROL OF SEMICONDUCTOR PROCESSING

Patent #:	6907590	Issue Dt:	06/14/2005	Application #:	09968008	Filing Dt:	10/02/2001
Title:	INTEGRATED CIRCUIT DESIGN SYSTEM AND METHOD FOR REDUCING AND AVOIDING CROSSTALK

Patent #:	6907586	Issue Dt:	06/14/2005	Application #:	09968009	Filing Dt:	10/02/2001
Title:	INTERGRATED DESIGN SYSTEM AND METHOD FOR REDUCING AND AVOIDING CROSSTALK

Patent #:	6709904	Issue Dt:	03/23/2004	Application #:	09968234	Filing Dt:	09/28/2001
Publication #:	US20030064567	Pub Dt:	04/03/2003
Title:	VERTICAL REPLACEMENT-GATE SILICON-ON-INSULATOR TRANSISTOR

Patent #:	6607927	Issue Dt:	08/19/2003	Application #:	09968243	Filing Dt:	09/28/2001
Publication #:	US20030064533	Pub Dt:	04/03/2003
Title:	METHOD AND APPARATUS FOR MONITORING IN-LINE COPPER CONTAMINATION

Patent #:	6657870	Issue Dt:	12/02/2003	Application #:	09968286	Filing Dt:	10/01/2001
Title:	DIE POWER DISTRIBUTION SYSTEM

Patent #:	NONE	Issue Dt:		Application #:	09968388	Filing Dt:	09/28/2001
Publication #:	US20030064550	Pub Dt:	04/03/2003
Title:	Method of ion implantation for achieving desired dopant concentration

Patent #:	6472314	Issue Dt:	10/29/2002	Application #:	09968944	Filing Dt:	10/02/2001
Title:	METHOD OF MAKING INTERCONNECT STRUCTURE INCLUDING DIAMOND BARRIER LAYER

Patent #:	6647348	Issue Dt:	11/11/2003	Application #:	09970392	Filing Dt:	10/21/1999
Publication #:	US20030069706	Pub Dt:	04/10/2003
Title:	LATENT DEFECT CLASSIFICATION SYSTEM

Patent #:	6472316	Issue Dt:	10/29/2002	Application #:	09971329	Filing Dt:	10/04/2001
Title:	PHOTOLITHOGRAPHY OVERLAY CONTROL

Patent #:	6792579	Issue Dt:	09/14/2004	Application #:	09972100	Filing Dt:	10/05/2001
Publication #:	US20030084410	Pub Dt:	05/01/2003
Title:	SPICE TO VERILOG NETLIST TRANSLATOR AND DESIGN METHODS USING SPICE TO VERILOG AND VERILOG TO SPICE TRANSLATION

Patent #:	6667536	Issue Dt:	12/23/2003	Application #:	09972481	Filing Dt:	10/05/2001
Publication #:	US20030003603	Pub Dt:	01/02/2003
Title:	THIN FILM MULTI-LAYER HIGH Q TRANSFORMER FORMED IN A SEMICONDUCTOR SUBSTRATE

Patent #:	6639298	Issue Dt:	10/28/2003	Application #:	09972482	Filing Dt:	10/05/2001
Publication #:	US20030001231	Pub Dt:	01/02/2003
Title:	MULTI-LAYER INDUCTOR FORMED IN A SEMICONDUCTOR SUBSTRATE

Patent #:	7051318	Issue Dt:	05/23/2006	Application #:	09973153	Filing Dt:	10/09/2001
Title:	WEB BASED OLA MEMORY GENERATOR

Patent #:	6658361	Issue Dt:	12/02/2003	Application #:	09974008	Filing Dt:	10/10/2001
Title:	HEAVIEST ONLY FAIL POTENTIAL

Patent #:	6618938	Issue Dt:	09/16/2003	Application #:	09974157	Filing Dt:	10/09/2001
Title:	INTERPOSER FOR SEMICONDUCTOR PACKAGE ASSEMBLY

Patent #:	6513376	Issue Dt:	02/04/2003	Application #:	09974251	Filing Dt:	10/10/2001
Title:	LIQUID LEVEL HEIGHT MEASUREMENT SYSTEM

Patent #:	6555914	Issue Dt:	04/29/2003	Application #:	09975871	Filing Dt:	10/12/2001
Title:	INTEGRATED CIRCUIT PACKAGE VIA

Patent #:	6931606	Issue Dt:	08/16/2005	Application #:	09978141	Filing Dt:	10/15/2001
Title:	AUTOMATIC METHOD AND SYSTEM FOR INSTANTIATING BUILT-IN -TEST (BIST) MODULES IN ASIC MEMORY DESIGNS

100

Patent #:	6696744	Issue Dt:	02/24/2004	Application #:	09978871	Filing Dt:	10/15/2001
Publication #:	US20020037434	Pub Dt:	03/28/2002
Title:	INTEGRATED CIRCUIT HAVING A MICROMAGNETIC DEVICE AND METHOD OF MANUFACTURE THEREFOR

Assignors

HILCO PATENT ACQUISITION 56, LLC

Exec Dt:

01/24/2018

BELL SEMICONDUCTOR, LLC

Exec Dt:

01/24/2018

BELL NORTHERN RESEARCH, LLC

Exec Dt:

01/24/2018

Assignee

CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT

225 W. WASHINGTON ST., 9TH FLOOR

CHICAGO, ILLINOIS 60606

Correspondence name and address
	JAVIER J. RAMOS
	1850 K STREET, NW, SUITE 1100
	MILBANK, TWEED, HADLEY & MCCLOY, LLP
	WASHINGTON, DC 20006

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