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05/04/2004
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10080186
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02/21/2002
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07/25/2002
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Title:
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METHODS OF FABRICATING A METAL-OXIDE-METAL CAPACITOR
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01/06/2004
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10082027
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02/20/2002
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08/21/2003
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Title:
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WIRE BOND PACKAGE WITH CORE RING FORMED OVER I/O CELLS
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06/29/2004
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10083411
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02/27/2002
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08/28/2003
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Title:
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SYSTEM AND METHOD FOR IDENTIFYING AND ELIMINATING BOTTLENECKS IN INTEGRATED CIRCUIT DESIGNS
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12/09/2003
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10086232
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02/27/2002
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08/28/2003
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METHOD OF REPEATER INSERTION FOR HIERARCHICAL INTEGRATED CIRCUIT DESIGN
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04/27/2004
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10091291
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03/05/2002
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07/18/2002
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Title:
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INTEGRATED CIRCUIT DEVICE SUBSTRATES WITH SELECTIVE EPITAXIAL GROWTH THICKNESS COMPENSATION
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09/02/2003
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10092195
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03/06/2002
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11/25/2003
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10094520
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03/08/2002
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09/11/2003
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THERMAL LOW K DIELECTRICS
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09/23/2003
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10094549
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03/08/2002
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SYSTEM AND METHOD FOR DETERMINING A SUBTHRESHOLD LEAKAGE TEST LIMIT OF AN INTEGRATED CIRCUIT
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11/02/2004
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10097419
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03/14/2002
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09/18/2003
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OPTICAL PROXIMITY CORRECTION DRIVEN HIERARCHY
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10/05/2004
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10099641
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03/15/2002
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09/05/2002
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LOW K DIELECTRIC COMPOSITE LAYER FOR INTEGRATED CIRCUIT STRUCTURE WHICH PROVIDES VOID-FREE LOW K DIELECTRIC MATERIAL BETWEEN METAL LINES WHILE MITIGATING VIA POISONING
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12/27/2005
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10103365
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03/21/2002
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07/24/2003
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RADIO FREQUENCY INTEGRATED CIRCUIT
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06/03/2003
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10105483
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03/25/2002
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IN SITU MEASUREMENT
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06/07/2005
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10105579
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03/25/2002
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INTEGRATED CIRCUIT HAVING INTEGRATED PROGRAMMABLE GATE ARRAY AND FIELD PROGRAMMABLE GATE ARRAY, AND METHOD OF OPERATING THE SAME
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05/11/2004
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10106128
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03/19/2002
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09/25/2003
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08/23/2005
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10106432
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03/26/2002
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INTEGRATED CIRCUIT HAVING INTEGRATED PROGRAMMABLE GATE ARRAY AND METHOD OF OPERATING THE SAME
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03/21/2006
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10106960
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03/26/2002
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10/02/2003
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SEQUENTIAL TEST PATTERN GENERATION USING CLOCK-CONTROL DESIGN FOR TESTABILITY STRUCTURES
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01/11/2005
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10108286
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03/27/2002
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10/02/2003
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SYMBOLIC SIMULATION DRIVEN NETLIST SIMPLIFICATION
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03/02/2004
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10109113
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03/27/2002
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10/02/2003
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FLOOR PLAN TESTER FOR INTEGRATED CIRCUIT DESIGN
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01/25/2005
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10114144
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04/02/2002
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10/02/2003
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VERTICALLY STAGGERED BONDPAD ARRAY
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04/12/2005
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10117487
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04/05/2002
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10/09/2003
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DYNAMIC USE OF PROCESS TEMPERATURE
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04/04/2006
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10119821
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04/10/2002
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INTEGRATED CIRCUIT HAVING A PROGRAMMABLE GATE ARRAY AND A FIELD PROGRAMMABLE GATE ARRAY AND METHODS OF DESIGNING AND MANUFACTURING THE SAME USING TESTING IC BEFORE CONFIGURING FPGA
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NONE
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10120707
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04/11/2002
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09/26/2002
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Process for fabricating copper interconnect for ULSI integrated circuits
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08/31/2004
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10120767
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04/10/2002
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10/16/2003
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METHOD AND APPARATUS FOR DETECTION OF CHEMICAL MECHANICAL PLANARIZATION ENDPOINT AND DEVICE PLANARITY
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05/31/2005
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10121370
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04/12/2002
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08/28/2003
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CHEMICAL MECHANICAL POLISHING OF DUAL ORIENTATION POLYCRYSTALLINE MATERIALS
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06/15/2004
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10122645
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04/12/2002
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10/16/2003
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CALIBRATION STANDARD FOR HIGH RESOLUTION ELECTRON MICROSCOPY
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11/07/2006
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10123263
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04/15/2002
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METHOD AND APPARATUS FOR FORMING A MEMORY STRUCTURE HAVING AN ELECTRON AFFINITY REGION
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04/11/2006
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10125675
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04/18/2002
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10/23/2003
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INPUT/OUTPUT CHARACTERIZATION CHAIN FOR AN INTEGRATED CIRCUIT
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08/10/2004
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10128534
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04/23/2002
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12/26/2002
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WEB-BASED INTERFACE WITH DEFECT DATABASE TO VIEW AND UPDATE FAILURE EVENTS
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09/30/2003
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10131431
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04/24/2002
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METHOD OF CHEMICALLY ALTERING A SILICON SURFACE AND ASSOCIATED ELECTRICAL DEVICES
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09/20/2005
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10132360
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04/25/2002
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10/30/2003
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MULTI-RESOLUTION VITERBI DECODING TECHNIQUE
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NONE
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10135189
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04/30/2002
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10/30/2003
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Extended instruction sets in a platform architecture
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02/06/2007
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10135383
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05/01/2002
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11/06/2003
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METHOD FOR ANALYZING MANUFACTURING DATA
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03/21/2006
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10135869
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04/30/2002
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10/30/2003
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COLLABORATIVE INTEGRATION OF HYBRID ELECTRONIC AND MICRO AND SUB-MICRO LEVEL AGGREGATES
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05/20/2003
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10138609
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05/03/2002
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PROCESS FOR IMPROVING MECHANICAL STRENGTH OF LAYERS OF LOW K DIELECTRIC MATERIAL
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09/30/2003
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10138742
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05/03/2002
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METHOD AND APPARATUS FOR DETECTING BACKSIDE CONTAMINATION DURING FABRICATION OF A SEMICONDUCTOR WAFER
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10/07/2003
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10140536
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05/07/2002
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METHOD AND APPARATUS FOR REMOVING WATER VAPOR AS A BYPRODUCT OF CHEMICAL REACTION IN A WAFER PROCESSING CHAMBER
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12/07/2004
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10140616
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05/07/2002
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Pub Dt:
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11/13/2003
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SEMICONDUCTOR DEVICE HAVING AN INTERCONNECT THAT ELECTRICALLY CONNECTS A CONDUCTIVE MATERIAL AND A DOPED LAYER, AND A METHOD OF MANUFACTURE THEREFOR
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01/27/2004
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10140967
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05/08/2002
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11/13/2003
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CONTACT RING ARCHITECTURE
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11/09/2004
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10141252
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05/08/2002
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11/13/2003
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DIRECT ALIGNMENT OF CONTACTS
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05/26/2009
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10143155
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05/10/2002
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11/13/2003
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REVISION CONTROL FOR DATABASE OF EVOLVED DESIGN
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05/24/2005
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10144101
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05/09/2002
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11/13/2003
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METHOD AND APPARATUS FOR CUSTOM DESIGN IN A STANDARD CELL DESIGN ENVIRONMENT
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08/16/2005
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10144511
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05/13/2002
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11/07/2002
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ELECTRONIC CIRCUIT STRUCTURE WITH IMPROVED DIELECTRIC PROPERTIES
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08/16/2005
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10146363
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05/15/2002
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DESIGN AND OPTIMIZATION METHODS FOR INTEGRATED CIRCUITS
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01/27/2004
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10147384
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05/16/2002
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10/31/2002
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A SEMICONDUCTOR DEVICE HAVING AN INTERCONNECT LAYER WITH A PLURALITY OF LAYOUT REGIONS HAVING SUBSTANTIALLY UNIFORM DENSITIES OF ACTIVE INTERCONNECTS AND DUMMY FILLS
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09/30/2003
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10150790
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05/17/2002
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INTEGRATED CIRCUIT DIE HAVING ALIGNMENT MARKS IN THE BOND PAD REGION AND METHOD OF MANUFACTURING SAME
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08/10/2004
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10151826
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05/22/2002
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11/27/2003
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CHIP DESIGN METHOD FOR DESIGNING INTEGRATED CIRCUIT CHIPS WITH EMBEDDED MEMORIES
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09/28/2004
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10151887
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05/22/2002
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11/27/2003
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FABRICATION PROCESS FOR A SEMICONDUCTOR DEVICE HAVING A METAL OXIDE DIELECTRIC MATERIAL WITH A HIGH DIELECTRIC CONSTANT, ANNEALED WITH A BUFFERED ANNEAL PROCESS
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NONE
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10152879
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05/21/2002
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01/23/2003
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Microstructure control of copper interconnects
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09/21/2004
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10153011
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05/21/2002
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09/26/2002
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INTEGRATED CIRCUIT STRUCTURE HAVING LOW DIELECTRIC CONSTANT MATERIAL AND HAVING SILICON OXYNITRIDE CAPS OVER CLOSELY SPACED APART METAL LINES
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02/03/2004
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10153231
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05/21/2002
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11/27/2003
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SEMICONDUCTOR DEVICE BARRIER LAYER
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12/16/2003
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10153570
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05/22/2002
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11/27/2003
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SPANNING TREE METHOD FOR K-DIMENSIONAL SPACE
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01/20/2004
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10155173
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05/28/2002
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12/04/2003
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HIGH K DIELECTRIC MATERIAL AND METHOD OF MAKING A HIGH K DIELECTRIC MATERIAL
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04/25/2006
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10155620
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05/22/2002
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11/27/2003
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QUALITY MEASUREMENT OF AN AERIAL IMAGE
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03/23/2004
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10156242
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05/24/2002
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11/27/2003
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ABNORMAL PHOTORESIST LINE/SPACE PROFILE DETECTION THROUGH SIGNAL PROCESSING OF METROLOGY WAVEFORM
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03/08/2005
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10158641
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05/30/2002
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GROUNDING MECHANISM FOR SEMICONDUCTOR DEVICES
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01/10/2006
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10158775
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05/30/2002
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12/04/2003
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OVERLAY METROLOGY USING SCATTEROMETRY PROFILING
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01/25/2005
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10159268
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Filing Dt:
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06/03/2002
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Publication #:
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Pub Dt:
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05/01/2003
| | | | |
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Title:
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HOLDER, SYSTEM, AND PROCESS FOR IMPROVING OVERLAY IN LITHOGRAPHY
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Patent #:
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Issue Dt:
|
09/02/2003
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Application #:
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10160812
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Filing Dt:
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05/31/2002
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Title:
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COMPOSITE SPACER SCHEME WITH LOW OVERLAPPED PARASITIC CAPACITANCE
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Patent #:
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Issue Dt:
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08/19/2003
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Application #:
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10163120
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Filing Dt:
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06/04/2002
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Title:
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LOW LEAKAGE PMOS ON-CHIP DECOUPLING CAPACITOR CELLS COMPATIBLE WITH STANDARD CMOS CELLS
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Patent #:
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Issue Dt:
|
12/07/2004
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Application #:
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10163208
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Filing Dt:
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06/04/2002
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Title:
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METHOD AND SYSTEM FOR CHECKING FOR POWER ERRORS IN ASIC DESIGNS
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Patent #:
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Issue Dt:
|
10/21/2003
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Application #:
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10164202
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Filing Dt:
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06/06/2002
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Title:
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ULTRA THIN BODY VERTICAL REPLACEMENT GATE MOSFET
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Patent #:
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Issue Dt:
|
06/01/2004
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Application #:
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10164227
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Filing Dt:
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06/05/2002
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Title:
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METHOD OF REDUCING LEAKAGE USING SI3N4 OR SION BLOCK DIELECTRIC FILMS
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Patent #:
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Issue Dt:
|
04/29/2003
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Application #:
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10164909
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Filing Dt:
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06/07/2002
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Title:
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ARRANGEMENT AND METHOD FOR POLISHING A SURFACE OF A SEMICONDUCTOR WAFER
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Patent #:
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Issue Dt:
|
05/11/2004
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Application #:
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10166797
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Filing Dt:
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06/10/2002
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Publication #:
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Pub Dt:
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12/11/2003
| | | | |
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Title:
|
PRE-SILICON VERIFICATION PATH COVERAGE
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Patent #:
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Issue Dt:
|
05/13/2003
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Application #:
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10171700
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Filing Dt:
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06/14/2002
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Publication #:
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Pub Dt:
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10/17/2002
| | | | |
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Title:
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SILICON NITRIDE AND SILICON DIOXIDE GATE INSULATOR TRANSISTORS AND METHOD OF FORMING SAME IN A HYBRID INTEGRATED CIRCUIT
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10171701
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Filing Dt:
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06/14/2002
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Publication #:
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Pub Dt:
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01/16/2003
| | | | |
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Title:
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Coupling capacitance reduction
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Patent #:
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Issue Dt:
|
07/12/2005
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Application #:
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10172849
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Filing Dt:
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06/17/2002
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Publication #:
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Pub Dt:
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12/18/2003
| | | | |
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Title:
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METHOD TO IMPROVE THE CONTROL OF SOURCE CHEMICALS DELIVERY BY A CARRIER GAS
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Patent #:
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Issue Dt:
|
12/14/2004
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Application #:
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10173182
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Filing Dt:
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06/17/2002
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Publication #:
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Pub Dt:
|
12/26/2002
| | | | |
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Title:
|
FLIP CHIP SEMICONDUSTOR DEVICE AND METHOD OF MAKING THE SAME
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Patent #:
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|
Issue Dt:
|
10/19/2010
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Application #:
|
10174681
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Filing Dt:
|
06/19/2002
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|
Publication #:
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Pub Dt:
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12/25/2003
| | | | |
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Title:
|
INSTANTANEOUS VOLTAGE DROP SENSITIVITY ANALYSIS TOOL (IVDSAT)
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Patent #:
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Issue Dt:
|
02/21/2006
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Application #:
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10177591
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Filing Dt:
|
06/19/2002
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|
Publication #:
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Pub Dt:
|
12/25/2003
| | | | |
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Title:
|
TABLE MODULE COMPILER EQUIVALENT TO ROM
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Patent #:
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|
Issue Dt:
|
01/11/2005
|
Application #:
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10178193
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Filing Dt:
|
06/24/2002
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Publication #:
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Pub Dt:
|
12/25/2003
| | | | |
|
Title:
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APPLICATION OF CO-VERIFICATION TOOLS TO THE TESTING OF IC DESIGNS
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Patent #:
|
NONE
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Issue Dt:
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|
Application #:
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10179057
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Filing Dt:
|
06/25/2002
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|
Publication #:
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Pub Dt:
|
12/25/2003
| | | | |
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Title:
|
Method and structure for graded gate oxides on vertical and non-planar surfaces
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|
Patent #:
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|
Issue Dt:
|
11/30/2004
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Application #:
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10180221
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Filing Dt:
|
06/25/2002
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|
Publication #:
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Pub Dt:
|
12/25/2003
| | | | |
|
Title:
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APPARATUS FOR SCANNING A CRYSTALLINE SAMPLE AND ASSOCIATED METHODS
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|
Patent #:
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Issue Dt:
|
08/10/2004
|
Application #:
|
10180661
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Filing Dt:
|
06/25/2002
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Title:
|
METHOD AND STRUCTURE FOR FORMING DIELECTRIC LAYERS HAVING REDUCED DIELECTRIC CONSTANTS
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Patent #:
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Issue Dt:
|
01/25/2005
|
Application #:
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10180910
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Filing Dt:
|
06/25/2002
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|
Publication #:
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|
Pub Dt:
|
12/25/2003
| | | | |
|
Title:
|
CAPACITOR FOR A SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATION THEREFOR
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|
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|
Patent #:
|
|
Issue Dt:
|
03/02/2004
|
Application #:
|
10185537
|
Filing Dt:
|
07/01/2002
|
|
Title:
|
METHOD OF FABRICATING AN INTEGRAL CAPACITOR AND GATE TRANSISTOR HAVING NITRIDE AND OXIDE POLISH STOP LAYERS USING CHEMICAL MECHANICAL POLISHING ELIMINATION
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Patent #:
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Issue Dt:
|
07/27/2004
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Application #:
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10185740
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Filing Dt:
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06/27/2002
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Publication #:
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Pub Dt:
|
01/01/2004
| | | | |
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Title:
|
SCALE-INVARIANT TOPOLOGY AND TRAFFIC ALLOCATION IN MULTI-NODE SYSTEM-ON-CHIP SWITCHING FABRICS
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Patent #:
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Issue Dt:
|
10/24/2006
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Application #:
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10186263
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Filing Dt:
|
06/27/2002
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|
Publication #:
|
|
Pub Dt:
|
01/01/2004
| | | | |
|
Title:
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TIMING ABSTRACTION AND PARTITIONING STRATEGY
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Patent #:
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|
Issue Dt:
|
10/19/2004
|
Application #:
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10190954
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Filing Dt:
|
07/08/2002
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|
Publication #:
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|
Pub Dt:
|
01/08/2004
| | | | |
|
Title:
|
PLASMA PASSIVATION
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|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
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|
Application #:
|
10191107
|
Filing Dt:
|
07/09/2002
|
|
Publication #:
|
|
Pub Dt:
|
11/21/2002
| | | | |
|
Title:
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System to improve SER immunity and punchthrough with an additional well tub deeper than shallow trench isolation
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|
Patent #:
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|
Issue Dt:
|
07/27/2004
|
Application #:
|
10191670
|
Filing Dt:
|
07/09/2002
|
|
Publication #:
|
|
Pub Dt:
|
01/15/2004
| | | | |
|
Title:
|
IMPLEMENTATION OF SI-GE HBT WITH CMOS PROCESS
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|
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|
|
Patent #:
|
|
Issue Dt:
|
10/26/2004
|
Application #:
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10192989
|
Filing Dt:
|
07/10/2002
|
|
Publication #:
|
|
Pub Dt:
|
01/15/2004
| | | | |
|
Title:
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INTEGRATED CIRCUIT DESIGN FLOW WITH CAPACITIVE MARGIN
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|
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|
Patent #:
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|
Issue Dt:
|
03/11/2003
|
Application #:
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10194134
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Filing Dt:
|
07/12/2002
|
|
Title:
|
RATIO TESTING
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|
|
|
|
Patent #:
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|
Issue Dt:
|
01/06/2004
|
Application #:
|
10194578
|
Filing Dt:
|
07/12/2002
|
|
Title:
|
THIN FILM CMOS CALIBRATION STANDARD HAVING PROTECTIVE COVER LAYER
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|
|
|
|
Patent #:
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|
Issue Dt:
|
02/22/2005
|
Application #:
|
10195044
|
Filing Dt:
|
07/12/2002
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|
Title:
|
ELECTRO CHEMICAL MECHANICAL POLISHING METHOD AND DEVICE FOR PLANARIZING SEMICONDUCTOR SURFACES
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|
Patent #:
|
|
Issue Dt:
|
01/06/2004
|
Application #:
|
10195775
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Filing Dt:
|
07/12/2002
|
|
Title:
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METHOD OF REDUCING PROCESS PLASMA DAMAGE USING OPTICAL SPECTROSCOPY
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Patent #:
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|
Issue Dt:
|
11/14/2006
|
Application #:
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10195935
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Filing Dt:
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07/16/2002
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|
Publication #:
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|
Pub Dt:
|
11/28/2002
| | | | |
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Title:
|
CAPACITOR FOR INTEGRATION WITH COPPER DAMASCENE PROCESSES AND A METHOD OF MANUFACTURE THEREFORE
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Patent #:
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|
Issue Dt:
|
09/07/2004
|
Application #:
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10196787
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Filing Dt:
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07/17/2002
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|
Publication #:
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Pub Dt:
|
11/28/2002
| | | | |
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Title:
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EXHAUST FLOW CONTROL SYSTEM
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Patent #:
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|
Issue Dt:
|
10/19/2004
|
Application #:
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10197956
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Filing Dt:
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07/16/2002
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Title:
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ADAPTIVE OFF TESTER SCREENING METHOD BASED ON INTRINSIC DIE PARAMETRIC MEASUREMENTS
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Patent #:
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Issue Dt:
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01/04/2005
|
Application #:
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10200233
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Filing Dt:
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07/23/2002
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Publication #:
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|
Pub Dt:
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01/29/2004
| | | | |
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Title:
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PROCESS FOR FABRICATING A MASK
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Patent #:
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|
Issue Dt:
|
06/22/2004
|
Application #:
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10200469
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Filing Dt:
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07/18/2002
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Title:
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PROCESS AND APPARATUS FOR WAFER EDGE PROFILE CONTROL USING GAS FLOW CONTROL RING
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Patent #:
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Issue Dt:
|
11/11/2003
|
Application #:
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10201010
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Filing Dt:
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07/22/2002
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Title:
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KEY HOLE FILLING
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Patent #:
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Issue Dt:
|
05/20/2003
|
Application #:
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10205229
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Filing Dt:
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07/25/2002
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Title:
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METHOD AND APPARATUS FOR PLANARIZING A WAFER SURFACE OF A SEMICONDUCTOR WAFER HAVING AN ELEVATED PORTION EXTENDING THEREFROM
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Patent #:
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Issue Dt:
|
07/20/2004
|
Application #:
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10207607
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Filing Dt:
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07/29/2002
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Publication #:
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Pub Dt:
|
01/29/2004
| | | | |
|
Title:
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METHOD TO IMPROVE THE RESOLUTION OF A PHOTOLITHOGRAPHY SYSTEM BY USE OF A COUPLING LAYER BETWEEN THE PHOTO RESIST AND THE ARC
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Patent #:
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Issue Dt:
|
11/04/2003
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Application #:
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10210365
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Filing Dt:
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08/01/2002
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Publication #:
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Pub Dt:
|
12/05/2002
| | | | |
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Title:
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INTEGRATED CIRCUIT FABRICATION DUAL PLASMA PROCESS WITH SEPARATE INTRODUCTION OF DIFFERENT GASES INTO GAS FLOW
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Patent #:
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Issue Dt:
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02/15/2005
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Application #:
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10210651
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Filing Dt:
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07/31/2002
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Publication #:
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Pub Dt:
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02/05/2004
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Title:
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INTERACTIVE REPRESENTATION OF STRUCTURAL DEPENDENCIES IN SEMICONDUCTOR DESIGN FLOWS
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Patent #:
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Issue Dt:
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11/25/2003
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Application #:
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10211674
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Filing Dt:
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08/02/2002
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Publication #:
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Pub Dt:
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03/27/2003
| | | | |
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Title:
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CMOS INTEGRATED CIRCUIT HAVING VERTICAL TRANSISTORS AND A PROCESS FOR FABRICATING SAME
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Patent #:
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Issue Dt:
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08/17/2004
|
Application #:
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10211914
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Filing Dt:
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08/02/2002
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Publication #:
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Pub Dt:
|
02/05/2004
| | | | |
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Title:
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METHOD OF FORMING ELECTROLYTIC CONTACT PADS INCLUDING LAYERS OF COPPER, NICKEL, AND GOLD
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Patent #:
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Issue Dt:
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03/02/2004
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Application #:
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10212448
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Filing Dt:
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08/05/2002
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|
Publication #:
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Pub Dt:
|
02/05/2004
| | | | |
|
Title:
|
FLIP-CHIP BALL GRID ARRAY PACKAGE FOR ELECTROMIGRATION TESTING
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Patent #:
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Issue Dt:
|
12/02/2003
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Application #:
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10215170
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Filing Dt:
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08/08/2002
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Publication #:
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Pub Dt:
|
12/19/2002
| | | | |
|
Title:
|
METHOD FOR IN-SITU REMOVAL OF SIDE WALLS IN MOM CAPACITOR FORMATION
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|
