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Patent #:
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Issue Dt:
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05/27/2003
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Application #:
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10216425
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Filing Dt:
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08/08/2002
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Title:
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METHOD OF REDUCING THE EFFECT OF IMPLANTATION DAMAGE TO SHALLOW TRENCH ISOLATION REGIONS DURING THE FORMATION OF VARIABLE THICKNESS GATE LAYERS
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Patent #:
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Issue Dt:
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12/21/2004
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Application #:
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10218783
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Filing Dt:
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08/14/2002
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Publication #:
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Pub Dt:
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12/19/2002
| | | | |
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Title:
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SEMICONDUCTOR DEVICE WITH VARIABLE PIN LOCATIONS
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Patent #:
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Issue Dt:
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05/17/2005
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Application #:
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10219951
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Filing Dt:
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08/15/2002
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Publication #:
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Pub Dt:
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02/27/2003
| | | | |
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Title:
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MULTIPLE PURPOSE RETICLE LAYOUT FOR SELECTIVE PRINTING OF TEST CIRCUITS
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Patent #:
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Issue Dt:
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08/10/2004
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Application #:
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10223931
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Filing Dt:
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08/20/2002
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Publication #:
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Pub Dt:
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02/26/2004
| | | | |
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Title:
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DEVICE PARAMETER AND GATE PERFORMANCE SIMULATION BASED ON WAFER IMAGE PREDICTION
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Patent #:
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Issue Dt:
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10/05/2004
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Application #:
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10224019
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Filing Dt:
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08/19/2002
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Title:
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CALCULATING RESISTANCE OF CONDUCTOR LAYER FOR INTEGRATED CIRCUIT DESIGN
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Patent #:
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Issue Dt:
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07/20/2004
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Application #:
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10224025
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Filing Dt:
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08/20/2002
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Title:
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CONDITIONING BAR ASSEMBLY HAVING AN ABRASION MEMBER SUPPORTED ON A POLYCARBONATE MEMBER
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Patent #:
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NONE
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Application #:
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10224220
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Filing Dt:
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08/20/2002
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Publication #:
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Pub Dt:
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12/26/2002
| | | | |
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Title:
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Transistor fabrication method
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Patent #:
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Issue Dt:
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08/31/2004
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Application #:
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10225909
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Filing Dt:
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08/21/2002
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Publication #:
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Pub Dt:
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02/26/2004
| | | | |
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Title:
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AUTOMATIC RECOGNITION OF AN OPTICALLY PERIODIC STRUCTURE IN AN INTEGRATED CIRCUIT DESIGN
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Patent #:
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Issue Dt:
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12/12/2006
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10226884
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Filing Dt:
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08/23/2002
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Title:
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METHOD FOR IMPLANTING IONS IN A SEMICONDUCTOR
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Patent #:
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Issue Dt:
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03/22/2005
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10226930
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Filing Dt:
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08/22/2002
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Publication #:
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Pub Dt:
|
03/11/2004
| | | | |
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Title:
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ELECTRO-MECHANICAL DEVICE HAVING A CHARGE DISSIPATION LAYER AND A METHOD OF MANUFACTURE THEREFOR
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Patent #:
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Issue Dt:
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03/29/2005
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Application #:
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10228444
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Filing Dt:
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08/27/2002
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Title:
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FAULT TOLERANT OPERATION OF RECONFIGURABLE DEVICES UTILIZING AN ADJUSTABLE SYSTEM CLOCK
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Patent #:
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Issue Dt:
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03/01/2005
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Application #:
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10228859
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Filing Dt:
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08/27/2002
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Publication #:
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Pub Dt:
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01/09/2003
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Title:
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CAPACITOR HAVING A TANTALUM LOWER ELECTRODE AND METHOD OF FORMING THE SAME
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Patent #:
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Issue Dt:
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08/24/2004
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Application #:
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10229601
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Filing Dt:
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08/28/2002
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Publication #:
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Pub Dt:
|
03/04/2004
| | | | |
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Title:
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TEST STRUCTURE
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Patent #:
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Issue Dt:
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08/17/2004
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Application #:
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10229659
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Filing Dt:
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08/28/2002
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Publication #:
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Pub Dt:
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03/04/2004
| | | | |
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Title:
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SOLDER MASK ON BONDING RING
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Patent #:
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Issue Dt:
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05/01/2007
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Application #:
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10231641
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Filing Dt:
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08/30/2002
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Publication #:
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Pub Dt:
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03/04/2004
| | | | |
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Title:
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INTERFACE FOR RAPID PROTOTYPING SYSTEM
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Patent #:
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Issue Dt:
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11/20/2007
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Application #:
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10231643
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Filing Dt:
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08/30/2002
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Publication #:
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Pub Dt:
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03/04/2004
| | | | |
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Title:
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RAPID PROTOTYPING SYSTEM
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Patent #:
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Issue Dt:
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06/08/2004
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Application #:
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10231904
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Filing Dt:
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08/30/2002
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Publication #:
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Pub Dt:
|
03/04/2004
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Title:
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METHOD OF USING FILLLER METAL FOR IMPLEMENTING CHANGES IN AN INTEGRATED CIRCUIT DESIGN
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Patent #:
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Issue Dt:
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02/01/2005
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Application #:
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10232423
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Filing Dt:
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08/28/2002
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Publication #:
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Pub Dt:
|
03/04/2004
| | | | |
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Title:
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STATIC TIMING ANALYSIS AND PERFORMANCE DIAGNOSTIC DISPLAY TOOL
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Patent #:
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Issue Dt:
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10/24/2006
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Application #:
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10234354
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Filing Dt:
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09/03/2002
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Publication #:
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Pub Dt:
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03/04/2004
| | | | |
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Title:
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PROTRUDING SPACERS FOR SELF-ALIGNED CONTACTS
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Patent #:
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Issue Dt:
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08/24/2004
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Application #:
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10236207
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Filing Dt:
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09/05/2002
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Publication #:
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Pub Dt:
|
03/11/2004
| | | | |
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Title:
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WAFER PROCESS CRITICAL DIMENSION, ALIGNMENT, AND REGISTRATION ANALYSIS SIMULATION TOOL
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Patent #:
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Issue Dt:
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03/21/2006
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Application #:
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10236226
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Filing Dt:
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09/06/2002
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Publication #:
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Pub Dt:
|
03/11/2004
| | | | |
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Title:
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RETICLE OVERLAY CORRECTION
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Patent #:
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Issue Dt:
|
05/11/2004
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Application #:
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10238073
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Filing Dt:
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09/09/2002
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Publication #:
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Pub Dt:
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04/03/2003
| | | | |
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Title:
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DIAMOND BARRIER LAYER
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Patent #:
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Issue Dt:
|
05/09/2006
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Application #:
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10241317
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Filing Dt:
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09/11/2002
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Publication #:
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Pub Dt:
|
03/11/2004
| | | | |
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Title:
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ARCHITECTURE AND/OR METHOD FOR USING INPUT/OUTPUT AFFINITY REGION FOR FLEXIBLE USE OF HARD MACRO I/O BUFFERS
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Patent #:
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Issue Dt:
|
01/11/2005
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Application #:
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10242165
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Filing Dt:
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09/11/2002
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Publication #:
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Pub Dt:
|
03/11/2004
| | | | |
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Title:
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GLOBAL CHIP INTERCONNECT
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Patent #:
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Issue Dt:
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04/26/2005
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Application #:
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10243562
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Filing Dt:
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09/13/2002
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Title:
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OPTICAL ERROR MINIMIZATION IN A SEMICONDUCTOR MANUFACTURING APPARATUS
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Patent #:
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Issue Dt:
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02/15/2005
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Application #:
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10245219
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Filing Dt:
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09/17/2002
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Title:
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LOW-LOSS ON-CHIP TRANSMISSION LINE FOR INTEGRATED CIRCUIT STRUCTURES AND METHOD OF MANUFACTURE
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Patent #:
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Issue Dt:
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07/31/2007
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Application #:
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10245447
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Filing Dt:
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09/17/2002
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Publication #:
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Pub Dt:
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03/18/2004
| | | | |
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Title:
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METHOD FOR FORMING METAL SILICIDE REGIONS IN AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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05/17/2005
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Application #:
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10246286
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Filing Dt:
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09/17/2002
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Title:
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DUAL SOURCE LITHOGRAPHY FOR DIRECT WRITE APPLICATION
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Patent #:
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Issue Dt:
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04/08/2003
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Application #:
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10251016
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Filing Dt:
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09/20/2002
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Title:
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POLYSILICON GATE SALICIDATION
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Patent #:
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Issue Dt:
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12/12/2006
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Application #:
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10251082
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Filing Dt:
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09/20/2002
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Publication #:
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Pub Dt:
|
03/25/2004
| | | | |
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Title:
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MASK DEFECT ANALYSIS FOR BOTH HORIZONTAL AND VERTICAL PROCESSING EFFECTS
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Patent #:
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Issue Dt:
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06/08/2004
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Application #:
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10252488
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Filing Dt:
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09/23/2002
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Publication #:
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Pub Dt:
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03/25/2004
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Title:
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DEVICE UNDER TEST INTERFACE CARD WITH ON-BOARD TESTING
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Patent #:
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Issue Dt:
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03/02/2004
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Application #:
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10253006
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Filing Dt:
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09/23/2002
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Title:
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MODEL OF THE CONTACT REGION OF INTEGRATED CIRCUIT RESISTORS
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Patent #:
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Issue Dt:
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03/30/2004
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Application #:
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10253158
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Filing Dt:
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09/24/2002
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Publication #:
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Pub Dt:
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01/23/2003
| | | | |
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Title:
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PROCESS FOR PLANARIZATION OF INTEGRATED CIRCUIT STRUCTURE WHICH INHIBITS CRACKING OF LOW DIELECTRIC CONSTANT DIELECTRIC MATERIAL ADJACENT UNDERLYING RAISED STRUCTURES
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Patent #:
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Issue Dt:
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05/17/2005
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Application #:
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10254083
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Filing Dt:
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09/24/2002
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Publication #:
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Pub Dt:
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03/25/2004
| | | | |
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Title:
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SUBSTRATE TOPOGRAPHY COMPENSATION AT MASK DESIGN: 3D OPC TOPOGRAPHY ANCHORED
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Patent #:
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Issue Dt:
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10/26/2004
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Application #:
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10254380
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Filing Dt:
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09/25/2002
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Publication #:
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Pub Dt:
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03/25/2004
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Title:
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PROCESS OF RESTRUCTURING LOGICS IN ICS FOR SETUP AND HOLD TIME OPTIMIZATION
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Patent #:
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Issue Dt:
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02/01/2005
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Application #:
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10254473
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Filing Dt:
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09/25/2002
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Title:
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SYSTEM AND METHOD FOR USING FILM DEPOSITION TECHNIQUES TO PROVIDE AN ANTENNA WITHIN AN INTEGRATED CIRCUIT PACKAGE
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Patent #:
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Issue Dt:
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07/06/2004
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Application #:
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10254607
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Filing Dt:
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09/25/2002
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Publication #:
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Pub Dt:
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03/25/2004
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Title:
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PROCESS LAYOUT OF BUFFER MODULES IN INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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10/12/2004
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Application #:
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10254616
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Filing Dt:
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09/25/2002
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Publication #:
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Pub Dt:
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03/25/2004
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Title:
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PROCESS FOR LAYOUT OF MEMORY MATRICES IN INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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03/29/2005
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Application #:
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10254708
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Filing Dt:
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09/25/2002
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Publication #:
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Pub Dt:
|
03/25/2004
| | | | |
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Title:
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DIRECT POSITIVE IMAGE PHOTO-RESIST TRANSFER OF SUBSTRATE DESIGN
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Patent #:
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Issue Dt:
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02/10/2004
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Application #:
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10256466
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Filing Dt:
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09/27/2002
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Publication #:
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Pub Dt:
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04/03/2003
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Title:
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HIGH DOPANT CONCENTRATION DIFFUSED RESISTOR AND METHOD OF MANUFACTURE THEREFOR
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Patent #:
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Issue Dt:
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12/06/2005
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Application #:
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10259254
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Filing Dt:
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09/27/2002
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Publication #:
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Pub Dt:
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04/15/2004
| | | | |
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Title:
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ELECTROCHEMICAL METHOD AND SYSTEM FOR MONITORING HYDROGEN PEROXIDE CONCENTRATION IN SLURRIES
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Patent #:
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Issue Dt:
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05/04/2004
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Application #:
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10259256
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Filing Dt:
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09/27/2002
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Publication #:
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Pub Dt:
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04/01/2004
| | | | |
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Title:
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METHOD OF DRY ETCHING A SEMICONDUCTOR DEVICE IN THE ABSENCE OF A PLASMA
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Patent #:
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Issue Dt:
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08/31/2004
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Application #:
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10260693
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Filing Dt:
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09/30/2002
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Publication #:
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Pub Dt:
|
04/01/2004
| | | | |
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Title:
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JUNCTION CAPACITOR STRUCTURE AND FABRICATION METHOD THEREFOR IN A DUAL DAMASCENE PROCESS
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Patent #:
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Issue Dt:
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12/07/2004
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Application #:
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10260694
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Filing Dt:
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09/30/2002
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Publication #:
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Pub Dt:
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04/01/2004
| | | | |
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Title:
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APPARATUS AND METHOD FOR DETECTING ALPHA PARTICLES
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Patent #:
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Issue Dt:
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02/28/2006
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Application #:
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10260727
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Filing Dt:
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09/30/2002
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Publication #:
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Pub Dt:
|
04/01/2004
| | | | |
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Title:
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METHOD TO AVOID COPPER CONTAMINATION OF A VIA OR DUAL DAMASCENE STRUCTURE
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Patent #:
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Issue Dt:
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10/10/2006
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Application #:
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10260824
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Filing Dt:
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09/27/2002
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Publication #:
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Pub Dt:
|
04/10/2003
| | | | |
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Title:
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METHOD OF FORMING A METAL-INSULATOR-METAL CAPACITOR IN AN INTERCONNECT CAVITY
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Patent #:
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Issue Dt:
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09/06/2005
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Application #:
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10261463
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Filing Dt:
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09/30/2002
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Publication #:
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Pub Dt:
|
04/01/2004
| | | | |
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Title:
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SILICON-RICH LOW THERMAL BUDGET SILICON NITRIDE FOR INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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05/18/2004
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Application #:
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10262654
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Filing Dt:
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09/30/2002
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Publication #:
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Pub Dt:
|
04/01/2004
| | | | |
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Title:
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ELECTRONIC FINGERPRINTING OF SEMICONDUCTOR INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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09/02/2003
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Application #:
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10263593
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Filing Dt:
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10/03/2002
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Publication #:
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Pub Dt:
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02/13/2003
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Title:
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APPARATUS FOR REMOVING PHOTORESIST EDGE BEADS FROM THIN FILM SUBSTRATES
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Patent #:
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Issue Dt:
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08/03/2004
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Application #:
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10263638
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Filing Dt:
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10/03/2002
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Publication #:
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Pub Dt:
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04/08/2004
| | | | |
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Title:
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PROCESS FOR SEMICONDUCTOR DEVICE FABRICATION IN WHICH A INSULATING LAYER IS FORMED ON A SEMICONDUCTOR SUBSTRATE
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Patent #:
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Issue Dt:
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01/20/2004
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Application #:
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10265751
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Filing Dt:
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10/07/2002
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Title:
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MULTI CHIP MODULE
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Patent #:
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Issue Dt:
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03/22/2005
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Application #:
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10265803
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Filing Dt:
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10/07/2002
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Publication #:
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Pub Dt:
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04/08/2004
| | | | |
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Title:
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BENT GATE TRANSISTOR MODELING
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Patent #:
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Issue Dt:
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03/15/2005
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Application #:
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10265856
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Filing Dt:
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10/07/2002
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Publication #:
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Pub Dt:
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04/08/2004
| | | | |
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Title:
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APPARATUS AND METHOD TO IMPROVE THE RESOLUTION OF PHOTOLITHOGRAPHY SYSTEMS BY IMPROVING THE TEMPERATURE STABILITY OF THE RETICLE
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10265867
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Filing Dt:
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10/07/2002
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Publication #:
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Pub Dt:
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02/13/2003
| | | | |
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Title:
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MOS transistor having an aluminum nitrade gate dielectric structure
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Patent #:
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Issue Dt:
|
04/19/2005
|
Application #:
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10266267
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Filing Dt:
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10/08/2002
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Publication #:
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Pub Dt:
|
04/08/2004
| | | | |
|
Title:
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ELECTRONIC COMPONENT PACKAGE
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Patent #:
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Issue Dt:
|
03/01/2005
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Application #:
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10267410
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Filing Dt:
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10/09/2002
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Publication #:
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Pub Dt:
|
04/15/2004
| | | | |
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Title:
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BUFFER METAL LAYER
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Patent #:
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Issue Dt:
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08/31/2004
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Application #:
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10267810
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Filing Dt:
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10/09/2002
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Publication #:
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Pub Dt:
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04/15/2004
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Title:
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LATERALLY INTERCONNECTING STRUCTURES
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Patent #:
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Issue Dt:
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04/06/2004
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Application #:
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10267814
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Filing Dt:
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10/09/2002
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Publication #:
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Pub Dt:
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04/15/2004
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Title:
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SUBSTRATE IMPEDANCE MEASUREMENT
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Patent #:
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Issue Dt:
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05/09/2006
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Application #:
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10268361
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Filing Dt:
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10/10/2002
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Publication #:
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Pub Dt:
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04/15/2004
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Title:
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MULTI CHIP MODULE ASSEMBLY
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10268735
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Filing Dt:
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10/10/2002
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Publication #:
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Pub Dt:
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04/03/2003
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Title:
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Barrier and seed layer system
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Patent #:
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Issue Dt:
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08/12/2003
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Application #:
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10268736
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Filing Dt:
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10/10/2002
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Publication #:
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Pub Dt:
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03/06/2003
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Title:
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SHALLOW JUNCTION FORMATION
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Patent #:
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Issue Dt:
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11/30/2004
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Application #:
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10271003
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Filing Dt:
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10/15/2002
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Publication #:
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Pub Dt:
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04/15/2004
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Title:
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INTEGRATED CIRCUIT PACKAGE DESIGN
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Patent #:
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Issue Dt:
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08/24/2004
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Application #:
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10271026
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Filing Dt:
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10/15/2002
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Publication #:
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Pub Dt:
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04/15/2004
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Title:
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PARALLEL CONFIGURABLE IP DESIGN METHODOLOGY
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Patent #:
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Issue Dt:
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04/12/2005
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Application #:
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10272182
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Filing Dt:
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10/16/2002
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Publication #:
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Pub Dt:
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04/22/2004
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Title:
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METHOD OF DELAY CALCULATION FOR VARIATION IN INTERCONNECT METAL PROCESS
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Patent #:
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Issue Dt:
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01/24/2006
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Application #:
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10272734
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Filing Dt:
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10/17/2002
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Publication #:
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Pub Dt:
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02/20/2003
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Title:
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METHOD FOR MAKING AN INTEGRATED CIRCUIT DEVICE WITH DIELECTRICALLY ISOLATED TUBS AND RELATED CIRCUIT
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Patent #:
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Issue Dt:
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11/04/2003
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Application #:
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10272767
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Filing Dt:
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10/16/2002
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Title:
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INTER-LAYER INTERCONNECTION STRUCTURE FOR LARGE ELECTRICAL CONNECTIONS
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Patent #:
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Issue Dt:
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04/20/2004
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Application #:
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10274765
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Filing Dt:
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10/21/2002
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Title:
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SEMICONDUCTOR DEVICE HAVING A HIGH-K GATE DIELECTRIC AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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03/22/2005
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Application #:
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10277025
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Filing Dt:
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10/21/2002
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Publication #:
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Pub Dt:
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04/22/2004
| | | | |
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Title:
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LAMINATE LOW K FILM
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Patent #:
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Issue Dt:
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09/06/2005
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Application #:
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10277398
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Filing Dt:
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10/21/2002
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Publication #:
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Pub Dt:
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04/22/2004
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Title:
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CLOCK TREE SYNTHESIS WITH SKEW FOR MEMORY DEVICES
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Patent #:
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Issue Dt:
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09/21/2004
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Application #:
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10278150
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Filing Dt:
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10/21/2002
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Publication #:
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Pub Dt:
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04/22/2004
| | | | |
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Title:
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METHOD OF DECREASING INSTANTANEOUS CURRENT WITHOUT AFFECTING TIMING
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Patent #:
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Issue Dt:
|
08/05/2003
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Application #:
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10278373
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Filing Dt:
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10/23/2002
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Title:
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ELECTRONIC SUBSTRATE
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Patent #:
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Issue Dt:
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11/25/2003
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Application #:
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10280566
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Filing Dt:
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10/25/2002
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Title:
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TOP GATED HEAT DISSIPATION
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Patent #:
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Issue Dt:
|
02/01/2005
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Application #:
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10283630
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Filing Dt:
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10/30/2002
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Title:
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THIN GATE DIELECTRIC FOR A CMOS TRANSISTOR AND METHOD OF FABRICATION THEREOF
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Patent #:
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Issue Dt:
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11/18/2003
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Application #:
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10283688
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Filing Dt:
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10/30/2002
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Title:
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INTEGRATED PROCESS TOOL MONITORING SYSTEM FOR SEMICONDUCTOR FABRICATION
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Patent #:
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Issue Dt:
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06/01/2004
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Application #:
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10283965
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Filing Dt:
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10/30/2002
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Publication #:
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Pub Dt:
|
05/06/2004
| | | | |
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Title:
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INTERLEAVED TERMINATION RING
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Patent #:
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Issue Dt:
|
01/22/2008
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Application #:
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10285301
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Filing Dt:
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10/31/2002
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Publication #:
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Pub Dt:
|
05/06/2004
| | | | |
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Title:
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VIRTUAL PATH FOR INTERCONNECT FABRIC USING BANDWIDTH PROCESS
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Patent #:
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Issue Dt:
|
12/07/2004
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Application #:
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10287668
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Filing Dt:
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11/04/2002
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Publication #:
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Pub Dt:
|
05/06/2004
| | | | |
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Title:
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BONDING PADS OVER INPUT CIRCUITS
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Patent #:
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Issue Dt:
|
03/16/2004
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Application #:
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10288410
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Filing Dt:
|
11/05/2002
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Title:
|
HIGH PERFORMANCE SI-GE DEVICE MODULE WITH CMOS TECHNOLOGY
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|
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Patent #:
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Issue Dt:
|
05/11/2004
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Application #:
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10289074
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Filing Dt:
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11/06/2002
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Publication #:
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Pub Dt:
|
05/06/2004
| | | | |
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Title:
|
DIE LOCATION ON UNGROUNDED WAFER FOR BACK-SIDE EMISSION MICROSCOPY
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Patent #:
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Issue Dt:
|
11/01/2005
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Application #:
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10290019
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Filing Dt:
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11/06/2002
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Publication #:
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Pub Dt:
|
05/06/2004
| | | | |
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Title:
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DESIGN METHODOLOGY FOR DUMMY LINES
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Patent #:
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Issue Dt:
|
01/04/2005
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Application #:
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10290437
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Filing Dt:
|
11/06/2002
|
|
Title:
|
METHOD AND APPARATUS FOR CLEANING DEPOSITED FILMS FROM THE EDGE OF A WAFER
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|
|
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Patent #:
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Issue Dt:
|
09/13/2005
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Application #:
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10290953
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Filing Dt:
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11/08/2002
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Publication #:
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Pub Dt:
|
05/13/2004
| | | | |
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Title:
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VIA CONSTRUCTION FOR STRUCTURAL SUPPORT
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|
|
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Patent #:
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Issue Dt:
|
09/05/2006
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Application #:
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10291982
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Filing Dt:
|
11/12/2002
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Publication #:
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Pub Dt:
|
05/13/2004
| | | | |
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Title:
|
OPTIMIZING DEPTHS OF CIRCUITS FOR BOOLEAN FUNCTIONS
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|
|
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Patent #:
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Issue Dt:
|
03/01/2005
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Application #:
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10293458
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Filing Dt:
|
11/13/2002
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Publication #:
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Pub Dt:
|
05/13/2004
| | | | |
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Title:
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SCATTER DOTS
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Patent #:
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Issue Dt:
|
03/22/2005
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Application #:
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10293631
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Filing Dt:
|
11/13/2002
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Title:
|
METHOD AND APPARATUS FOR MONITORING THE CONDITION OF A LUBRICATING MEDIUM
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|
|
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Patent #:
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Issue Dt:
|
11/16/2004
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Application #:
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10295489
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Filing Dt:
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11/15/2002
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Publication #:
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Pub Dt:
|
05/20/2004
| | | | |
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Title:
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FEED FORWARD LEVELING
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|
|
|
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Patent #:
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Issue Dt:
|
11/18/2003
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Application #:
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10298338
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Filing Dt:
|
11/14/2002
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Title:
|
ACTIVE HEAT SINK
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|
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Patent #:
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Issue Dt:
|
03/01/2005
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Application #:
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10298971
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Filing Dt:
|
11/18/2002
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Publication #:
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Pub Dt:
|
05/20/2004
| | | | |
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Title:
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TEST STRUCTURE
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Patent #:
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Issue Dt:
|
03/15/2005
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Application #:
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10299564
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Filing Dt:
|
11/19/2002
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Publication #:
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Pub Dt:
|
05/20/2004
| | | | |
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Title:
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METHOD TO FIND BOOLEAN FUNCTION SYMMETRIES
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|
|
|
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Patent #:
|
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Issue Dt:
|
07/13/2004
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Application #:
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10300254
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Filing Dt:
|
11/20/2002
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Publication #:
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Pub Dt:
|
05/29/2003
| | | | |
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Title:
|
LDMOS DEVICE HAVING A TAPERED OXIDE
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|
|
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Patent #:
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Issue Dt:
|
11/30/2004
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Application #:
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10300365
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Filing Dt:
|
11/20/2002
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Publication #:
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Pub Dt:
|
05/20/2004
| | | | |
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Title:
|
SEMICONDUCTOR DEVICE USING AN INSULATING LAYER HAVING A SEED LAYER
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|
|
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Patent #:
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Issue Dt:
|
07/25/2006
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Application #:
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10301069
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Filing Dt:
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11/20/2002
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Publication #:
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Pub Dt:
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05/20/2004
| | | | |
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Title:
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METHOD FOR REDUCING A PARASITIC GRAPH IN MOMENT COMPUTATION IN VLSI SYSTEMS
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|
|
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Patent #:
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Issue Dt:
|
04/04/2006
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Application #:
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10301182
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Filing Dt:
|
11/20/2002
|
|
Publication #:
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Pub Dt:
|
05/20/2004
| | | | |
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Title:
|
CHIP MANAGEMENT SYSTEM
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|
|
|
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Patent #:
|
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Issue Dt:
|
03/30/2004
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Application #:
|
10303280
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Filing Dt:
|
11/25/2002
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|
Publication #:
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Pub Dt:
|
06/12/2003
| | | | |
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Title:
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SEMICONDUCTOR MANUFACTURING USING MODULAR SUBSTRATES
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|
|
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Patent #:
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|
Issue Dt:
|
03/21/2006
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Application #:
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10304289
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Filing Dt:
|
11/26/2002
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Publication #:
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Pub Dt:
|
12/04/2003
| | | | |
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Title:
|
METACORES: DESIGN AND OPTIMIZATION TECHNIQUES
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|
|
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Patent #:
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|
Issue Dt:
|
12/02/2003
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Application #:
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10304631
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Filing Dt:
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11/26/2002
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Publication #:
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Pub Dt:
|
04/24/2003
| | | | |
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Title:
|
METHOD OF REDUCING SILICONE OXYNITRIDE GATE INSULATOR THICKNESS IN SOME TRANSISTORS OF A HYBRID INTEGRATED CIRCUIT TO OBTAIN INCREASED DIFFERENTIAL IN GATE INSULATOR THICKNESS WITH OTHER TRANSISTORS OF THE HYBRID CIRCUIT
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|
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Patent #:
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|
Issue Dt:
|
03/15/2005
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Application #:
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10304974
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Filing Dt:
|
11/26/2002
|
|
Publication #:
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|
Pub Dt:
|
05/27/2004
| | | | |
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Title:
|
THICK METAL TOP LAYER
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|
|
|
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Patent #:
|
|
Issue Dt:
|
07/27/2004
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Application #:
|
10305673
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Filing Dt:
|
11/26/2002
|
|
Publication #:
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Pub Dt:
|
05/27/2004
| | | | |
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Title:
|
AUTOMATIC CALIBRATION OF A MASKING PROCESS SIMULATOR
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|
|
|
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Patent #:
|
|
Issue Dt:
|
05/10/2005
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Application #:
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10306011
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Filing Dt:
|
11/26/2002
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Publication #:
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Pub Dt:
|
06/19/2003
| | | | |
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Title:
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METAL-INSULATOR-METAL CAPACITOR FORMED BY DAMASCENE PROCESSES BETWEEN METAL INTERCONNECT LAYERS AND METHOD OF FORMING SAME
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|
|
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Patent #:
|
|
Issue Dt:
|
07/22/2003
|
Application #:
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10306064
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Filing Dt:
|
11/27/2002
|
|
Title:
|
SOCKETLESS/BOARDLESS TEST INTERPOSER CARD
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|
