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04/27/2004
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10425155
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04/29/2003
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06/13/2006
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10426549
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04/30/2003
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11/04/2004
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07/25/2006
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10427609
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04/30/2003
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11/04/2004
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08/03/2004
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10428200
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04/30/2003
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05/27/2004
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08/28/2007
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10429312
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05/05/2003
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11/11/2004
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03/28/2006
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10429376
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05/05/2003
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11/11/2004
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08/16/2005
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05/08/2003
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03/28/2006
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10435168
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05/08/2003
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11/11/2004
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02/21/2006
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05/09/2003
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11/11/2004
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02/08/2005
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10435561
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05/09/2003
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11/06/2003
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12/06/2005
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10435870
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05/12/2003
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11/18/2004
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01/24/2006
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05/14/2003
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11/18/2004
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02/28/2006
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10439373
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05/15/2003
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11/18/2004
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03/23/2004
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10439863
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05/16/2003
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05/16/2006
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05/19/2003
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10/21/2004
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03/08/2005
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05/20/2003
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01/08/2008
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05/29/2003
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08/17/2004
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05/29/2003
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INTERCONNECT INTEGRATION
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03/01/2011
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06/02/2003
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12/02/2004
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02/19/2008
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06/02/2003
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03/28/2006
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06/02/2003
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12/02/2004
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03/08/2005
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06/03/2003
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06/27/2006
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06/03/2003
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12/09/2004
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09/20/2005
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06/02/2003
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12/02/2004
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06/28/2005
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10453821
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06/02/2003
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12/02/2004
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04/12/2005
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06/04/2003
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12/09/2004
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11/30/2004
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06/04/2003
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12/09/2004
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09/30/2008
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06/04/2003
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12/09/2004
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06/28/2005
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12/09/2004
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09/27/2005
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03/15/2005
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06/10/2003
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12/16/2004
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05/18/2004
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12/09/2004
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10/19/2004
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06/11/2003
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03/22/2005
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12/16/2004
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10/19/2004
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06/13/2003
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03/23/2004
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11/13/2003
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09/26/2006
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11/08/2005
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12/23/2004
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08/14/2008
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12/30/2004
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12/14/2004
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06/26/2003
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03/22/2005
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Pub Dt:
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05/20/2004
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Title:
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COPPER SILICIDE PASSIVATION FOR IMPROVED RELIABILITY
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Patent #:
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Issue Dt:
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08/25/2009
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Application #:
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10610002
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Filing Dt:
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06/30/2003
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Publication #:
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Pub Dt:
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12/30/2004
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Title:
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METHOD AND APPARATUS FOR MANUFACTURING MULTIPLE CIRCUIT PATTERNS USING A MULTIPLE PROJECT MASK
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Patent #:
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Issue Dt:
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08/07/2007
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Application #:
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10614307
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Filing Dt:
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07/02/2003
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Publication #:
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Pub Dt:
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01/06/2005
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Title:
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INTEGRATED CIRCUIT WITH INDUCTOR HAVING HORIZONTAL MAGNETIC FLUX LINES
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Patent #:
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Issue Dt:
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12/28/2004
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Application #:
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10614402
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Filing Dt:
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07/03/2003
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Title:
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INTEGRATD CIRCUIT DESIGN FOR BOTH INPUT OUTPUT LIMITED AND CORE LIMITED INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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04/19/2005
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Application #:
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10614776
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Filing Dt:
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07/07/2003
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Publication #:
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Pub Dt:
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01/15/2004
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Title:
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PROCESS FOR PLANARIZING UPPER SURFACE OF DAMASCENE WIRING STRUCTURE FOR INTEGRATED CIRCUIT STRUCTURES
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Patent #:
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Issue Dt:
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11/01/2005
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Application #:
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10615039
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Filing Dt:
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07/08/2003
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Publication #:
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Pub Dt:
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01/08/2004
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Title:
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LOW TEMPERATURE COEFFICIENT RESISTOR
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Patent #:
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Issue Dt:
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06/01/2004
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Application #:
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10615063
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Filing Dt:
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07/08/2003
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Title:
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ISOLATED STRIPLINE STRUCTURE
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Patent #:
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Issue Dt:
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01/24/2006
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Application #:
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10615558
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Filing Dt:
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07/08/2003
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Publication #:
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Pub Dt:
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01/13/2005
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Title:
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HARD MASK REMOVAL
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Patent #:
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Issue Dt:
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08/22/2006
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Application #:
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10616623
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Filing Dt:
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07/10/2003
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Publication #:
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Pub Dt:
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01/13/2005
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Title:
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OPTIMIZING IC CLOCK STRUCTURES BY MINIMIZING CLOCK UNCERTAINTY
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Patent #:
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Issue Dt:
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05/23/2006
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Application #:
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10619058
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Filing Dt:
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07/14/2003
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Publication #:
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Pub Dt:
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01/22/2004
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Title:
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METHOD OF ION IMPLANTATION FOR ACHIEVING DESIRED DOPANT CONCENTRATION
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Patent #:
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Issue Dt:
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07/04/2006
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Application #:
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10619978
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Filing Dt:
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07/14/2003
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Publication #:
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Pub Dt:
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04/15/2004
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Title:
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PROCESS FOR REMOVAL OF PHOTORESIST MASK USED FOR MAKING VIAS IN LOW K CARBON-DOPED SILICON OXIDE DIELECTRIC MATERIAL, AND FOR REMOVAL OF ETCH RESIDUES FROM FORMATION OF VIAS AND REMOVAL OF PHOTORESIST MASK
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Patent #:
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Issue Dt:
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09/20/2005
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Application #:
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10620057
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Filing Dt:
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07/15/2003
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Publication #:
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Pub Dt:
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12/16/2004
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Title:
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MEASUREMENT OF PACKAGE INTERCONNECT IMPEDANCE USING TESTER AND SUPPORTING TESTER
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Patent #:
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Issue Dt:
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08/23/2005
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Application #:
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10620074
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Filing Dt:
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07/14/2003
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Title:
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SEMICONDUCTOR PACKAGE HAVING A THERMALLY AND ELECTRICALLY CONNECTED HEATSPREADER
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Patent #:
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Issue Dt:
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06/22/2010
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Application #:
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10620581
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Filing Dt:
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07/15/2003
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Publication #:
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Pub Dt:
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01/20/2005
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Title:
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FLEXIBLE ARCHITECTURE COMPONENT (FAC) FOR EFFICIENT DATA INTEGRATION AND INFORMATION INTERCHANGE USING WEB SERVICES
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Patent #:
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Issue Dt:
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07/25/2006
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Application #:
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10621737
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Filing Dt:
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07/17/2003
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Publication #:
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Pub Dt:
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01/20/2005
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Title:
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METHOD AND APPARATUS OF IC IMPLEMENTATION BASED ON C++ LANGUAGE DESCRIPTION
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Patent #:
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Issue Dt:
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01/09/2007
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Application #:
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10623082
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Filing Dt:
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07/17/2003
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Title:
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INTER-LAYER INTERCONNECTION STRUCTURE FOR LARGE ELECTRICAL CONNECTIONS
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Patent #:
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Issue Dt:
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11/21/2006
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Application #:
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10623983
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Filing Dt:
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07/21/2003
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Publication #:
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Pub Dt:
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01/27/2005
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Title:
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SHIELDING STRUCTURE FOR USE IN A METAL-OXIDE-SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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08/22/2006
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Application #:
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10624347
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Filing Dt:
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07/22/2003
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Publication #:
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Pub Dt:
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01/27/2005
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Title:
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METHODS AND SYSTEMS FOR AUTOMATIC VERIFICATION OF SPECIFICATION DOCUMENT TO HARDWARE DESIGN
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Patent #:
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Issue Dt:
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06/06/2006
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Application #:
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10626825
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Filing Dt:
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07/23/2003
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Publication #:
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Pub Dt:
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07/15/2004
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Title:
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ARCHITECTURE FOR A SEA OF PLATFORMS
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Patent #:
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Issue Dt:
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10/25/2005
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Application #:
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10627289
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Filing Dt:
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07/25/2003
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Publication #:
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Pub Dt:
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01/27/2005
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Title:
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LOW GATE RESISTANCE LAYOUT PROCEDURE FOR RF TRANSISTOR DEVICES
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Patent #:
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Issue Dt:
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09/13/2005
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Application #:
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10628601
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Filing Dt:
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07/28/2003
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Publication #:
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Pub Dt:
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04/15/2004
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Title:
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METHOD AND APPARATUS FOR DETECTING BACKSIDE CONTAMINATION DURING FABRICATION OF A SEMICONDUCTOR WAFER
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Patent #:
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Issue Dt:
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06/28/2011
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Application #:
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10628614
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Filing Dt:
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07/28/2003
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Publication #:
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Pub Dt:
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02/03/2005
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Title:
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WAFER EDGE DEFECT INSPECTION USING CAPTURED IMAGE ANALYSIS
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Patent #:
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Issue Dt:
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01/10/2006
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Application #:
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10628986
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Filing Dt:
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07/28/2003
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Publication #:
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Pub Dt:
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02/03/2005
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Title:
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METHOD OF MAPPING LOGIC FAILURES IN AN INTEGRATED CIRCUIT DIE
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Patent #:
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Issue Dt:
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11/16/2004
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Application #:
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10629496
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Filing Dt:
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07/29/2003
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Title:
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SELECTIVE HIGH K DIELECTRICS REMOVAL
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Patent #:
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Issue Dt:
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10/19/2004
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Application #:
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10631328
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Filing Dt:
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07/30/2003
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Publication #:
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Pub Dt:
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06/24/2004
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Title:
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METHOD OF BALANCED COEFFICIENT OF THERMAL EXPANSION FOR FLIP CHIP BALL GRID ARRAY
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Patent #:
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Issue Dt:
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09/21/2004
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Application #:
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10631528
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Filing Dt:
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07/31/2003
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Title:
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METHOD AND APPARATUS FOR REDUCING MICROTRENCHING FOR BORDERLESS VIAS CREATED IN A DUAL DAMASCENE PROCESS
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Patent #:
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Issue Dt:
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02/28/2006
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Application #:
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10632622
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Filing Dt:
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07/31/2003
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Publication #:
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Pub Dt:
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02/03/2005
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Title:
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METHOD FOR PROVIDING CLOCK-NET AWARE DUMMY METAL USING DUMMY REGIONS
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Patent #:
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Issue Dt:
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04/25/2006
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Application #:
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10633334
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Filing Dt:
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08/01/2003
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Publication #:
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Pub Dt:
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02/03/2005
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Title:
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TEMPERATURE OPTIMIZATION OF A PHYSICAL VAPOR DEPOSITION PROCESS TO PREVENT EXTRUSION INTO OPENINGS
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Patent #:
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Issue Dt:
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01/17/2006
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Application #:
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10633856
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Filing Dt:
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08/04/2003
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Publication #:
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Pub Dt:
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02/10/2005
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Title:
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UNIVERSAL GATES FOR ICS AND TRANSFORMATION OF NETLISTS FOR THEIR IMPLEMENTATION
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Patent #:
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Issue Dt:
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02/20/2007
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Application #:
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10634416
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Filing Dt:
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08/04/2003
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Publication #:
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Pub Dt:
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02/10/2005
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Title:
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METHOD AND APPARATUS FOR INTEGRATING SIX SIGMA METHODOLOGY INTO INSPECTION RECEIVING PROCESS OF OUTSOURCED SUBASSEMBLIES, PARTS, AND MATERIALS: ACCEPTANCE, REJECTION, TRENDING, TRACKING AND CLOSED LOOP CORRECTIVE ACTION
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Patent #:
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Issue Dt:
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05/23/2006
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Application #:
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10634634
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Filing Dt:
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08/04/2003
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Publication #:
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Pub Dt:
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02/10/2005
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Title:
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METHOD AND APPARATUS FOR MAPPING PLATFORM-BASED DESIGN TO MULTIPLE FOUNDRY PROCESSES
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Patent #:
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Issue Dt:
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12/07/2004
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Application #:
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10635276
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Filing Dt:
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08/06/2003
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Title:
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SUBSTRATE VOLTAGE CONNECTION
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Patent #:
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Issue Dt:
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06/27/2006
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Application #:
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10637385
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Filing Dt:
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08/08/2003
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Publication #:
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Pub Dt:
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02/10/2005
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Title:
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METHOD TO IMPROVE THE CONTROL OF ELECTRO-POLISHING BY USE OF A PLATING ELECTRODE AN ELECTROLYTE BATH
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Patent #:
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Issue Dt:
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05/16/2006
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Application #:
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10638248
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Filing Dt:
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08/08/2003
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Publication #:
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Pub Dt:
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02/12/2004
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Title:
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HIGH-DENSITY INTER-DIE INTERCONNECT STRUCTURE
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Patent #:
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Issue Dt:
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02/22/2005
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Application #:
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10638772
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Filing Dt:
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08/11/2003
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Publication #:
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Pub Dt:
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04/08/2004
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Title:
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MULTI CHIP MODULE
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10640530
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Filing Dt:
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08/13/2003
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Publication #:
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Pub Dt:
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05/06/2004
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Title:
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Residual oxygen reduction system
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Patent #:
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Issue Dt:
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08/02/2005
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Application #:
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10640738
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Filing Dt:
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08/13/2003
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Publication #:
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Pub Dt:
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02/17/2005
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Title:
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METHOD OF ROUTING A REDISTRIBUTION LAYER TRACE IN AN INTEGRATED CIRCUIT DIE
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Patent #:
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Issue Dt:
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09/13/2005
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Application #:
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10640778
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Filing Dt:
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08/13/2003
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Publication #:
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Pub Dt:
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02/19/2004
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Title:
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METHOD OF DETECTING SPATIALLY CORRELATED VARIATIONS IN A PARAMETER OF AN INTEGRATED CIRCUIT DIE
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Patent #:
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Issue Dt:
|
01/17/2006
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Application #:
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10641768
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Filing Dt:
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08/14/2003
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Title:
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METHOD AND STRUCTURE FOR CREATING ULTRA LOW RESISTANCE DAMASCENE COPPER WIRING
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Patent #:
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Issue Dt:
|
11/30/2004
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Application #:
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10641799
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Filing Dt:
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08/15/2003
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Title:
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SYSTEM FOR YIELD ENHANCEMENT IN PROGRAMMABLE LOGIC
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Patent #:
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Issue Dt:
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01/31/2006
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Application #:
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10642706
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Filing Dt:
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08/18/2003
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Publication #:
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Pub Dt:
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09/23/2004
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Title:
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INSULATED BONDING WIRE TOOL FOR MICROELECTRONIC PACKAGING
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Patent #:
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Issue Dt:
|
05/17/2005
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Application #:
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10643123
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Filing Dt:
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08/18/2003
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Publication #:
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Pub Dt:
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02/24/2005
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Title:
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METHOD AND APPARATUS USING AN ON-CHIP RING OSCILLATOR FOR CHIP IDENTIFICATION
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Patent #:
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Issue Dt:
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07/19/2005
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Application #:
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10643687
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Filing Dt:
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08/19/2003
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Publication #:
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Pub Dt:
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05/13/2004
| | | | |
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Title:
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HIGH-K DIELECTRIC GATE MATERIAL UNIQUELY FORMED
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Patent #:
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Issue Dt:
|
07/17/2007
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Application #:
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10644116
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Filing Dt:
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08/20/2003
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Publication #:
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Pub Dt:
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02/24/2005
| | | | |
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Title:
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WHOLE-WAFER PHOTOEMISSION ANALYSIS
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|
