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Reel/Frame:	045216/0020			Pages:	334
		Recorded:	02/01/2018
Attorney Dkt #:	43172.01200
Conveyance:	SECURITY INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 3463
Page 27 of 35
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35

Patent #:	6984869	Issue Dt:	01/10/2006	Application #:	10730554	Filing Dt:	12/08/2003
Publication #:	US20050121746	Pub Dt:	06/09/2005
Title:	HIGH PERFORMANCE DIODE IMPLANTED VOLTAGE CONTROLLED P-TYPE DIFFUSION RESISTOR

Patent #:	7328417	Issue Dt:	02/05/2008	Application #:	10732395	Filing Dt:	12/09/2003
Publication #:	US20050125759	Pub Dt:	06/09/2005
Title:	CELL-BASED METHOD FOR CREATING SLOTTED METAL IN SEMICONDUCTOR DESIGNS

Patent #:	7148146	Issue Dt:	12/12/2006	Application #:	10733034	Filing Dt:	12/11/2003
Title:	METHOD OF FABRICATING AN INTEGRAL CAPACITOR AND GATE TRANSISTOR HAVING NITRIDE AND OXIDE POLISH STOP LAYERS USING CHEMICAL MECHANICAL POLISHING ELIMINATION

Patent #:	7653523	Issue Dt:	01/26/2010	Application #:	10736386	Filing Dt:	12/15/2003
Publication #:	US20050132308	Pub Dt:	06/16/2005
Title:	METHOD FOR CALCULATING HIGH-RESOLUTION WAFER PARAMETER PROFILES

Patent #:	7064062	Issue Dt:	06/20/2006	Application #:	10738761	Filing Dt:	12/16/2003
Publication #:	US20050127458	Pub Dt:	06/16/2005
Title:	INCORPORATING DOPANTS TO ENHANCE THE DIELECTRIC PROPERTIES OF METAL SILICATES

Patent #:	6988260	Issue Dt:	01/17/2006	Application #:	10739460	Filing Dt:	12/18/2003
Publication #:	US20050138597	Pub Dt:	06/23/2005
Title:	METHOD AND APPARATUS FOR OPTIMIZING FRAGMENTATION OF BOUNDARIES FOR OPTICAL PROXIMITY CORRECTION (OPC) PURPOSES

Patent #:	7269803	Issue Dt:	09/11/2007	Application #:	10740284	Filing Dt:	12/18/2003
Publication #:	US20050138595	Pub Dt:	06/23/2005
Title:	SYSTEM AND METHOD FOR MAPPING LOGICAL COMPONENTS TO PHYSICAL LOCATIONS IN AN INTEGRATED CIRCUIT DESIGN ENVIRONMENT

Patent #:	7039896	Issue Dt:	05/02/2006	Application #:	10740359	Filing Dt:	12/18/2003
Publication #:	US20050138596	Pub Dt:	06/23/2005
Title:	GRADIENT METHOD OF MASK EDGE CORRECTION

Patent #:	7328830	Issue Dt:	02/12/2008	Application #:	10741155	Filing Dt:	12/19/2003
Publication #:	US20040182915	Pub Dt:	09/23/2004
Title:	STRUCTURE AND METHOD FOR BONDING TO COPPER INTERCONNECT STRUCTURES

Patent #:	NONE	Issue Dt:		Application #:	10742916	Filing Dt:	12/23/2003
Publication #:	US20040163244	Pub Dt:	08/26/2004
Title:	Method of manufacturing and mounting electronic devices to limit the effects of parasitics

Patent #:	7098528	Issue Dt:	08/29/2006	Application #:	10744363	Filing Dt:	12/22/2003
Publication #:	US20050133935	Pub Dt:	06/23/2005
Title:	EMBEDDED REDISTRIBUTION INTERPOSER FOR FOOTPRINT COMPATIBLE CHIP PACKAGE CONVERSION

Patent #:	7456716	Issue Dt:	11/25/2008	Application #:	10746824	Filing Dt:	12/24/2003
Publication #:	US20050146413	Pub Dt:	07/07/2005
Title:	ELECTRICAL DEVICES HAVING ADJUSTABLE ELECTRICAL CHARACTERISTICS

Patent #:	7055117	Issue Dt:	05/30/2006	Application #:	10748068	Filing Dt:	12/29/2003
Publication #:	US20050149892	Pub Dt:	07/07/2005
Title:	SYSTEM AND METHOD FOR DEBUGGING SYSTEM-ON-CHIPS USING SINGLE OR N-CYCLE STEPPING

Patent #:	6969683	Issue Dt:	11/29/2005	Application #:	10750348	Filing Dt:	12/31/2003
Publication #:	US20040161927	Pub Dt:	08/19/2004
Title:	METHOD OF PREVENTING RESIST POISONING IN DUAL DAMASCENE STRUCTURES

Patent #:	NONE	Issue Dt:		Application #:	10755616	Filing Dt:	01/12/2004
Publication #:	US20050150682	Pub Dt:	07/14/2005
Title:	Method for electrical interconnection between printed wiring board layers using through holes with solid core conductive material

Patent #:	7065721	Issue Dt:	06/20/2006	Application #:	10757752	Filing Dt:	01/14/2004
Publication #:	US20050028123	Pub Dt:	02/03/2005
Title:	OPTIMIZED BOND OUT METHOD FOR FLIP CHIP WAFERS

Patent #:	7151059	Issue Dt:	12/19/2006	Application #:	10762788	Filing Dt:	01/22/2004
Publication #:	US20040150014	Pub Dt:	08/05/2004
Title:	MOS TRANSISTOR AND METHOD OF MANUFACTURE

Patent #:	7276767	Issue Dt:	10/02/2007	Application #:	10762962	Filing Dt:	01/22/2004
Publication #:	US20050040494	Pub Dt:	02/24/2005
Title:	THIN FILM RESISTOR DEVICE AND A METHOD OF MANUFACTURE THEREFOR

Patent #:	7037820	Issue Dt:	05/02/2006	Application #:	10767205	Filing Dt:	01/30/2004
Publication #:	US20050167702	Pub Dt:	08/04/2005
Title:	CROSS-FILL PATTERN FOR METAL FILL LEVELS, POWER SUPPLY FILTERING, AND ANALOG CIRUCIT SHIELDING

Patent #:	6888367	Issue Dt:	05/03/2005	Application #:	10767314	Filing Dt:	01/28/2004
Title:	METHOD AND APPARATUS FOR TESTING INTEGRATED CIRCUIT CORE MODULES

Patent #:	7076746	Issue Dt:	07/11/2006	Application #:	10768558	Filing Dt:	01/29/2004
Publication #:	US20050034086	Pub Dt:	02/10/2005
Title:	METHOD AND APPARATUS FOR MAPPING PLATFORM-BASED DESIGN TO MULTIPLE FOUNDRY PROCESSES

Patent #:	NONE	Issue Dt:		Application #:	10768588	Filing Dt:	01/29/2004
Publication #:	US20050034087	Pub Dt:	02/10/2005
Title:	Method and apparatus for mapping platform-based design to multiple foundry processes

Patent #:	7034653	Issue Dt:	04/25/2006	Application #:	10768771	Filing Dt:	01/30/2004
Publication #:	US20050168319	Pub Dt:	08/04/2005
Title:	SEMICONDUCTOR RESISTOR

Patent #:	7398501	Issue Dt:	07/08/2008	Application #:	10769510	Filing Dt:	01/30/2004
Publication #:	US20040187087	Pub Dt:	09/23/2004
Title:	SYSTEM AND METHOD FOR OPTIMIZING AN INTEGRATED CIRCUIT DESIGN

Patent #:	7277417	Issue Dt:	10/02/2007	Application #:	10771532	Filing Dt:	02/04/2004
Publication #:	US20040218620	Pub Dt:	11/04/2004
Title:	LOW POWER PROTOCOL FOR WIRELESS TERMINAL PEER-TO-PEER COMMUNICATIONS

Patent #:	7229923	Issue Dt:	06/12/2007	Application #:	10772133	Filing Dt:	02/03/2004
Publication #:	US20040157425	Pub Dt:	08/12/2004
Title:	MULTI-STEP PROCESS FOR FORMING A BARRIER FILM FOR USE IN COPPER LAYER FORMATION

Patent #:	7214568	Issue Dt:	05/08/2007	Application #:	10773614	Filing Dt:	02/06/2004
Publication #:	US20050173024	Pub Dt:	08/11/2005
Title:	SEMICONDUCTOR DEVICE CONFIGURED FOR REDUCING POST-FABRICATION DAMAGE

Patent #:	7078280	Issue Dt:	07/18/2006	Application #:	10773900	Filing Dt:	02/06/2004
Publication #:	US20040155264	Pub Dt:	08/12/2004
Title:	VERTICAL REPLACEMENT-GATE SILICON-ON-INSULATOR TRANSISTOR

Patent #:	6927125	Issue Dt:	08/09/2005	Application #:	10776752	Filing Dt:	02/11/2004
Publication #:	US20040159862	Pub Dt:	08/19/2004
Title:	INTERDIGITATED CAPACITOR AND METHOD OF MANUFACTURING THEREOF

Patent #:	6873171	Issue Dt:	03/29/2005	Application #:	10777250	Filing Dt:	02/12/2004
Publication #:	US20040160239	Pub Dt:	08/19/2004
Title:	INTEGRATED CIRCUIT EARLY LIFE FAILURE DETECTION BY MONITORING CHANGES IN CURRENT SIGNATURES

Patent #:	7005724	Issue Dt:	02/28/2006	Application #:	10778454	Filing Dt:	02/13/2004
Publication #:	US20050179116	Pub Dt:	08/18/2005
Title:	SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURE THEREFOR

Patent #:	6971944	Issue Dt:	12/06/2005	Application #:	10779966	Filing Dt:	02/17/2004
Publication #:	US20050181706	Pub Dt:	08/18/2005
Title:	METHOD AND CONTROL SYSTEM FOR IMPROVING CMP PROCESS BY DETECTING AND REACTING TO HARMONIC OSCILLATION

Patent #:	7074705	Issue Dt:	07/11/2006	Application #:	10786182	Filing Dt:	02/25/2004
Publication #:	US20050176232	Pub Dt:	08/11/2005
Title:	METHODS AND APPARATUS FOR INTEGRATED CIRCUIT BALL BONDING WITH SUBSTANTIALLY PERPENDICULAR WIRE BOND PROFILES

Patent #:	7086148	Issue Dt:	08/08/2006	Application #:	10787010	Filing Dt:	02/25/2004
Publication #:	US20050183265	Pub Dt:	08/25/2005
Title:	METHODS AND APPARATUS FOR WIRE BONDING WITH WIRE LENGTH ADJUSTMENT IN AN INTEGRATED CIRCUIT

Patent #:	7075174	Issue Dt:	07/11/2006	Application #:	10788162	Filing Dt:	02/26/2004
Publication #:	US20050191793	Pub Dt:	09/01/2005
Title:	SEMICONDUCTOR PACKAGING TECHNIQUES FOR USE WITH NON-CERAMIC PACKAGES

Patent #:	7164200	Issue Dt:	01/16/2007	Application #:	10788678	Filing Dt:	02/27/2004
Publication #:	US20050189616	Pub Dt:	09/01/2005
Title:	TECHNIQUES FOR REDUCING BOWING IN POWER TRANSISTOR DEVICES

Patent #:	NONE	Issue Dt:		Application #:	10791337	Filing Dt:	03/01/2004
Publication #:	US20050191812	Pub Dt:	09/01/2005
Title:	Spacer-less transistor integration scheme for high-k gate dielectrics and small gate-to-gate spaces applicable to Si, SiGe strained silicon schemes

Patent #:	7131103	Issue Dt:	10/31/2006	Application #:	10793055	Filing Dt:	03/04/2004
Publication #:	US20050198608	Pub Dt:	09/08/2005
Title:	CONDUCTOR STACK SHIFTING

Patent #:	6931297	Issue Dt:	08/16/2005	Application #:	10794225	Filing Dt:	03/05/2004
Publication #:	US20050197728	Pub Dt:	09/08/2005
Title:	FEATURE TARGETED INSPECTION

Patent #:	7264906	Issue Dt:	09/04/2007	Application #:	10794683	Filing Dt:	03/05/2004
Publication #:	US20050196681	Pub Dt:	09/08/2005
Title:	OPC BASED ILLUMINATION OPTIMIZATION WITH MASK ERROR CONSTRAINTS

Patent #:	6951510	Issue Dt:	10/04/2005	Application #:	10799279	Filing Dt:	03/12/2004
Publication #:	US20050202761	Pub Dt:	09/15/2005
Title:	CHEMICAL MECHANICAL POLISHING PAD WITH GROOVES ALTERNATING BETWEEN A LARGER GROOVE SIZE AND A SMALLER GROOVE SIZE

Patent #:	7299158	Issue Dt:	11/20/2007	Application #:	10799851	Filing Dt:	03/12/2004
Publication #:	US20050203862	Pub Dt:	09/15/2005
Title:	PROCESS CONTROL DATA COLLECTION

Patent #:	7325222	Issue Dt:	01/29/2008	Application #:	10800219	Filing Dt:	03/12/2004
Publication #:	US20050204328	Pub Dt:	09/15/2005
Title:	METHOD AND APPARATUS FOR VERIFYING THE POST-OPTICAL PROXIMITY CORRECTED MASK WAFER IMAGE SENSITIVITY TO RETICLE MANUFACTURING ERRORS

Patent #:	7395522	Issue Dt:	07/01/2008	Application #:	10801310	Filing Dt:	03/16/2004
Publication #:	US20050229144	Pub Dt:	10/13/2005
Title:	YIELD PROFILE MANIPULATOR

Patent #:	NONE	Issue Dt:		Application #:	10802522	Filing Dt:	03/17/2004
Publication #:	US20040238960	Pub Dt:	12/02/2004
Title:	Interconnect integration

Patent #:	7398486	Issue Dt:	07/08/2008	Application #:	10803516	Filing Dt:	03/17/2004
Publication #:	US20050210422	Pub Dt:	09/22/2005
Title:	METHOD AND APPARATUS FOR PERFORMING LOGICAL TRANSFORMATIONS FOR GLOBAL ROUTING

Patent #:	7081296	Issue Dt:	07/25/2006	Application #:	10804980	Filing Dt:	03/18/2004
Publication #:	US20040175947	Pub Dt:	09/09/2004
Title:	METHOD FOR GROWING THIN FILMS

Patent #:	7114133	Issue Dt:	09/26/2006	Application #:	10809939	Filing Dt:	03/25/2004
Publication #:	US20040221248	Pub Dt:	11/04/2004
Title:	BROKEN SYMMETRY FOR OPTIMIZATION OF RESOURCE FABRIC IN A SEA-OF-PLATFORM ARCHITECTURE

Patent #:	7200832	Issue Dt:	04/03/2007	Application #:	10810294	Filing Dt:	03/26/2004
Publication #:	US20050229132	Pub Dt:	10/13/2005
Title:	MACRO CELL FOR INTEGRATED CIRCUIT PHYSICAL LAYER INTERFACE

Patent #:	7041561	Issue Dt:	05/09/2006	Application #:	10814062	Filing Dt:	03/31/2004
Publication #:	US20050221563	Pub Dt:	10/06/2005
Title:	ENHANCED SUBSTRATE CONTACT FOR A SEMICONDUCTOR DEVICE

Patent #:	6855991	Issue Dt:	02/15/2005	Application #:	10814680	Filing Dt:	03/31/2004
Publication #:	US20040183140	Pub Dt:	09/23/2004
Title:	SEMICONDUCTOR DEVICE HAVING A DOPED LATTICE MATCHING LAYER AND A METHOD OF MANUFACTURE THEREFOR

Patent #:	NONE	Issue Dt:		Application #:	10814682	Filing Dt:	03/31/2004
Publication #:	US20040183160	Pub Dt:	09/23/2004
Title:	Semiconductor device having a doped lattice matching layer and a method of manufacture therefor

Patent #:	7030472	Issue Dt:	04/18/2006	Application #:	10816060	Filing Dt:	04/01/2004
Publication #:	US20050224926	Pub Dt:	10/13/2005
Title:	INTEGRATED CIRCUIT DEVICE HAVING FLEXIBLE LEADFRAME

Patent #:	7620743	Issue Dt:	11/17/2009	Application #:	10817419	Filing Dt:	04/01/2004
Publication #:	US20050223388	Pub Dt:	10/06/2005
Title:	SYSTEM AND METHOD FOR IMPLEMENTING MULTIPLE INSTANTIATED CONFIGURABLE PERIPHERALS IN A CIRCUIT DESIGN

Patent #:	7242056	Issue Dt:	07/10/2007	Application #:	10819253	Filing Dt:	04/05/2004
Publication #:	US20040188737	Pub Dt:	09/30/2004
Title:	STRUCTURE AND FABRICATION METHOD FOR CAPACITORS INTEGRATIBLE WITH VERTICAL REPLACEMENT GATE TRANSISTORS

Patent #:	7185301	Issue Dt:	02/27/2007	Application #:	10819254	Filing Dt:	04/06/2004
Publication #:	US20050226056	Pub Dt:	10/13/2005
Title:	GENERIC METHOD AND APPARATUS FOR IMPLEMENTING SOURCE SYNCHRONOUS INTERFACE IN PLATFORM ASIC

Patent #:	7173328	Issue Dt:	02/06/2007	Application #:	10819684	Filing Dt:	04/06/2004
Publication #:	US20050224964	Pub Dt:	10/13/2005
Title:	INTEGRATED CIRCUIT PACKAGE AND METHOD HAVING WIRE-BONDED INTRA-DIE ELECTRICAL CONNECTIONS

Patent #:	7119432	Issue Dt:	10/10/2006	Application #:	10820494	Filing Dt:	04/07/2004
Publication #:	US20050224955	Pub Dt:	10/13/2005
Title:	METHOD AND APPARATUS FOR ESTABLISHING IMPROVED THERMAL COMMUNICATION BETWEEN A DIE AND A HEATSPREADER IN A SEMICONDUCTOR PACKAGE

Patent #:	7103858	Issue Dt:	09/05/2006	Application #:	10824509	Filing Dt:	04/14/2004
Publication #:	US20050235244	Pub Dt:	10/20/2005
Title:	PROCESS AND APPARATUS FOR CHARACTERIZING INTELLECTUAL PROPERTY FOR INTEGRATION INTO AN IC PLATFORM ENVIRONMENT

Patent #:	7270942	Issue Dt:	09/18/2007	Application #:	10825342	Filing Dt:	04/14/2004
Publication #:	US20050088640	Pub Dt:	04/28/2005
Title:	OPTIMIZED MIRROR DESIGN FOR OPTICAL DIRECT WRITE

Patent #:	7219317	Issue Dt:	05/15/2007	Application #:	10828408	Filing Dt:	04/19/2004
Publication #:	US20050235234	Pub Dt:	10/20/2005
Title:	METHOD AND COMPUTER PROGRAM FOR VERIFYING AN INCREMENTAL CHANGE TO AN INTEGRATED CIRCUIT DESIGN

Patent #:	NONE	Issue Dt:		Application #:	10828993	Filing Dt:	04/21/2004
Publication #:	US20040195684	Pub Dt:	10/07/2004
Title:	Method for making a radio frequency component and component produced thereby

Patent #:	6868355	Issue Dt:	03/15/2005	Application #:	10829408	Filing Dt:	04/20/2004
Publication #:	US20040199349	Pub Dt:	10/07/2004
Title:	AUTOMATIC CALIBRATION OF A MASKING PROCESS SIMULATOR

Patent #:	7210113	Issue Dt:	04/24/2007	Application #:	10830542	Filing Dt:	04/23/2004
Publication #:	US20050240889	Pub Dt:	10/27/2005
Title:	PROCESS AND APPARATUS FOR PLACING CELLS IN AN IC FLOORPLAN

Patent #:	7219321	Issue Dt:	05/15/2007	Application #:	10830739	Filing Dt:	04/25/2004
Publication #:	US20050240746	Pub Dt:	10/27/2005
Title:	PROCESS AND APPARATUS FOR MEMORY MAPPING

Patent #:	7606692	Issue Dt:	10/20/2009	Application #:	10832226	Filing Dt:	04/26/2004
Publication #:	US20050240387	Pub Dt:	10/27/2005
Title:	GATE-LEVEL NETLIST REDUCTION FOR SIMULATING TARGET MODULES OF A DESIGN

Patent #:	NONE	Issue Dt:		Application #:	10838384	Filing Dt:	05/04/2004
Publication #:	US20040203212	Pub Dt:	10/14/2004
Title:	Implementation of Si-Ge HBT module with CMOS process

Patent #:	7584437	Issue Dt:	09/01/2009	Application #:	10840534	Filing Dt:	05/06/2004
Publication #:	US20050251772	Pub Dt:	11/10/2005
Title:	ASSURING CORRECT DATA ENTRY TO GENERATE SHELLS FOR A SEMICONDUCTOR PLATFORM

Patent #:	7157365	Issue Dt:	01/02/2007	Application #:	10842139	Filing Dt:	05/10/2004
Publication #:	US20050248033	Pub Dt:	11/10/2005
Title:	SEMICONDUCTOR DEVICE HAVING A DUMMY CONDUCTIVE VIA AND A METHOD OF MANUFACTURE THEREFOR

Patent #:	7086015	Issue Dt:	08/01/2006	Application #:	10844664	Filing Dt:	05/12/2004
Publication #:	US20050257180	Pub Dt:	11/17/2005
Title:	METHOD OF OPTIMIZING RTL CODE FOR MULTIPLEX STRUCTURES

Patent #:	7360133	Issue Dt:	04/15/2008	Application #:	10847691	Filing Dt:	05/18/2004
Publication #:	US20050262460	Pub Dt:	11/24/2005
Title:	METHOD FOR CREATING A JTAG TAP CONTROLLER IN A SLICE FOR USE DURING CUSTOM INSTANCE CREATION TO AVOID THE NEED OF A BOUNDARY SCAN SYNTHESIS TOOL

Patent #:	7188330	Issue Dt:	03/06/2007	Application #:	10847692	Filing Dt:	05/18/2004
Publication #:	US20050262465	Pub Dt:	11/24/2005
Title:	HANDLING OF UNUSED COREWARE WITH EMBEDDED BOUNDARY SCAN CHAINS TO AVOID THE NEED OF A BOUNDARY SCAN SYNTHESIS TOOL DURING CUSTOM INSTANCE CREATION

Patent #:	7081419	Issue Dt:	07/25/2006	Application #:	10847789	Filing Dt:	05/18/2004
Publication #:	US20040238905	Pub Dt:	12/02/2004
Title:	NOVEL GATE DIELECTRIC STRUCTURE FOR REDUCING BORON PENETRATION AND CURRENT LEAKAGE

Patent #:	7117475	Issue Dt:	10/03/2006	Application #:	10848994	Filing Dt:	05/18/2004
Publication #:	US20050262467	Pub Dt:	11/24/2005
Title:	METHOD AND SYSTEM FOR UTILIZING AN ISOFOCAL CONTOUR TO PERFORM OPTICAL AND PROCESS CORRECTIONS

Patent #:	7235489	Issue Dt:	06/26/2007	Application #:	10850812	Filing Dt:	05/21/2004
Publication #:	US20050260843	Pub Dt:	11/24/2005
Title:	DEVICE AND METHOD TO ELIMINATE SHORTING INDUCED BY VIA TO METAL MISALIGNMENT

Patent #:	7042242	Issue Dt:	05/09/2006	Application #:	10852902	Filing Dt:	05/25/2004
Publication #:	US20050264314	Pub Dt:	12/01/2005
Title:	BUILT-IN SELF TEST TECHNIQUE FOR PROGRAMMABLE IMPEDANCE DRIVERS FOR RAPIDCHIP AND ASIC DRIVERS

Patent #:	6894400	Issue Dt:	05/17/2005	Application #:	10853395	Filing Dt:	05/25/2004
Title:	ROBUST ELECTRONIC DEVICE PACKAGES

Patent #:	7368326	Issue Dt:	05/06/2008	Application #:	10855148	Filing Dt:	05/27/2004
Publication #:	US20050153532	Pub Dt:	07/14/2005
Title:	METHODS AND APPARATUS TO REDUCE GROWTH FORMATIONS ON PLATED CONDUCTIVE LEADS

Patent #:	7404146	Issue Dt:	07/22/2008	Application #:	10855458	Filing Dt:	05/27/2004
Publication #:	US20050268251	Pub Dt:	12/01/2005
Title:	INPUT DEVICE FOR PORTABLE HANDSET

Patent #:	6998638	Issue Dt:	02/14/2006	Application #:	10856213	Filing Dt:	05/28/2004
Publication #:	US20040217487	Pub Dt:	11/04/2004
Title:	TEST STRUCTURE FOR DETECTING BONDING-INDUCED CRACKS

Patent #:	7065734	Issue Dt:	06/20/2006	Application #:	10859857	Filing Dt:	06/02/2004
Publication #:	US20050273751	Pub Dt:	12/08/2005
Title:	METHOD OF GENERATING MULTIPLE HARDWARE DESCRIPTION LANGUAGE CONFIGURATIONS FOR A PHASE LOCKED LOOP FROM A SINGLE GENETIC MODEL FOR INTEGRATED CIRCUIT DESIGN

Patent #:	7412678	Issue Dt:	08/12/2008	Application #:	10859874	Filing Dt:	06/02/2004
Publication #:	US20050273741	Pub Dt:	12/08/2005
Title:	METHOD AND COMPUTER PROGRAM FOR MANAGEMENT OF SYNCHRONOUS AND ASYNCHRONOUS CLOCK DOMAIN CROSSING IN INTEGRATED CIRCUIT DESIGN

Patent #:	7223616	Issue Dt:	05/29/2007	Application #:	10862049	Filing Dt:	06/04/2004
Publication #:	US20050272174	Pub Dt:	12/08/2005
Title:	TEST STRUCTURES IN UNUSED AREAS OF SEMICONDUCTOR INTEGRATED CIRCUITS AND METHODS FOR DESIGNING THE SAME

Patent #:	7436060	Issue Dt:	10/14/2008	Application #:	10865179	Filing Dt:	06/09/2004
Publication #:	US20050275086	Pub Dt:	12/15/2005
Title:	SEMICONDUCTOR PACKAGE AND PROCESS UTILIZING PRE-FORMED MOLD CAP AND HEATSPREADER ASSEMBLY

Patent #:	7039556	Issue Dt:	05/02/2006	Application #:	10867003	Filing Dt:	06/14/2004
Publication #:	US20050288896	Pub Dt:	12/29/2005
Title:	SUBSTRATE PROFILE ANALYSIS

Patent #:	7013192	Issue Dt:	03/14/2006	Application #:	10867014	Filing Dt:	06/14/2004
Publication #:	US20050278678	Pub Dt:	12/15/2005
Title:	SUBSTRATE CONTACT ANALYSIS

Patent #:	NONE	Issue Dt:		Application #:	10870834	Filing Dt:	06/17/2004
Publication #:	US20040241947	Pub Dt:	12/02/2004
Title:	Process for semiconductor device fabrication in which a insulating layer is formed on a semiconductor substrate

Patent #:	7610495	Issue Dt:	10/27/2009	Application #:	10874834	Filing Dt:	06/23/2004
Publication #:	US20050114721	Pub Dt:	05/26/2005
Title:	METHOD AND APPARATUS FOR POWER MANAGEMENT USING TRANSMISSION MODE WITH REDUCED POWER

Patent #:	7494888	Issue Dt:	02/24/2009	Application #:	10875029	Filing Dt:	06/23/2004
Publication #:	US20050287786	Pub Dt:	12/29/2005
Title:	DEVICE AND METHOD USING ISOTOPICALLY ENRICHED SILICON

Patent #:	7168052	Issue Dt:	01/23/2007	Application #:	10875128	Filing Dt:	06/23/2004
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Title:	YIELD DRIVEN MEMORY PLACEMENT SYSTEM

Patent #:	7223677	Issue Dt:	05/29/2007	Application #:	10876183	Filing Dt:	06/24/2004
Publication #:	US20040235313	Pub Dt:	11/25/2004
Title:	PROCESS FOR FABRICATING A SEMICONDUCTOR DEVICE HAVING AN INSULATING LAYER FORMED OVER A SEMICONDUCTOR SUBSTRATE

Patent #:	7157361	Issue Dt:	01/02/2007	Application #:	10878157	Filing Dt:	06/28/2004
Publication #:	US20060014370	Pub Dt:	01/19/2006
Title:	METHODS FOR PROCESSING INTEGRATED CIRCUIT PACKAGES FORMED USING ELECTROPLATING AND APPARATUS MADE THEREFROM

Patent #:	7148540	Issue Dt:	12/12/2006	Application #:	10878857	Filing Dt:	06/28/2004
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Title:	GRADED CONDUCTIVE STRUCTURE FOR USE IN A METAL-OXIDE-SEMICONDUCTOR DEVICE

Patent #:	7198546	Issue Dt:	04/03/2007	Application #:	10879629	Filing Dt:	06/29/2004
Publication #:	US20050287927	Pub Dt:	12/29/2005
Title:	METHOD TO MONITOR PAD WEAR IN CMP PROCESSING

Patent #:	7181710	Issue Dt:	02/20/2007	Application #:	10879768	Filing Dt:	06/28/2004
Publication #:	US20050289491	Pub Dt:	12/29/2005
Title:	DEVICE FOR ESTIMATING CELL DELAY FROM A TABLE WITH ADDED VOLTAGE SWING

Patent #:	7745927	Issue Dt:	06/29/2010	Application #:	10879909	Filing Dt:	06/29/2004
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Title:	HEAT SINK FORMED OF MULTIPLE METAL LAYERS ON BACKSIDE OF INTEGRATED CIRCUIT DIE

Patent #:	7346879	Issue Dt:	03/18/2008	Application #:	10880216	Filing Dt:	06/29/2004
Publication #:	US20050289496	Pub Dt:	12/29/2005
Title:	SYMMETRIC SIGNAL DISTRIBUTION THROUGH ABUTMENT CONNECTION

Patent #:	7009305	Issue Dt:	03/07/2006	Application #:	10881191	Filing Dt:	06/30/2004
Publication #:	US20060001157	Pub Dt:	01/05/2006
Title:	METHODS AND APPARATUS FOR INTEGRATED CIRCUIT BALL BONDING USING STACKED BALL BUMPS

Patent #:	7015096	Issue Dt:	03/21/2006	Application #:	10883137	Filing Dt:	07/01/2004
Title:	BIMETALLIC OXIDE COMPOSITIONS FOR GATE DIELECTRICS

100

Patent #:	7022581	Issue Dt:	04/04/2006	Application #:	10886763	Filing Dt:	07/08/2004
Publication #:	US20060006496	Pub Dt:	01/12/2006
Title:	INTERDIGITADED CAPACITORS

Assignors

HILCO PATENT ACQUISITION 56, LLC

Exec Dt:

01/24/2018

BELL SEMICONDUCTOR, LLC

Exec Dt:

01/24/2018

BELL NORTHERN RESEARCH, LLC

Exec Dt:

01/24/2018

Assignee

CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT

225 W. WASHINGTON ST., 9TH FLOOR

CHICAGO, ILLINOIS 60606

Correspondence name and address
	JAVIER J. RAMOS
	1850 K STREET, NW, SUITE 1100
	MILBANK, TWEED, HADLEY & MCCLOY, LLP
	WASHINGTON, DC 20006

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