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Patent #:
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Issue Dt:
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10/03/2006
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Application #:
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10887599
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Filing Dt:
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07/09/2004
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Publication #:
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Pub Dt:
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01/12/2006
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Title:
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PLACEMENT OF A CLOCK SIGNAL SUPPLY NETWORK DURING DESIGN OF INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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04/29/2008
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Application #:
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10889901
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Filing Dt:
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07/13/2004
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Publication #:
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Pub Dt:
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01/19/2006
| | | | |
Title:
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DAMASCENE REPLACEMENT METAL GATE PROCESS WITH CONTROLLED GATE PROFILE AND LENGTH USING SI1-XGEX AS SACRIFICIAL MATERIAL
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Patent #:
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Issue Dt:
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07/04/2006
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10893659
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07/16/2004
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Publication #:
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Pub Dt:
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12/16/2004
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Title:
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DUAL LAYER BARRIER FILM TECHNIQUES TO PREVENT RESIST POISONING
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Patent #:
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08/19/2008
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10894781
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Filing Dt:
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07/20/2004
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Publication #:
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Pub Dt:
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01/26/2006
| | | | |
Title:
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METHOD AND SYSTEM FOR OUTPUTTING A SEQUENCE OF COMMANDS AND DATA DESCRIBED BY A FLOWCHART
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Patent #:
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04/25/2006
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Application #:
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10895574
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Filing Dt:
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07/21/2004
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Publication #:
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Pub Dt:
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01/26/2006
| | | | |
Title:
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CARRIER HEAD FOR CHEMICAL MECHANICAL POLISHING
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Patent #:
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Issue Dt:
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12/15/2009
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10897655
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Filing Dt:
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07/22/2004
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Publication #:
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Pub Dt:
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02/09/2006
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Title:
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SPECIAL ENGINEERING CHANGE ORDER CELLS
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Patent #:
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Issue Dt:
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11/08/2005
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Application #:
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10898792
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Filing Dt:
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07/26/2004
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Title:
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OPERATION OF SEMICONDUCTOR DEVICES SUBJECT TO HOT CARRIER INJECTION
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Patent #:
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05/08/2007
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10900224
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Filing Dt:
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07/27/2004
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Publication #:
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Pub Dt:
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10/20/2005
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Title:
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METHOD OF GENERATING TEST PATTERNS TO EFFICIENTLY SCREEN INLINE RESISTANCE DELAY DEFECTS IN COMPLEX ASICS
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Patent #:
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Issue Dt:
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12/11/2007
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10900642
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07/27/2004
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Publication #:
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Pub Dt:
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01/20/2005
| | | | |
Title:
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SELF-TIMED RELIABILITY AND YIELD VEHICLE WITH GATED DATA AND CLOCK
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Patent #:
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Issue Dt:
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08/29/2006
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Application #:
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10900869
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Filing Dt:
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07/28/2004
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Publication #:
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02/02/2006
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Title:
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EMBEDDED STRAIN GAUGE IN PRINTED CIRCUIT BOARDS
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Patent #:
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Issue Dt:
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06/13/2006
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Application #:
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10901841
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Filing Dt:
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07/28/2004
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Publication #:
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Pub Dt:
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02/02/2006
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Title:
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METHOD OF AUTOMATED REPAIR OF CROSSTALK VIOLATIONS AND TIMING VIOLATIONS IN AN INTEGRATED CIRCUIT DESIGN
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Patent #:
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Issue Dt:
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09/26/2006
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Application #:
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10902332
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Filing Dt:
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07/29/2004
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Publication #:
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Pub Dt:
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02/02/2006
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Title:
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APPARATUS AND METHOD FOR IN-SITU MEASURING OF VIBRATIONAL ENERGY IN A PROCESS BATH OF A VIBRATIONAL CLEANING SYSTEM
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Patent #:
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Issue Dt:
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02/12/2008
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10902987
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Filing Dt:
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07/30/2004
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Publication #:
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Pub Dt:
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02/02/2006
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Title:
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ENGINEERING CHANGE ORDER SCENARIO MANAGER
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Patent #:
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02/06/2007
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10903836
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Filing Dt:
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07/30/2004
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Publication #:
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Pub Dt:
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02/02/2006
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Title:
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ACCURATE DENSITY CALCULATION WITH DENSITY VIEWS IN LAYOUT DATABASES
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Patent #:
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Issue Dt:
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08/03/2010
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10903938
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Filing Dt:
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07/30/2004
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Publication #:
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Pub Dt:
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02/02/2006
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Title:
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METAL CAPACITOR STACKED WITH A MOS CAPACITOR TO PROVIDE INCREASED CAPACITANCE DENSITY
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Patent #:
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Issue Dt:
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09/30/2008
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Application #:
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10909603
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Filing Dt:
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08/02/2004
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Publication #:
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Pub Dt:
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02/02/2006
| | | | |
Title:
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DISABLING UNUSED IO RESOURCES IN PLATFORM-BASED INTEGRATED CIRCUITS
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10909821
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Filing Dt:
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08/02/2004
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Publication #:
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Pub Dt:
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02/10/2005
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Title:
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Semiconductor wafer chuck assembly for a semiconductor processing device
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Patent #:
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Issue Dt:
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09/12/2006
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Application #:
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10914657
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Filing Dt:
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08/09/2004
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Publication #:
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Pub Dt:
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02/09/2006
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Title:
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METHOD OF SIZING VIA ARRAYS AND INTERCONNECTS TO REDUCE ROUTING CONGESTION IN FLIP CHIP INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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01/23/2007
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Application #:
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10914921
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Filing Dt:
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08/10/2004
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Publication #:
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Pub Dt:
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02/16/2006
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Title:
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METHOD AND APPARATUS FOR DETECTING NETS PHYSICALLY CHANGED AND ELECTRICALLY AFFECTED BY DESIGN ECO
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Patent #:
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Issue Dt:
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07/25/2006
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Application #:
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10915719
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Filing Dt:
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08/10/2004
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Publication #:
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Pub Dt:
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02/16/2006
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Title:
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INTERCONNECT DIELECTRIC TUNING
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Patent #:
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Issue Dt:
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07/29/2008
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Application #:
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10916322
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Filing Dt:
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08/11/2004
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Publication #:
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Pub Dt:
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02/16/2006
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Title:
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APPLICATION OF GATE EDGE LINER TO MAINTAIN GATE LENGTH CD IN A REPLACEMENT GATE TRANSISTOR FLOW
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Patent #:
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Issue Dt:
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10/03/2006
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Application #:
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10918933
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Filing Dt:
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08/16/2004
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Publication #:
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Pub Dt:
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02/16/2006
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Title:
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METHODS FOR OPTIMIZING PACKAGE AND SILICON CO-DESIGN OF INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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03/18/2008
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10918981
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08/16/2004
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Publication #:
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Pub Dt:
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02/03/2005
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Title:
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INCREASED QUALITY FACTOR OF A VARACTOR IN AN INTEGRATED CIRCUIT VIA A HIGH CONDUCTIVE REGION IN A WELL
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Patent #:
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Issue Dt:
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03/04/2008
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Application #:
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10919591
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Filing Dt:
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08/17/2004
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Publication #:
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Pub Dt:
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02/23/2006
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Title:
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METALLIZATION PERFORMANCE IN ELECTRONIC DEVICES
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Patent #:
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Issue Dt:
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08/08/2006
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10920656
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Filing Dt:
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08/18/2004
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Publication #:
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Pub Dt:
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02/23/2006
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Title:
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METAL-OXIDE-SEMICONDUCTOR DEVICE HAVING AN ENHANCED SHIELDING STRUCTURE
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10921497
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Filing Dt:
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08/18/2004
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Publication #:
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Pub Dt:
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01/27/2005
| | | | |
Title:
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Multi-level redistribution layer traces for reducing current crowding in flipchip solder bumps
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Patent #:
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Issue Dt:
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10/31/2006
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10921538
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Filing Dt:
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08/18/2004
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Publication #:
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Pub Dt:
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02/24/2005
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Title:
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FAILURE ANALYSIS VEHICLE FOR YIELD ENHANCEMENT WITH SELF TEST AT SPEED BURNIN CAPABILITY FOR RELIABILITY TESTING
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Patent #:
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Issue Dt:
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09/12/2006
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Application #:
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10924531
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Filing Dt:
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08/23/2004
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Publication #:
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Pub Dt:
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01/27/2005
| | | | |
Title:
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METHOD OF FINDING CRITICAL NETS IN AN INTEGRATED CIRCUIT DESIGN
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Patent #:
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Issue Dt:
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12/25/2007
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Application #:
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10925497
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Filing Dt:
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08/24/2004
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Publication #:
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Pub Dt:
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03/02/2006
| | | | |
Title:
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WAFER EDGE STRUCTURE MEASUREMENT METHOD
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Patent #:
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Issue Dt:
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01/02/2007
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Application #:
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10925555
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Filing Dt:
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08/25/2004
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Publication #:
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Pub Dt:
|
03/02/2006
| | | | |
Title:
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METHODS OF DOWNSTREAM MICROWAVE PHOTORESIST REMOVAL AND VIA CLEAN, PARTICULARLY FOLLOWING STOP-ON TIN ETCHING
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Patent #:
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Issue Dt:
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09/19/2006
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10926631
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Filing Dt:
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08/26/2004
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Publication #:
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Pub Dt:
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03/02/2006
| | | | |
Title:
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INTEGRATED CIRCUIT WITH SUBSTANTIALLY PERPENDICULAR WIRE BONDS
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Patent #:
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Issue Dt:
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11/14/2006
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Application #:
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10927802
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Filing Dt:
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08/27/2004
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Publication #:
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Pub Dt:
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03/16/2006
| | | | |
Title:
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PATTERN COMPONENT ANALYSIS AND MANIPULATION
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Patent #:
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Issue Dt:
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03/21/2006
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Application #:
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10927985
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Filing Dt:
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08/26/2004
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Publication #:
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Pub Dt:
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03/02/2006
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Title:
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METHOD AND APPARATUS FOR IMPLEMENTING A CO-AXIAL WIRE IN A SEMICONDUCTOR CHIP
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Patent #:
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Issue Dt:
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06/13/2006
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Application #:
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10928292
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Filing Dt:
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08/27/2004
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Pub Dt:
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03/02/2006
| | | | |
Title:
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PARAMETRIC OUTLIER DETECTION
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Patent #:
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Issue Dt:
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09/19/2006
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Application #:
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10928799
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Filing Dt:
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08/27/2004
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Publication #:
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Pub Dt:
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03/02/2006
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Title:
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PROCESS AND APPARATUS TO ASSIGN COORDINATES TO NODES OF LOGICAL TREES WITHOUT INCREASE OF WIRE LENGTHS
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Patent #:
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Issue Dt:
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03/13/2007
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Application #:
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10929218
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Filing Dt:
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08/30/2004
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Publication #:
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Pub Dt:
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03/02/2006
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Title:
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SPECIAL TIE-HIGH/LOW CELLS FOR SINGLE METAL LAYER ROUTE CHANGES
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Patent #:
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Issue Dt:
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04/01/2014
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Application #:
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10929706
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Filing Dt:
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08/30/2004
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Publication #:
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Pub Dt:
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03/02/2006
| | | | |
Title:
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Method for optimizing wafer edge patterning
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Patent #:
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Issue Dt:
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04/03/2007
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Application #:
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10929843
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Filing Dt:
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08/30/2004
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Publication #:
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Pub Dt:
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03/02/2006
| | | | |
Title:
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THREE-TERMINAL, TUNABLE ACTIVE INDUCTOR
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Patent #:
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Issue Dt:
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06/12/2007
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Application #:
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10930544
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Filing Dt:
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08/30/2004
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Publication #:
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Pub Dt:
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05/26/2005
| | | | |
Title:
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PREDICTIVE APPLICATIONS FOR DEVICES WITH THIN DIELECTRIC REGIONS
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Patent #:
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Issue Dt:
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03/26/2013
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Application #:
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10930590
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Filing Dt:
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08/31/2004
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Publication #:
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Pub Dt:
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03/02/2006
| | | | |
Title:
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METHOD FOR HEAT DISSIPATION ON SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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03/13/2007
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Application #:
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10931605
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Filing Dt:
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08/31/2004
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Title:
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FABRICATION OF TRENCHES WITH MULTIPLE DEPTHS ON THE SAME SUBSTRATE
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Patent #:
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Issue Dt:
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08/12/2008
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Application #:
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10931902
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Filing Dt:
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09/01/2004
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Publication #:
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Pub Dt:
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03/30/2006
| | | | |
Title:
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ADVISORY ALERT OF LOW SIGNAL STRENGTH FOR CELL PHONE USER
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Patent #:
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Issue Dt:
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05/02/2006
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Application #:
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10936016
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Filing Dt:
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09/07/2004
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Publication #:
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Pub Dt:
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03/09/2006
| | | | |
Title:
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SYSTEM AND METHOD FOR PROVIDING SCALABILITY IN AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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03/20/2007
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Application #:
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10936202
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Filing Dt:
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09/08/2004
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Publication #:
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Pub Dt:
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04/20/2006
| | | | |
Title:
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COMPACT CUSTOM LAYOUT FOR RRAM COLUMN CONTROLLER
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Patent #:
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Issue Dt:
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05/20/2008
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Application #:
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10937049
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Filing Dt:
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09/09/2004
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Publication #:
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Pub Dt:
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03/09/2006
| | | | |
Title:
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ACCURATE PIN-BASED MEMORY POWER MODEL USING ARC-BASED CHARACTERIZATION
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Patent #:
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Issue Dt:
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06/26/2007
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Application #:
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10939082
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Filing Dt:
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09/10/2004
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Publication #:
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Pub Dt:
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03/16/2006
| | | | |
Title:
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INTEGRATED HEATSPREADER FOR USE IN WIRE BONDED BALL GRID ARRAY SEMICONDUCTOR PACKAGES
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10939292
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Filing Dt:
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09/10/2004
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Publication #:
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Pub Dt:
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02/17/2005
| | | | |
Title:
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Wire bonding method for copper interconnects in semiconductor devices
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Patent #:
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Issue Dt:
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08/07/2007
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Application #:
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10941665
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Filing Dt:
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09/14/2004
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Publication #:
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Pub Dt:
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03/16/2006
| | | | |
Title:
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GUARD RING FOR IMPROVED MATCHING
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Patent #:
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Issue Dt:
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06/03/2008
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Application #:
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10942444
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Filing Dt:
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09/16/2004
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Publication #:
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Pub Dt:
|
03/10/2005
| | | | |
Title:
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APPARATUS AND METHOD TO IMPROVE THE RESOLUTION OF PHOTOLITHOGRAPHY SYSTEMS BY IMPROVING THE TEMPERATURE STABILITY OF THE RETICLE
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Patent #:
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Issue Dt:
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10/17/2006
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Application #:
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10944373
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Filing Dt:
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09/16/2004
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Publication #:
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Pub Dt:
|
03/16/2006
| | | | |
Title:
|
TECHNIQUES FOR FORMING PASSIVE DEVICES DURING SEMICONDUCTOR BACK-END PROCESSING
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|
Patent #:
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NONE
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Issue Dt:
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|
Application #:
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10944995
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Filing Dt:
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09/20/2004
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Publication #:
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Pub Dt:
|
03/23/2006
| | | | |
Title:
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Pseudo low volume reticle (PLVR) design for asic manufacturing
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Patent #:
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Issue Dt:
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09/21/2010
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Application #:
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10944996
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Filing Dt:
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09/20/2004
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Publication #:
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Pub Dt:
|
03/23/2006
| | | | |
Title:
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WAFER EDGE EXPOSE ALIGNMENT METHOD
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Patent #:
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Issue Dt:
|
12/26/2006
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Application #:
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10945177
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Filing Dt:
|
09/20/2004
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Publication #:
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Pub Dt:
|
03/23/2006
| | | | |
Title:
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FULLY SHIELDED CAPACITOR CELL STRUCTURE
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Patent #:
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Issue Dt:
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11/27/2007
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Application #:
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10945777
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Filing Dt:
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09/20/2004
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Publication #:
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Pub Dt:
|
03/23/2006
| | | | |
Title:
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INTEGRATED BARRIER AND SEED LAYER FOR COPPER INTERCONNECT TECHNOLOGY
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Patent #:
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Issue Dt:
|
09/18/2007
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Application #:
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10946274
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Filing Dt:
|
09/20/2004
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Publication #:
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Pub Dt:
|
03/23/2006
| | | | |
Title:
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RECONFIGURING A RAM TO A ROM USING UPPER LAYERS OF METALLIZATION
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Patent #:
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Issue Dt:
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02/19/2008
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Application #:
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10946422
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Filing Dt:
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09/21/2004
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Publication #:
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Pub Dt:
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03/23/2006
| | | | |
Title:
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METHOD FOR CALCULATING FREQUENCY-DEPENDENT IMPEDANCE IN AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
|
07/11/2006
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Application #:
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10947069
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Filing Dt:
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09/22/2004
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Publication #:
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Pub Dt:
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03/23/2006
| | | | |
Title:
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TEST STRUCTURE AND METHOD FOR YIELD IMPROVEMENT OF DOUBLE POLY BIPOLAR DEVICE
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Patent #:
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Issue Dt:
|
12/12/2006
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Application #:
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10947498
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Filing Dt:
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09/22/2004
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Publication #:
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Pub Dt:
|
03/23/2006
| | | | |
Title:
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METHOD OF EARLY PHYSICAL DESIGN VALIDATION AND IDENTIFICATION OF TEXTED METAL SHORT CIRCUITS IN AN INTEGRATED CIRCUIT DESIGN
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Patent #:
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Issue Dt:
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02/06/2007
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Application #:
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10947618
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Filing Dt:
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09/22/2004
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Publication #:
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Pub Dt:
|
03/23/2006
| | | | |
Title:
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METHOD OF FLOORPLANNING AND CELL PLACEMENT FOR INTEGRATED CIRCUIT CHIP ARCHITECTURE WITH INTERNAL I/O RING
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Patent #:
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Issue Dt:
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02/20/2007
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Application #:
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10948897
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Filing Dt:
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09/24/2004
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Publication #:
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Pub Dt:
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04/06/2006
| | | | |
Title:
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III-V POWER FIELD EFFECT TRANSISTORS
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Patent #:
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Issue Dt:
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01/01/2008
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Application #:
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10949760
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Filing Dt:
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09/24/2004
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Publication #:
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Pub Dt:
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04/06/2006
| | | | |
Title:
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SURFACE COORDINATE SYSTEM
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Patent #:
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Issue Dt:
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02/27/2007
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Application #:
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10950839
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Filing Dt:
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09/27/2004
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Publication #:
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Pub Dt:
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04/06/2006
| | | | |
Title:
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DYNAMIC EDGE BEAD REMOVAL
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10951430
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Filing Dt:
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09/28/2004
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Publication #:
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Pub Dt:
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03/30/2006
| | | | |
Title:
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Whisker-free lead frames
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10951646
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Filing Dt:
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09/28/2004
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Publication #:
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Pub Dt:
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03/24/2005
| | | | |
Title:
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Plasma removal of high k metal oxide
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Patent #:
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Issue Dt:
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06/12/2007
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Application #:
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10952194
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Filing Dt:
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09/28/2004
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Publication #:
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Pub Dt:
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04/06/2006
| | | | |
Title:
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METHOD AND APPARATUS FOR USE OF HIDDEN DECOUPLING CAPACITORS IN AN INTEGRATED CIRCUIT DESIGN
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Patent #:
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Issue Dt:
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12/19/2006
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Application #:
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10952213
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Filing Dt:
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09/28/2004
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Publication #:
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Pub Dt:
|
04/06/2006
| | | | |
Title:
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FOUR POINT MEASUREMENT TECHNIQUE FOR PROGRAMMABLE IMPEDANCE DRIVERS RAPIDCHIP AND ASIC DEVICES
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Patent #:
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Issue Dt:
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05/22/2007
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Application #:
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10953291
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Filing Dt:
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09/29/2004
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Publication #:
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Pub Dt:
|
03/30/2006
| | | | |
Title:
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METHOD AND STRUCTURES FOR TESTING A SEMICONDUCTOR WAFER PRIOR TO PERFORMING A FLIP CHIP BUMPING PROCESS
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Patent #:
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Issue Dt:
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06/13/2006
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Application #:
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10953292
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Filing Dt:
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09/29/2004
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Publication #:
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Pub Dt:
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03/30/2006
| | | | |
Title:
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TEST SEMICONDUCTOR DEVICE AND METHOD FOR DETERMINING JOULE HEATING EFFECTS IN SUCH A DEVICE
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Patent #:
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Issue Dt:
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06/23/2009
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Application #:
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10953322
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Filing Dt:
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09/29/2004
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Publication #:
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Pub Dt:
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03/30/2006
| | | | |
Title:
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MULTI WAVELENGTH MASK FOR MULTI LAYER PRINTING ON A PROCESS SUBSTRATE
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Patent #:
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Issue Dt:
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06/27/2006
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Application #:
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10953475
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Filing Dt:
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09/29/2004
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Publication #:
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Pub Dt:
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05/12/2005
| | | | |
Title:
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INDUCTOR FORMED IN AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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03/04/2008
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Application #:
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10953477
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Filing Dt:
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09/29/2004
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Publication #:
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Pub Dt:
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03/30/2006
| | | | |
Title:
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METHOD AND SYSTEM OF USING OFFSET GAGE FOR CMP POLISHING PAD ALIGNMENT AND ADJUSTMENT
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Patent #:
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Issue Dt:
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02/13/2007
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Application #:
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10953478
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Filing Dt:
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09/29/2004
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Publication #:
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Pub Dt:
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04/27/2006
| | | | |
Title:
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STRUCTURE AND METHOD FOR ADJUSTING INTEGRATED CIRCUIT RESISTOR VALUE
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Patent #:
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Issue Dt:
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03/27/2007
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Application #:
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10953480
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Filing Dt:
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09/29/2004
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Publication #:
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Pub Dt:
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04/06/2006
| | | | |
Title:
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SEMICONDUCTOR DEVICE MANUFACTURING
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Patent #:
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Issue Dt:
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08/01/2006
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Application #:
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10953585
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Filing Dt:
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09/29/2004
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Publication #:
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Pub Dt:
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03/30/2006
| | | | |
Title:
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SEMICONDUCTOR TESTING
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Patent #:
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Issue Dt:
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10/09/2007
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Application #:
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10953632
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Filing Dt:
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09/29/2004
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Publication #:
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Pub Dt:
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03/30/2006
| | | | |
Title:
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TRENCH ISOLATION STRUCTURE AND METHOD OF MANUFACTURE THEREFOR
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Patent #:
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Issue Dt:
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06/27/2006
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Application #:
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10953750
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Filing Dt:
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09/29/2004
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Publication #:
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Pub Dt:
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04/06/2006
| | | | |
Title:
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THICK OXIDE REGION IN A SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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08/22/2006
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Application #:
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10953894
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Filing Dt:
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09/29/2004
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Publication #:
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Pub Dt:
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03/30/2006
| | | | |
Title:
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MULTIPLE DOPING LEVEL BIPOLAR JUNCTIONS TRANSISTORS AND METHOD FOR FORMING
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Patent #:
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Issue Dt:
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10/03/2006
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Application #:
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10953897
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Filing Dt:
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09/29/2004
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Publication #:
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Pub Dt:
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03/30/2006
| | | | |
Title:
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BASE CURRENT COMPENSATION CIRCUIT FOR A BIPOLAR JUNCTION TRANSISTOR
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Patent #:
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09/12/2006
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Application #:
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10954907
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09/30/2004
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Publication #:
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Pub Dt:
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03/30/2006
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Title:
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TECHNIQUE FOR MEASUREMENT OF PROGRAMMABLE TERMINATION RESISTOR NETWORKS ON RAPIDCHIP AND ASIC DEVICES
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Patent #:
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12/05/2006
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10954940
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09/30/2004
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Publication #:
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Pub Dt:
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04/06/2006
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Title:
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CONSTRUCTION TO IMPROVE THERMAL PERFORMANCE AND REDUCE DIE BACKSIDE WARPAGE
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Patent #:
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Issue Dt:
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06/27/2006
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Application #:
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10955168
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Filing Dt:
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09/29/2004
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Publication #:
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Pub Dt:
|
04/06/2006
| | | | |
Title:
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METHOD OF PREDICTING QUIESCENT CURRENT VARIATION OF AN INTEGRATED CIRCUIT DIE FROM A PROCESS MONITOR DERATING FACTOR
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Patent #:
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Issue Dt:
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03/18/2008
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10955238
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Filing Dt:
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09/30/2004
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Publication #:
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Pub Dt:
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08/04/2005
| | | | |
Title:
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STRUCTURE AND METHOD FOR IMPROVED HEAT CONDUCTION FOR SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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05/06/2008
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Application #:
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10955912
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Filing Dt:
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09/30/2004
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Publication #:
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Pub Dt:
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03/30/2006
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Title:
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SYSTEM AND METHOD FOR FORMING SOLDER JOINTS
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Patent #:
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Issue Dt:
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10/03/2006
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Application #:
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10955913
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Filing Dt:
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09/30/2004
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Publication #:
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Pub Dt:
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03/30/2006
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Title:
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REINFORCED BOND PAD FOR A SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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10/16/2007
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10956860
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Filing Dt:
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09/30/2004
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Publication #:
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Pub Dt:
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04/06/2006
| | | | |
Title:
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NQL - NETLIST QUERY LANGUAGE
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Patent #:
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Issue Dt:
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06/12/2007
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10956862
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Filing Dt:
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09/30/2004
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Publication #:
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Pub Dt:
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04/06/2006
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Title:
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NETLIST DATABASE
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Patent #:
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Issue Dt:
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04/20/2010
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10959186
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10/07/2004
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Publication #:
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Pub Dt:
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03/10/2005
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Title:
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CORDLESS TELEPHONE WITH MP3 PLAYER CAPABILITY
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Patent #:
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Issue Dt:
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02/13/2007
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10959868
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10/06/2004
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Publication #:
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Pub Dt:
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02/24/2005
| | | | |
Title:
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ANALOG CAPACITOR IN DUAL DAMASCENE PROCESS
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Patent #:
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Issue Dt:
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10/17/2006
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10960680
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10/07/2004
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Publication #:
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Pub Dt:
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04/13/2006
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Title:
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MULTI-CHIP INTEGRATED CIRCUIT MODULE FOR HIGH-FREQUENCY OPERATION
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Patent #:
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Issue Dt:
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02/20/2007
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Application #:
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10963156
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Filing Dt:
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10/12/2004
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Publication #:
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Pub Dt:
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03/03/2005
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Title:
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CATHODE WITH IMPROVED WORK FUNCTION AND METHOD FOR MAKING THE SAME
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Patent #:
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NONE
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Application #:
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10964032
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Filing Dt:
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10/12/2004
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Publication #:
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Pub Dt:
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03/24/2005
| | | | |
Title:
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Via and metal line interface capable of reducing the incidence of electro-migration induced voids
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Patent #:
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Issue Dt:
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02/20/2007
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Application #:
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10966074
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Filing Dt:
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10/14/2004
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Publication #:
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Pub Dt:
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04/20/2006
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Title:
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METHOD FOR FABRICATING PLANAR SEMICONDUCTOR WAFERS
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Patent #:
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Issue Dt:
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03/21/2006
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Application #:
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10967900
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10/18/2004
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Publication #:
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Pub Dt:
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03/10/2005
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Title:
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ELECTRO-MECHANICAL DEVICE HAVING A CHARGE DISSIPATION LAYER AND A METHOD OF MANUFACTURE THEREFOR
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Patent #:
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Issue Dt:
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01/30/2007
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Application #:
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10969745
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Filing Dt:
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10/20/2004
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Publication #:
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Pub Dt:
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04/20/2006
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Title:
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METHOD OF SCREENING ASIC DEFECTS USING INDEPENDENT COMPONENT ANALYSIS OF QUIESCENT CURRENT MEASUREMENTS
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Patent #:
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Issue Dt:
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07/12/2011
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Application #:
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10971911
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Filing Dt:
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10/23/2004
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Publication #:
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Pub Dt:
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05/11/2006
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Title:
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DEBUGGING SIMULATION OF A CIRCUIT CORE USING PATTERN RECORDER, PLAYER & CHECKER
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Patent #:
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Issue Dt:
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08/21/2007
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Application #:
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10971961
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Filing Dt:
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10/22/2004
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Publication #:
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Pub Dt:
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04/27/2006
| | | | |
Title:
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LOCAL INTERCONNECT MANUFACTURING PROCESS
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Patent #:
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Issue Dt:
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06/27/2006
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Application #:
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10972898
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Filing Dt:
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10/25/2004
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Publication #:
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Pub Dt:
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05/26/2005
| | | | |
Title:
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ADJUSTABLE TRANSMISSION PHASE SHIFT MASK
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Patent #:
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Issue Dt:
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04/17/2007
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Application #:
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10973851
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Filing Dt:
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10/25/2004
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Publication #:
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Pub Dt:
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04/27/2006
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Title:
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CONTACT RING DESIGN FOR REDUCING BUBBLE AND ELECTROLYTE EFFECTS DURING ELECTROCHEMICAL PLATING IN MANUFACTURING
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Patent #:
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NONE
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Application #:
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10974450
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Filing Dt:
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10/27/2004
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Publication #:
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Pub Dt:
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04/27/2006
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Title:
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Generalized BIST for multiport memories
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10975570
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Filing Dt:
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10/27/2004
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Publication #:
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Pub Dt:
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04/27/2006
| | | | |
Title:
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Method of automating place and route corrections for an integrated circuit design from physical design validation
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