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Reel/Frame:045216/0020   Pages: 334
Recorded: 02/01/2018
Attorney Dkt #:43172.01200
Conveyance: SECURITY INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 3463
Page 29 of 35
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
1
Patent #:
7181712
Issue Dt:
02/20/2007
Application #:
10975981
Filing Dt:
10/27/2004
Publication #:
US20060090145
Pub Dt:
04/27/2006
Title:
METHOD OF OPTIMIZING CRITICAL PATH DELAY IN AN INTEGRATED CIRCUIT DESIGN
2
Patent #:
7216323
Issue Dt:
05/08/2007
Application #:
10976518
Filing Dt:
10/29/2004
Publication #:
US20060095880
Pub Dt:
05/04/2006
Title:
PROCESS FOR DESIGNING BASE PLATFORMS FOR IC DESIGN TO PERMIT RESOURCE RECOVERY AND FLEXIBLE MACRO PLACEMENT, BASE PLATFORM FOR ICS, AND PROCESS OF CREATING ICS
3
Patent #:
7302654
Issue Dt:
11/27/2007
Application #:
10977386
Filing Dt:
10/29/2004
Publication #:
US20060095883
Pub Dt:
05/04/2006
Title:
METHOD OF AUTOMATING PLACE AND ROUTE CORRECTIONS FOR AN INTEGRATED CIRCUIT DESIGN FROM PHYSICAL DESIGN VALIDATION
4
Patent #:
7279744
Issue Dt:
10/09/2007
Application #:
10977732
Filing Dt:
10/29/2004
Publication #:
US20050156234
Pub Dt:
07/21/2005
Title:
CONTROL OF HOT CARRIER INJECTION IN A METAL-OXIDE SEMICONDUCTOR DEVICE
5
Patent #:
7642188
Issue Dt:
01/05/2010
Application #:
10978716
Filing Dt:
11/01/2004
Publication #:
US20050064677
Pub Dt:
03/24/2005
Title:
MIXED SIGNAL INTEGRATED CIRCUIT WITH IMPROVED ISOLATION
6
Patent #:
7352062
Issue Dt:
04/01/2008
Application #:
10979491
Filing Dt:
11/02/2004
Publication #:
US20050062143
Pub Dt:
03/24/2005
Title:
INTEGRATED CIRCUIT PACKAGE DESIGN
7
Patent #:
7074710
Issue Dt:
07/11/2006
Application #:
10980945
Filing Dt:
11/03/2004
Publication #:
US20060094246
Pub Dt:
05/04/2006
Title:
METHOD OF WAFER PATTERNING FOR REDUCING EDGE EXCLUSION ZONE
8
Patent #:
7573097
Issue Dt:
08/11/2009
Application #:
10981175
Filing Dt:
11/03/2004
Publication #:
US20060091480
Pub Dt:
05/04/2006
Title:
LATERAL DOUBLE DIFFUSED MOS TRANSISTORS
9
Patent #:
7380228
Issue Dt:
05/27/2008
Application #:
10984115
Filing Dt:
11/08/2004
Publication #:
US20060101363
Pub Dt:
05/11/2006
Title:
METHOD OF ASSOCIATING TIMING VIOLATIONS WITH CRITICAL STRUCTURES IN AN INTEGRATED CIRCUIT DESIGN
10
Patent #:
7148556
Issue Dt:
12/12/2006
Application #:
10984286
Filing Dt:
11/09/2004
Publication #:
US20060097349
Pub Dt:
05/11/2006
Title:
HIGH PERFORMANCE DIODE-IMPLANTED VOLTAGE-CONTROLLED POLY RESISTORS FOR MIXED-SIGNAL AND RF APPLICATIONS
11
Patent #:
7169714
Issue Dt:
01/30/2007
Application #:
10986984
Filing Dt:
11/12/2004
Publication #:
US20050164516
Pub Dt:
07/28/2005
Title:
METHOD AND STRUCTURE FOR GRADED GATE OXIDES ON VERTICAL AND NON-PLANAR SURFACES
12
Patent #:
7181359
Issue Dt:
02/20/2007
Application #:
10988081
Filing Dt:
11/12/2004
Publication #:
US20060106563
Pub Dt:
05/18/2006
Title:
METHOD AND SYSTEM OF GENERIC IMPLEMENTATION OF SHARING TEST PINS WITH I/O CELLS
13
Patent #:
NONE
Issue Dt:
Application #:
10988087
Filing Dt:
11/12/2004
Publication #:
US20050151949
Pub Dt:
07/14/2005
Title:
Process and apparatus for applying apodization to maskless optical direct write lithography processes
14
Patent #:
7207026
Issue Dt:
04/17/2007
Application #:
10990237
Filing Dt:
11/16/2004
Publication #:
US20060104145
Pub Dt:
05/18/2006
Title:
MEMORY TILING ARCHITECTURE
15
Patent #:
7155688
Issue Dt:
12/26/2006
Application #:
10990589
Filing Dt:
11/17/2004
Publication #:
US20060107247
Pub Dt:
05/18/2006
Title:
MEMORY GENERATION AND PLACEMENT
16
Patent #:
7396760
Issue Dt:
07/08/2008
Application #:
10991107
Filing Dt:
11/17/2004
Publication #:
US20060105564
Pub Dt:
05/18/2006
Title:
METHOD AND SYSTEM FOR REDUCING INTER-LAYER CAPACITANCE IN INTEGRATED CIRCUITS
17
Patent #:
7174532
Issue Dt:
02/06/2007
Application #:
10992031
Filing Dt:
11/18/2004
Publication #:
US20060107243
Pub Dt:
05/18/2006
Title:
METHOD OF MAKING A SEMICONDUCTOR DEVICE BY BALANCING SHALLOW TRENCH ISOLATION STRESS AND OPTICAL PROXIMITY EFFECTS
18
Patent #:
7146591
Issue Dt:
12/05/2006
Application #:
10992941
Filing Dt:
11/19/2004
Publication #:
US20060112361
Pub Dt:
05/25/2006
Title:
METHOD OF SELECTING CELLS IN LOGIC RESTRUCTURING
19
Patent #:
7257791
Issue Dt:
08/14/2007
Application #:
10992999
Filing Dt:
11/19/2004
Publication #:
US20060112363
Pub Dt:
05/25/2006
Title:
MULTIPLE BUFFER INSERTION IN GLOBAL ROUTING
20
Patent #:
7189498
Issue Dt:
03/13/2007
Application #:
10993603
Filing Dt:
11/19/2004
Publication #:
US20050153246
Pub Dt:
07/14/2005
Title:
PROCESS AND APPARATUS FOR GENERATING A STRONG PHASE SHIFT OPTICAL PATTERN FOR USE IN AN OPTICAL DIRECT WRITE LITHOGRAPHY PROCESS
21
Patent #:
7213223
Issue Dt:
05/01/2007
Application #:
10994114
Filing Dt:
11/19/2004
Publication #:
US20060112158
Pub Dt:
05/25/2006
Title:
METHOD OF ESTIMATING A TOTAL PATH DELAY IN AN INTEGRATED CIRCUIT DESIGN WITH STOCHASTICALLY WEIGHTED CONSERVATISM
22
Patent #:
7434180
Issue Dt:
10/07/2008
Application #:
10995777
Filing Dt:
11/23/2004
Publication #:
US20060112376
Pub Dt:
05/25/2006
Title:
VIRTUAL DATA REPRESENTATION THROUGH SELECTIVE BIDIRECTIONAL TRANSLATION
23
Patent #:
7305634
Issue Dt:
12/04/2007
Application #:
10996074
Filing Dt:
11/23/2004
Publication #:
US20060109462
Pub Dt:
05/25/2006
Title:
METHOD TO SELECTIVELY IDENTIFY AT RISK DIE BASED ON LOCATION WITHIN THE RETICLE
24
Patent #:
7221042
Issue Dt:
05/22/2007
Application #:
10997630
Filing Dt:
11/24/2004
Publication #:
US20060108670
Pub Dt:
05/25/2006
Title:
LEADFRAME DESIGNS FOR INTEGRATED CIRCUIT PLASTIC PACKAGES
25
Patent #:
7315993
Issue Dt:
01/01/2008
Application #:
10999468
Filing Dt:
11/30/2004
Publication #:
US20060117281
Pub Dt:
06/01/2006
Title:
VERIFICATION OF RRAM TILING NETLIST
26
Patent #:
7216278
Issue Dt:
05/08/2007
Application #:
10999493
Filing Dt:
11/30/2004
Publication #:
US20060156088
Pub Dt:
07/13/2006
Title:
METHOD AND BIST ARCHITECTURE FOR FAST MEMORY TESTING IN PLATFORM-BASED INTEGRATED CIRCUIT
27
Patent #:
7262476
Issue Dt:
08/28/2007
Application #:
10999704
Filing Dt:
11/30/2004
Publication #:
US20060113625
Pub Dt:
06/01/2006
Title:
SEMICONDUCTOR DEVICE HAVING IMPROVED POWER DENSITY
28
Patent #:
7329922
Issue Dt:
02/12/2008
Application #:
10999705
Filing Dt:
11/30/2004
Publication #:
US20060113601
Pub Dt:
06/01/2006
Title:
DUAL-GATE METAL-OXIDE SEMICONDUCTOR DEVICE
29
Patent #:
7200826
Issue Dt:
04/03/2007
Application #:
11000104
Filing Dt:
11/30/2004
Publication #:
US20060117284
Pub Dt:
06/01/2006
Title:
RRAM MEMORY TIMING LEARNING TOOL
30
Patent #:
7095483
Issue Dt:
08/22/2006
Application #:
11000772
Filing Dt:
12/01/2004
Publication #:
US20050078289
Pub Dt:
04/14/2005
Title:
PROCESS INDEPENDENT ALIGNMENT MARKS
31
Patent #:
7493577
Issue Dt:
02/17/2009
Application #:
11002576
Filing Dt:
12/01/2004
Publication #:
US20060117292
Pub Dt:
06/01/2006
Title:
AUTOMATIC RECOGNITION OF GEOMETRIC POINTS IN A TARGET IC DESIGN FOR OPC MASK QUALITY CALCULATION
32
Patent #:
7246336
Issue Dt:
07/17/2007
Application #:
11004309
Filing Dt:
12/03/2004
Publication #:
US20060123369
Pub Dt:
06/08/2006
Title:
RAMPTIME PROPAGATION ON DESIGNS WITH CYCLES
33
Patent #:
7424690
Issue Dt:
09/09/2008
Application #:
11005690
Filing Dt:
12/07/2004
Publication #:
US20060123377
Pub Dt:
06/08/2006
Title:
INTERCONNECT INTEGRITY VERIFICATION
34
Patent #:
7242074
Issue Dt:
07/10/2007
Application #:
11005765
Filing Dt:
12/06/2004
Publication #:
US20060118908
Pub Dt:
06/08/2006
Title:
REDUCED CAPACITANCE RESISTORS
35
Patent #:
7373626
Issue Dt:
05/13/2008
Application #:
11006349
Filing Dt:
12/06/2004
Publication #:
US20060123281
Pub Dt:
06/08/2006
Title:
METHOD AND TIMING HARNESS FOR SYSTEM LEVEL STATIC TIMING ANALYSIS
36
Patent #:
7246337
Issue Dt:
07/17/2007
Application #:
11007039
Filing Dt:
12/08/2004
Publication #:
US20060123373
Pub Dt:
06/08/2006
Title:
DENSITY DRIVEN LAYOUT FOR RRAM CONFIGURATION MODULE
37
Patent #:
7619272
Issue Dt:
11/17/2009
Application #:
11007392
Filing Dt:
12/07/2004
Publication #:
US20060118919
Pub Dt:
06/08/2006
Title:
BI-AXIAL TEXTURING OF HIGH-K DIELECTRIC FILMS TO REDUCE LEAKAGE CURRENTS
38
Patent #:
7285145
Issue Dt:
10/23/2007
Application #:
11007694
Filing Dt:
12/07/2004
Title:
ELECTRO CHEMICAL MECHANICAL POLISHING METHOD AND DEVICE FOR PLANARIZING SEMICONDUCTOR SURFACES
39
Patent #:
7363608
Issue Dt:
04/22/2008
Application #:
11008854
Filing Dt:
12/09/2004
Publication #:
US20060125485
Pub Dt:
06/15/2006
Title:
ACCELERATING PCB DEVELOPMENT AND DEBUG IN ADVANCE OF PLATFORM ASIC PROTOTYPE SAMPLES
40
Patent #:
7334206
Issue Dt:
02/19/2008
Application #:
11010745
Filing Dt:
12/13/2004
Publication #:
US20060129962
Pub Dt:
06/15/2006
Title:
CELL BUILDER FOR DIFFERENT LAYER STACKS
41
Patent #:
7285840
Issue Dt:
10/23/2007
Application #:
11010970
Filing Dt:
12/12/2004
Publication #:
US20060128112
Pub Dt:
06/15/2006
Title:
APPARATUS FOR CONFINING INDUCTIVELY COUPLED SURFACE CURRENTS
42
Patent #:
7376260
Issue Dt:
05/20/2008
Application #:
11011384
Filing Dt:
12/14/2004
Publication #:
US20050100802
Pub Dt:
05/12/2005
Title:
METHOD FOR POST-OPC MULTI LAYER OVERLAY QUALITY INSPECTION
43
Patent #:
8057963
Issue Dt:
11/15/2011
Application #:
11011896
Filing Dt:
12/14/2004
Publication #:
US20050275814
Pub Dt:
12/15/2005
Title:
MASKLESS VORTEX PHASE SHIFT OPTICAL DIRECT WRITE LITHOGRAPHY
44
Patent #:
7372547
Issue Dt:
05/13/2008
Application #:
11012003
Filing Dt:
12/14/2004
Publication #:
US20050237508
Pub Dt:
10/27/2005
Title:
PROCESS AND APPARATUS FOR ACHIEVING SINGLE EXPOSURE PATTERN TRANSFER USING MASKLESS OPTICAL DIRECT WRITE LITHOGRAPHY
45
Patent #:
7260814
Issue Dt:
08/21/2007
Application #:
11012618
Filing Dt:
12/14/2004
Publication #:
US20060129966
Pub Dt:
06/15/2006
Title:
OPC EDGE CORRECTION BASED ON A SMOOTHED MASK DESIGN
46
Patent #:
7197735
Issue Dt:
03/27/2007
Application #:
11012741
Filing Dt:
12/15/2004
Publication #:
US20060129963
Pub Dt:
06/15/2006
Title:
FLOORPLAN VISUALIZATION METHOD USING GATE COUNT AND GATE DENSITY ESTIMATIONS
47
Patent #:
NONE
Issue Dt:
Application #:
11012838
Filing Dt:
12/15/2004
Publication #:
US20050093111
Pub Dt:
05/05/2005
Title:
System and method for using film deposition techniques to provide an antenna within an integrated circuit package
48
Patent #:
7210083
Issue Dt:
04/24/2007
Application #:
11013641
Filing Dt:
12/16/2004
Publication #:
US20060156128
Pub Dt:
07/13/2006
Title:
SYSTEM AND METHOD FOR IMPLEMENTING POSTPONED QUASI-MASKING TEST OUTPUT COMPRESSION IN INTEGRATED CIRCUIT
49
Patent #:
NONE
Issue Dt:
Application #:
11014476
Filing Dt:
12/16/2004
Publication #:
US20050109369
Pub Dt:
05/26/2005
Title:
Method to use a laser to perform the edge clean operation on a semiconductor wafer
50
Patent #:
7185298
Issue Dt:
02/27/2007
Application #:
11015114
Filing Dt:
12/17/2004
Publication #:
US20060136850
Pub Dt:
06/22/2006
Title:
METHOD OF PARASITIC EXTRACTION FROM A PREVIOUSLY CALCULATED CAPACITANCE SOLUTION
51
Patent #:
7231626
Issue Dt:
06/12/2007
Application #:
11015123
Filing Dt:
12/17/2004
Publication #:
US20060136855
Pub Dt:
06/22/2006
Title:
METHOD OF IMPLEMENTING AN ENGINEERING CHANGE ORDER IN AN INTEGRATED CIRCUIT DESIGN BY WINDOWS
52
Patent #:
7224047
Issue Dt:
05/29/2007
Application #:
11015534
Filing Dt:
12/18/2004
Publication #:
US20060131707
Pub Dt:
06/22/2006
Title:
SEMICONDUCTOR DEVICE PACKAGE WITH REDUCED LEAKAGE
53
Patent #:
7956451
Issue Dt:
06/07/2011
Application #:
11015535
Filing Dt:
12/18/2004
Publication #:
US20060131704
Pub Dt:
06/22/2006
Title:
PACKAGES FOR ENCAPSULATED SEMICONDUCTOR DEVICES AND METHOD OF MAKING SAME
54
Patent #:
7075179
Issue Dt:
07/11/2006
Application #:
11016014
Filing Dt:
12/17/2004
Publication #:
US20060131725
Pub Dt:
06/22/2006
Title:
SYSTEM FOR IMPLEMENTING A CONFIGURABLE INTEGRATED CIRCUIT
55
Patent #:
7290194
Issue Dt:
10/30/2007
Application #:
11016192
Filing Dt:
12/17/2004
Publication #:
US20060156142
Pub Dt:
07/13/2006
Title:
SYSTEM FOR PERFORMING AUTOMATIC TEST PIN ASSIGNMENT FOR A PROGRAMMABLE DEVICE
56
Patent #:
6998716
Issue Dt:
02/14/2006
Application #:
11016468
Filing Dt:
12/16/2004
Publication #:
US20050098895
Pub Dt:
05/12/2005
Title:
DIAMOND METAL-FILLED PATTERNS ACHIEVING LOW PARASITIC COUPLING CAPACITANCE
57
Patent #:
7398492
Issue Dt:
07/08/2008
Application #:
11017015
Filing Dt:
12/20/2004
Publication #:
US20050273736
Pub Dt:
12/08/2005
Title:
RULES AND DIRECTIVES FOR VALIDATING CORRECT DATA USED IN THE DESIGN OF SEMICONDUCTOR PRODUCTS
58
Patent #:
7404156
Issue Dt:
07/22/2008
Application #:
11017017
Filing Dt:
12/20/2004
Publication #:
US20050273737
Pub Dt:
12/08/2005
Title:
LANGUAGE AND TEMPLATES FOR USE IN THE DESIGN OF SEMICONDUCTOR PRODUCTS
59
Patent #:
7340697
Issue Dt:
03/04/2008
Application #:
11019885
Filing Dt:
12/22/2004
Publication #:
US20060136860
Pub Dt:
06/22/2006
Title:
INTEGRATED COMPUTER-AIDED CIRCUIT DESIGN KIT FACILITATING VERIFICATION OF DESIGNS ACROSS DIFFERENT PROCESS TECHNOLOGIES
60
Patent #:
7280816
Issue Dt:
10/09/2007
Application #:
11022159
Filing Dt:
12/23/2004
Publication #:
US20060141994
Pub Dt:
06/29/2006
Title:
TECHNIQUES FOR MONITORING MOBILE TELECOMMUNICATIONS FOR SHARED ACCOUNTS
61
Patent #:
7290224
Issue Dt:
10/30/2007
Application #:
11027266
Filing Dt:
12/31/2004
Publication #:
US20050273738
Pub Dt:
12/08/2005
Title:
GUIDED CAPTURE, CREATION, AND SEAMLESS INTEGRATION WITH SCALABLE COMPLEXITY OF A CLOCK SPECIFICATION INTO A DESIGN FLOW OF AN INTEGRATED CIRCUIT
62
Patent #:
7181713
Issue Dt:
02/20/2007
Application #:
11028403
Filing Dt:
01/03/2005
Publication #:
US20050114811
Pub Dt:
05/26/2005
Title:
STATIC TIMING AND RISK ANALYSIS TOOL
63
Patent #:
7203877
Issue Dt:
04/10/2007
Application #:
11028695
Filing Dt:
01/04/2005
Publication #:
US20060150041
Pub Dt:
07/06/2006
Title:
FAILURE ANALYSIS AND TESTING OF SEMI-CONDUCTOR DEVICES USING INTELLIGENT SOFTWARE ON AUTOMATED TEST EQUIPMENT (ATE)
64
Patent #:
7390680
Issue Dt:
06/24/2008
Application #:
11031564
Filing Dt:
01/06/2005
Publication #:
US20050145841
Pub Dt:
07/07/2005
Title:
METHOD TO SELECTIVELY IDENTIFY RELIABILITY RISK DIE BASED ON CHARACTERISTICS OF LOCAL REGIONS ON THE WAFER
65
Patent #:
7234122
Issue Dt:
06/19/2007
Application #:
11032720
Filing Dt:
01/10/2005
Publication #:
US20050235235
Pub Dt:
10/20/2005
Title:
THREE-DIMENSIONAL INTERCONNECT RESISTANCE EXTRACTION USING VARIATIONAL METHOD
66
Patent #:
7207021
Issue Dt:
04/17/2007
Application #:
11036822
Filing Dt:
01/14/2005
Publication #:
US20060190853
Pub Dt:
08/24/2006
Title:
METHOD FOR ESTIMATING A FREQUENCY-BASED RAMPTIME LIMIT
67
Patent #:
7299435
Issue Dt:
11/20/2007
Application #:
11037306
Filing Dt:
01/18/2005
Publication #:
US20060190879
Pub Dt:
08/24/2006
Title:
FREQUENCY DEPENDENT TIMING MARGIN
68
Patent #:
7243324
Issue Dt:
07/10/2007
Application #:
11041489
Filing Dt:
01/24/2005
Publication #:
US20060190901
Pub Dt:
08/24/2006
Title:
METHOD OF BUFFER INSERTION TO ACHIEVE PIN SPECIFIC DELAYS
69
Patent #:
7258953
Issue Dt:
08/21/2007
Application #:
11046150
Filing Dt:
01/28/2005
Publication #:
US20060172447
Pub Dt:
08/03/2006
Title:
MULTI-LAYER REGISTRATION AND DIMENSIONAL TEST MARK FOR SCATTEROMETRICAL MEASUREMENT
70
Patent #:
7553772
Issue Dt:
06/30/2009
Application #:
11046949
Filing Dt:
01/31/2005
Title:
PROCESS AND APPARATUS FOR SIMULTANEOUS LIGHT AND RADICAL SURFACE TREATMENT OF INTEGRATED CIRCUIT STRUCTURE
71
Patent #:
7235422
Issue Dt:
06/26/2007
Application #:
11049246
Filing Dt:
02/02/2005
Publication #:
US20060172465
Pub Dt:
08/03/2006
Title:
DEVICE PACKAGES
72
Patent #:
7242090
Issue Dt:
07/10/2007
Application #:
11049407
Filing Dt:
02/02/2005
Publication #:
US20060170095
Pub Dt:
08/03/2006
Title:
DEVICE PACKAGE
73
Patent #:
7515581
Issue Dt:
04/07/2009
Application #:
11050505
Filing Dt:
02/03/2005
Publication #:
US20050226208
Pub Dt:
10/13/2005
Title:
METHOD AND SYSTEM FOR A NEW PACKET PREAMBLE FOR WIDEBAND WIRELESS LOCAL AREA NETWORK (LAN) SYSTEMS
74
Patent #:
7564914
Issue Dt:
07/21/2009
Application #:
11052353
Filing Dt:
02/07/2005
Publication #:
US20060126752
Pub Dt:
06/15/2006
Title:
METHOD AND SYSTEM FOR FRAME FORMATS FOR MIMO CHANNEL MEASUREMENT EXCHANGE
75
Patent #:
7057261
Issue Dt:
06/06/2006
Application #:
11053505
Filing Dt:
02/08/2005
Publication #:
US20050147913
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Title:
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Assignors
1
HILCO PATENT ACQUISITION 56, LLC
Exec Dt:
01/24/2018
2
BELL SEMICONDUCTOR, LLC
Exec Dt:
01/24/2018
3
BELL NORTHERN RESEARCH, LLC
Exec Dt:
01/24/2018
Assignee
1
CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
225 W. WASHINGTON ST., 9TH FLOOR
CHICAGO, ILLINOIS 60606
Correspondence name and address
JAVIER J. RAMOS
1850 K STREET, NW, SUITE 1100
MILBANK, TWEED, HADLEY & MCCLOY, LLP
WASHINGTON, DC 20006

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