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Patent Assignment Details
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Reel/Frame:045216/0020   Pages: 334
Recorded: 02/01/2018
Attorney Dkt #:43172.01200
Conveyance: SECURITY INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 3463
Page 31 of 35
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
1
Patent #:
7571397
Issue Dt:
08/04/2009
Application #:
11265040
Filing Dt:
11/02/2005
Publication #:
US20070099313
Pub Dt:
05/03/2007
Title:
METHOD OF DESIGN BASED PROCESS CONTROL OPTIMIZATION
2
Patent #:
7635888
Issue Dt:
12/22/2009
Application #:
11265062
Filing Dt:
11/02/2005
Publication #:
US20060054994
Pub Dt:
03/16/2006
Title:
INTERDIGITADED CAPACITORS
3
Patent #:
7327011
Issue Dt:
02/05/2008
Application #:
11266133
Filing Dt:
11/02/2005
Publication #:
US20070096252
Pub Dt:
05/03/2007
Title:
MULTI-SURFACED PLATE-TO-PLATE CAPACITOR AND METHOD OF FORMING SAME
4
Patent #:
7467359
Issue Dt:
12/16/2008
Application #:
11266687
Filing Dt:
11/03/2005
Publication #:
US20060067436
Pub Dt:
03/30/2006
Title:
DECODER USING A MEMORY FOR STORING STATE METRICS INPLEMENTING A DECODER TRELLIS
5
Patent #:
8076779
Issue Dt:
12/13/2011
Application #:
11269275
Filing Dt:
11/08/2005
Publication #:
US20070102812
Pub Dt:
05/10/2007
Title:
REDUCTION OF MACRO LEVEL STRESSES IN COPPER/LOW-K WAFERS
6
Patent #:
7325216
Issue Dt:
01/29/2008
Application #:
11271991
Filing Dt:
11/09/2005
Publication #:
US20070104029
Pub Dt:
05/10/2007
Title:
METHOD AND COMPUTER PROGRAM FOR SPREADING TRACE SEGMENTS IN AN INTEGRATED CIRCUIT PACKAGE DESIGN
7
Patent #:
7332924
Issue Dt:
02/19/2008
Application #:
11273857
Filing Dt:
11/15/2005
Publication #:
US20070109005
Pub Dt:
05/17/2007
Title:
EMBEDDED TEST CIRCUITRY AND A METHOD FOR TESTING A SEMICONDUCTOR DEVICE FOR BREAKDOWN, WEAROUT OR FAILURE
8
Patent #:
7180011
Issue Dt:
02/20/2007
Application #:
11276938
Filing Dt:
03/17/2006
Title:
DEVICE FOR MINIMIZING DIFFERENTIAL PAIR LENGTH MISMATCH AND IMPEDANCE DISCONTINUITIES IN AN INTEGRATED CIRCUIT PACKAGE DESIGN
9
Patent #:
8049340
Issue Dt:
11/01/2011
Application #:
11277188
Filing Dt:
03/22/2006
Publication #:
US20070222084
Pub Dt:
09/27/2007
Title:
DEVICE FOR AVOIDING PARASITIC CAPACITANCE IN AN INTEGRATED CIRCUIT PACKAGE
10
Patent #:
7424687
Issue Dt:
09/09/2008
Application #:
11280110
Filing Dt:
11/16/2005
Publication #:
US20070113212
Pub Dt:
05/17/2007
Title:
METHOD AND APPARATUS FOR MAPPING DESIGN MEMORIES TO INTEGRATED CIRCUIT LAYOUT
11
Patent #:
7389484
Issue Dt:
06/17/2008
Application #:
11280879
Filing Dt:
11/16/2005
Publication #:
US20070108961
Pub Dt:
05/17/2007
Title:
METHOD AND APPARATUS FOR TILING MEMORIES IN INTEGRATED CIRCUIT LAYOUT
12
Patent #:
7205673
Issue Dt:
04/17/2007
Application #:
11283044
Filing Dt:
11/18/2005
Title:
REDUCE OR ELIMINATE IMC CRACKING IN POST WIRE BONDED DIES BY DOPING ALUMINUM USED IN BOND PADS DURING CU/LOW-K BEOL PROCESSING
13
Patent #:
8552560
Issue Dt:
10/08/2013
Application #:
11283219
Filing Dt:
11/18/2005
Publication #:
US20070114667
Pub Dt:
05/24/2007
Title:
ALTERNATE PAD STRUCTURES/PASSIVATION INEGRATION SCHEMES TO REDUCE OR ELIMINATE IMC CRACKING IN POST WIRE BONDED DIES DURING CU/LOW-K BEOL PROCESSING
14
Patent #:
7298036
Issue Dt:
11/20/2007
Application #:
11283340
Filing Dt:
11/18/2005
Publication #:
US20070114644
Pub Dt:
05/24/2007
Title:
SCALING OF FUNCTIONAL ASSIGNMENTS IN PACKAGES
15
Patent #:
7494842
Issue Dt:
02/24/2009
Application #:
11286546
Filing Dt:
11/23/2005
Publication #:
US20070114613
Pub Dt:
05/24/2007
Title:
PROGRAMMABLE NANOTUBE INTERCONNECT
16
Patent #:
7847285
Issue Dt:
12/07/2010
Application #:
11286558
Filing Dt:
11/23/2005
Publication #:
US20070125999
Pub Dt:
06/07/2007
Title:
CONFIGURABLE POWER SEGMENTATION USING A NANOTUBE STRUCTURE
17
Patent #:
7254761
Issue Dt:
08/07/2007
Application #:
11287927
Filing Dt:
11/28/2005
Publication #:
US20070122922
Pub Dt:
05/31/2007
Title:
PLATFORM ASIC RELIABILITY
18
Patent #:
7531442
Issue Dt:
05/12/2009
Application #:
11290087
Filing Dt:
11/30/2005
Publication #:
US20070123024
Pub Dt:
05/31/2007
Title:
ELIMINATE IMC CRACKING IN POST WIREBONDED DIES: MACRO LEVEL STRESS REDUCTION BY MODIFYING DIELECTRIC/METAL FILM STACK IN BE LAYERS DURING CU/LOW-K PROCESSING
19
Patent #:
7496861
Issue Dt:
02/24/2009
Application #:
11290186
Filing Dt:
11/30/2005
Publication #:
US20070124716
Pub Dt:
05/31/2007
Title:
METHOD FOR GENERALIZING DESIGN ATTRIBUTES IN A DESIGN CAPTURE ENVIRONMENT
20
Patent #:
7570978
Issue Dt:
08/04/2009
Application #:
11291937
Filing Dt:
12/01/2005
Publication #:
US20070129121
Pub Dt:
06/07/2007
Title:
APPARATUS AND METHOD FOR PREVENTING AN UNINTENTIONAL ACTIVATION OF A MOBILE COMMUNICATION DEVICE
21
Patent #:
7406669
Issue Dt:
07/29/2008
Application #:
11295351
Filing Dt:
12/06/2005
Publication #:
US20070130486
Pub Dt:
06/07/2007
Title:
TIMING CONSTRAINTS METHODOLOGY FOR ENABLING CLOCK RECONVERGENCE PESSIMISM REMOVAL IN EXTRACTED TIMING MODELS
22
Patent #:
7504728
Issue Dt:
03/17/2009
Application #:
11298030
Filing Dt:
12/09/2005
Publication #:
US20070134903
Pub Dt:
06/14/2007
Title:
INTEGRATED CIRCUIT HAVING BOND PAD WITH IMPROVED THERMAL AND MECHANICAL PROPERTIES
23
Patent #:
7584442
Issue Dt:
09/01/2009
Application #:
11298894
Filing Dt:
12/09/2005
Publication #:
US20070136704
Pub Dt:
06/14/2007
Title:
METHOD AND APPARATUS FOR GENERATING MEMORY MODELS AND TIMING DATABASE
24
Patent #:
7379836
Issue Dt:
05/27/2008
Application #:
11300789
Filing Dt:
12/14/2005
Publication #:
US20070136023
Pub Dt:
06/14/2007
Title:
METHOD OF USING AUTOMATED TEST EQUIPMENT TO SCREEN FOR LEAKAGE INDUCING DEFECTS AFTER CALIBRATION TO INTRINSIC LEAKAGE
25
Patent #:
7541220
Issue Dt:
06/02/2009
Application #:
11302690
Filing Dt:
12/14/2005
Publication #:
US20060097367
Pub Dt:
05/11/2006
Title:
INTEGRATED CIRCUIT DEVICE HAVING FLEXIBLE LEADFRAME
26
Patent #:
7498664
Issue Dt:
03/03/2009
Application #:
11304862
Filing Dt:
12/14/2005
Publication #:
US20070132083
Pub Dt:
06/14/2007
Title:
SEMICONDUCTOR PACKAGE HAVING INCREASED RESISTANCE TO ELECTROSTATIC DISCHARGE
27
Patent #:
7406675
Issue Dt:
07/29/2008
Application #:
11305542
Filing Dt:
12/16/2005
Publication #:
US20070143734
Pub Dt:
06/21/2007
Title:
METHOD AND SYSTEM FOR IMPROVING AERIAL IMAGE SIMULATION SPEEDS
28
Patent #:
7415686
Issue Dt:
08/19/2008
Application #:
11311388
Filing Dt:
12/19/2005
Publication #:
US20070143648
Pub Dt:
06/21/2007
Title:
MEMORY TIMING MODEL WITH BACK-ANNOTATING
29
Patent #:
7546568
Issue Dt:
06/09/2009
Application #:
11311515
Filing Dt:
12/19/2005
Publication #:
US20070143725
Pub Dt:
06/21/2007
Title:
AUTOMATION OF TIE CELL INSERTION, OPTIMIZATION AND REPLACEMENT BY SCAN FLIP-FLOPS TO INCREASE FAULT COVERAGE
30
Patent #:
NONE
Issue Dt:
Application #:
11314649
Filing Dt:
12/21/2005
Publication #:
US20060093965
Pub Dt:
05/04/2006
Title:
Variable mask field exposure
31
Patent #:
7720556
Issue Dt:
05/18/2010
Application #:
11315959
Filing Dt:
12/21/2005
Publication #:
US20070142930
Pub Dt:
06/21/2007
Title:
WEB-ENABLED SOLUTIONS FOR MEMORY COMPILATION TO SUPPORT PRE-SALES ESTIMATION OF MEMORY SIZE, PERFORMANCE AND POWER DATA FOR MEMORY COMPONENTS
32
Patent #:
7514336
Issue Dt:
04/07/2009
Application #:
11321206
Filing Dt:
12/29/2005
Publication #:
US20070152294
Pub Dt:
07/05/2007
Title:
ROBUST SHALLOW TRENCH ISOLATION STRUCTURES AND A METHOD FOR FORMING SHALLOW TRENCH ISOLATION STRUCTURES
33
Patent #:
7480878
Issue Dt:
01/20/2009
Application #:
11321260
Filing Dt:
12/29/2005
Publication #:
US20070157140
Pub Dt:
07/05/2007
Title:
METHOD AND SYSTEM FOR LAYOUT VERSUS SCHEMATIC VALIDATION OF INTEGRATED CIRCUIT DESIGNS
34
Patent #:
7712066
Issue Dt:
05/04/2010
Application #:
11322103
Filing Dt:
12/29/2005
Publication #:
US20070164806
Pub Dt:
07/19/2007
Title:
AREA-EFFICIENT POWER SWITCHING CELL
35
Patent #:
7436040
Issue Dt:
10/14/2008
Application #:
11323398
Filing Dt:
12/29/2005
Publication #:
US20070259518
Pub Dt:
11/08/2007
Title:
METHOD AND APPARATUS FOR DIVERTING VOID DIFFUSION IN INTEGRATED CIRCUIT CONDUCTORS
36
Patent #:
7361965
Issue Dt:
04/22/2008
Application #:
11323400
Filing Dt:
12/29/2005
Publication #:
US20070155160
Pub Dt:
07/05/2007
Title:
METHOD AND APPARATUS FOR REDIRECTING VOID DIFFUSION AWAY FROM VIAS IN AN INTEGRATED CIRCUIT DESIGN
37
Patent #:
7434198
Issue Dt:
10/07/2008
Application #:
11323401
Filing Dt:
12/29/2005
Publication #:
US20070157152
Pub Dt:
07/05/2007
Title:
METHOD AND COMPUTER PROGRAM PRODUCT FOR DETECTING POTENTIAL FAILURES IN AN INTEGRATED CIRCUIT DESIGN AFTER OPTICAL PROXIMITY CORRECTION
38
Patent #:
7429733
Issue Dt:
09/30/2008
Application #:
11323405
Filing Dt:
12/29/2005
Publication #:
US20070152151
Pub Dt:
07/05/2007
Title:
METHOD AND SAMPLE FOR RADIATION MICROSCOPY INCLUDING A PARTICLE BEAM CHANNEL FORMED IN THE SAMPLE SOURCE
39
Patent #:
7458060
Issue Dt:
11/25/2008
Application #:
11323468
Filing Dt:
12/30/2005
Publication #:
US20070157153
Pub Dt:
07/05/2007
Title:
YIELD-LIMITING DESIGN-RULES-COMPLIANT PATTERN LIBRARY GENERATION AND LAYOUT INSPECTION
40
Patent #:
7334204
Issue Dt:
02/19/2008
Application #:
11324082
Filing Dt:
12/29/2005
Publication #:
US20070157143
Pub Dt:
07/05/2007
Title:
SYSTEM FOR AVOIDING FALSE PATH PESSIMISM IN ESTIMATING NET DELAY FOR AN INTEGRATED CIRCUIT DESIGN
41
Patent #:
7617427
Issue Dt:
11/10/2009
Application #:
11324084
Filing Dt:
12/29/2005
Publication #:
US20070157056
Pub Dt:
07/05/2007
Title:
METHOD AND APPARATUS FOR DETECTING DEFECTS IN INTEGRATED CIRCUIT DIE FROM STIMULATION OF STATISTICAL OUTLIER SIGNATURES
42
Patent #:
7409660
Issue Dt:
08/05/2008
Application #:
11324105
Filing Dt:
12/29/2005
Publication #:
US20070157145
Pub Dt:
07/05/2007
Title:
METHOD AND END CELL LIBRARY FOR AVOIDING SUBSTRATE NOISE IN AN INTEGRATED CIRCUIT
43
Patent #:
RE41516
Issue Dt:
08/17/2010
Application #:
11324119
Filing Dt:
12/30/2005
Title:
SOCKETLESS/BOARDLESS TEST INTERPOSER CARD
44
Patent #:
7737564
Issue Dt:
06/15/2010
Application #:
11334870
Filing Dt:
01/19/2006
Publication #:
US20070164451
Pub Dt:
07/19/2007
Title:
POWER CONFIGURATION METHOD FOR STRUCTURED ASICS
45
Patent #:
7220362
Issue Dt:
05/22/2007
Application #:
11337460
Filing Dt:
01/23/2006
Publication #:
US20060118523
Pub Dt:
06/08/2006
Title:
PLANARIZATION WITH REDUCED DISHING
46
Patent #:
7342316
Issue Dt:
03/11/2008
Application #:
11339540
Filing Dt:
01/26/2006
Publication #:
US20060124972
Pub Dt:
06/15/2006
Title:
CROSS-FILL PATTERN FOR METAL FILL LEVELS, POWER SUPPLY FILTERING, AND ANALOG CIRCUIT SHIELDING
47
Patent #:
7335565
Issue Dt:
02/26/2008
Application #:
11348597
Filing Dt:
02/07/2006
Publication #:
US20060128085
Pub Dt:
06/15/2006
Title:
METAL-OXIDE-SEMICONDUCTOR DEVICE HAVING IMPROVED PERFORMANCE AND RELIABILITY
48
Patent #:
7493576
Issue Dt:
02/17/2009
Application #:
11349356
Filing Dt:
02/07/2006
Publication #:
US20060245126
Pub Dt:
11/02/2006
Title:
CDM ESD EVENT PROTECTION IN APPLICATION CIRCUITS
49
Patent #:
7458044
Issue Dt:
11/25/2008
Application #:
11349358
Filing Dt:
02/07/2006
Publication #:
US20060245127
Pub Dt:
11/02/2006
Title:
CDM ESD EVENT SIMULATION AND REMEDIATION THEREOF IN APPLICATION CIRCUITS
50
Patent #:
7689965
Issue Dt:
03/30/2010
Application #:
11351091
Filing Dt:
02/09/2006
Publication #:
US20070186198
Pub Dt:
08/09/2007
Title:
GENERATION OF AN EXTRACTED TIMING MODEL FILE
51
Patent #:
7702050
Issue Dt:
04/20/2010
Application #:
11356685
Filing Dt:
02/17/2006
Publication #:
US20070206696
Pub Dt:
09/06/2007
Title:
METHOD AND SYSTEM FOR AN ADAPTIVE VBLAST RECEIVER FOR WIRELESS MULTIPLE INPUT MULTIPLE OUTPUT (MIMO) DETECTION
52
Patent #:
7693234
Issue Dt:
04/06/2010
Application #:
11359460
Filing Dt:
02/23/2006
Publication #:
US20070019747
Pub Dt:
01/25/2007
Title:
METHOD AND APPARATUS FOR INTERLEAVING IN A WIRELESS COMMUNICATION SYSTEM
53
Patent #:
7394028
Issue Dt:
07/01/2008
Application #:
11360200
Filing Dt:
02/23/2006
Publication #:
US20070194456
Pub Dt:
08/23/2007
Title:
FLEXIBLE CIRCUIT SUBSTRATE FOR FLIP-CHIP-ON-FLEX APPLICATIONS
54
Patent #:
7439119
Issue Dt:
10/21/2008
Application #:
11361430
Filing Dt:
02/24/2006
Publication #:
US20070202642
Pub Dt:
08/30/2007
Title:
THERMALLY STABLE BICMOS FABRICATION METHOD AND BIPOLAR JUNCTION TRANSISTORS FORMED ACCORDING TO THE METHOD
55
Patent #:
NONE
Issue Dt:
Application #:
11364142
Filing Dt:
02/27/2006
Publication #:
US20070204215
Pub Dt:
08/30/2007
Title:
Device for analyzing log files generated by process automation tools
56
Patent #:
8218517
Issue Dt:
07/10/2012
Application #:
11364751
Filing Dt:
02/28/2006
Publication #:
US20070201422
Pub Dt:
08/30/2007
Title:
METHOD AND APPARATUS FOR DUAL FREQUENCY TIMING ACQUISITION FOR COMPRESSED WCDMA COMMUNICATION NETWORKS
57
Patent #:
7476951
Issue Dt:
01/13/2009
Application #:
11368780
Filing Dt:
03/06/2006
Publication #:
US20060226553
Pub Dt:
10/12/2006
Title:
SELECTIVE ISOTROPIC ETCH FOR TITANIUM-BASED MATERIALS
58
Patent #:
7499722
Issue Dt:
03/03/2009
Application #:
11369363
Filing Dt:
03/07/2006
Publication #:
US20060154687
Pub Dt:
07/13/2006
Title:
PROXIMITY REGULATION SYSTEM FOR USE WITH A PORTABLE CELL PHONE AND A METHOD OF OPERATION THEREOF
59
Patent #:
7684522
Issue Dt:
03/23/2010
Application #:
11374705
Filing Dt:
03/14/2006
Publication #:
US20070030925
Pub Dt:
02/08/2007
Title:
METHOD AND SYSTEM FOR DETERMINING A LOG-LIKELIHOOD RATIO (LLR) CORRESPONDING TO EACH BIT OF A SYMBOL
60
Patent #:
7479695
Issue Dt:
01/20/2009
Application #:
11375302
Filing Dt:
03/14/2006
Publication #:
US20070216034
Pub Dt:
09/20/2007
Title:
LOW THERMAL RESISTANCE ASSEMBLY FOR FLIP CHIP APPLICATIONS
61
Patent #:
7509609
Issue Dt:
03/24/2009
Application #:
11376600
Filing Dt:
03/15/2006
Publication #:
US20070220466
Pub Dt:
09/20/2007
Title:
METHODS AND APPARATUS FOR REDUCING TIMING SKEW
62
Patent #:
7577928
Issue Dt:
08/18/2009
Application #:
11376781
Filing Dt:
03/15/2006
Publication #:
US20070220462
Pub Dt:
09/20/2007
Title:
VERIFICATION OF AN EXTRACTED TIMING MODEL FILE
63
Patent #:
7424693
Issue Dt:
09/09/2008
Application #:
11377778
Filing Dt:
03/16/2006
Publication #:
US20070094626
Pub Dt:
04/26/2007
Title:
METHODS FOR MEASUREMENT AND PREDICTION OF HOLD-TIME AND EXCEEDING HOLD TIME LIMITS DUE TO CELLS WITH TIED INPUT PINS
64
Patent #:
8601683
Issue Dt:
12/10/2013
Application #:
11379256
Filing Dt:
04/19/2006
Publication #:
US20060175081
Pub Dt:
08/10/2006
Title:
METHOD FOR ELECTRICAL INTERCONNECTION BETWEEN PRINTED WIRING BOARD LAYERS USING THROUGH HOLES WITH SOLID CORE CONDUCTIVE MATERIAL
65
Patent #:
NONE
Issue Dt:
Application #:
11381409
Filing Dt:
05/03/2006
Publication #:
US20060188793
Pub Dt:
08/24/2006
Title:
Adjustable Transmission Phase Shift Mask
66
Patent #:
7460211
Issue Dt:
12/02/2008
Application #:
11383171
Filing Dt:
05/12/2006
Publication #:
US20060191634
Pub Dt:
08/31/2006
Title:
APPARATUS FOR WAFER PATTERNING TO REDUCE EDGE EXCLUSION ZONE
67
Patent #:
7563669
Issue Dt:
07/21/2009
Application #:
11383670
Filing Dt:
05/16/2006
Publication #:
US20070267670
Pub Dt:
11/22/2007
Title:
INTEGRATED CIRCUIT WITH A TRENCH CAPACITOR STRUCTURE AND METHOD OF MANUFACTURE
68
Patent #:
7705473
Issue Dt:
04/27/2010
Application #:
11385086
Filing Dt:
03/21/2006
Publication #:
US20060157871
Pub Dt:
07/20/2006
Title:
METHODS AND APPARATUS FOR DETERMINING PAD HEIGHT FOR A WIRE-BONDING OPERATION IN AN INTEGRATED CIRCUIT
69
Patent #:
7282461
Issue Dt:
10/16/2007
Application #:
11385156
Filing Dt:
03/21/2006
Publication #:
US20060166517
Pub Dt:
07/27/2006
Title:
PHASE-SHIFTING MASK AND SEMICONDUCTOR DEVICE
70
Patent #:
7443042
Issue Dt:
10/28/2008
Application #:
11385245
Filing Dt:
03/21/2006
Publication #:
US20060158856
Pub Dt:
07/20/2006
Title:
METHODS AND APPARATUS FOR WIRE BONDING WITH WIRE LENGTH ADJUSTMENT IN AN INTEGRATED CIRCUIT
71
Patent #:
7312127
Issue Dt:
12/25/2007
Application #:
11389643
Filing Dt:
03/23/2006
Publication #:
US20060166496
Pub Dt:
07/27/2006
Title:
INCORPORATING DOPANTS TO ENHANCE THE DIELECTRIC PROPERTIES OF METAL SILICATES
72
Patent #:
NONE
Issue Dt:
Application #:
11390015
Filing Dt:
03/27/2006
Publication #:
US20060166429
Pub Dt:
07/27/2006
Title:
Vertical replacement-gate junction field-effect transistor
73
Patent #:
NONE
Issue Dt:
Application #:
11392375
Filing Dt:
03/29/2006
Publication #:
US20060166395
Pub Dt:
07/27/2006
Title:
High-density inter-die interconnect structure
74
Patent #:
8025201
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Assignors
1
HILCO PATENT ACQUISITION 56, LLC
Exec Dt:
01/24/2018
2
BELL SEMICONDUCTOR, LLC
Exec Dt:
01/24/2018
3
BELL NORTHERN RESEARCH, LLC
Exec Dt:
01/24/2018
Assignee
1
CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
225 W. WASHINGTON ST., 9TH FLOOR
CHICAGO, ILLINOIS 60606
Correspondence name and address
JAVIER J. RAMOS
1850 K STREET, NW, SUITE 1100
MILBANK, TWEED, HADLEY & MCCLOY, LLP
WASHINGTON, DC 20006

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