|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/21/2009
|
Application #:
|
11964920
|
Filing Dt:
|
12/27/2007
|
|
Publication #:
|
|
Pub Dt:
|
07/03/2008
| | | | |
|
Title:
|
FAILURE ANALYSIS AND TESTING OF SEMI-CONDUCTOR DEVICES USING INTELLIGENT SOFTWARE ON AUTOMATED TEST EQUIPMENT (ATE)
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/03/2009
|
Application #:
|
11968693
|
Filing Dt:
|
01/03/2008
|
|
Publication #:
|
|
Pub Dt:
|
05/01/2008
| | | | |
|
Title:
|
STRUCTURE AND METHOD FOR IMPROVED HEAT CONDUCTION FOR SEMICONDUCTOR DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/05/2009
|
Application #:
|
11968930
|
Filing Dt:
|
01/03/2008
|
|
Publication #:
|
|
Pub Dt:
|
05/01/2008
| | | | |
|
Title:
|
SYSTEM OF USING OFFSET GAGE FOR CMP POLISHING PAD ALIGNMENT AND ADJUSTMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/15/2011
|
Application #:
|
11973859
|
Filing Dt:
|
10/10/2007
|
|
Publication #:
|
|
Pub Dt:
|
04/16/2009
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGE INCLUDING WIRE BONDS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/10/2012
|
Application #:
|
11999168
|
Filing Dt:
|
12/04/2007
|
|
Publication #:
|
|
Pub Dt:
|
04/24/2008
| | | | |
|
Title:
|
METAL-OXIDE-SEMICONDUCTOR DEVICE HAVING TRENCHED DIFFUSION REGION AND METHOD OF FORMING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/09/2011
|
Application #:
|
12015925
|
Filing Dt:
|
01/17/2008
|
|
Publication #:
|
|
Pub Dt:
|
07/23/2009
| | | | |
|
Title:
|
SIGNAL DELAY SKEW REDUCTION SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/01/2009
|
Application #:
|
12018849
|
Filing Dt:
|
01/24/2008
|
|
Publication #:
|
|
Pub Dt:
|
06/05/2008
| | | | |
|
Title:
|
METHOD FOR REDIRECTING VOID DIFFUSION AWAY FROM VIAS IN AN INTEGRATED CIRCUIT DESIGN
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12021728
|
Filing Dt:
|
01/29/2008
|
|
Publication #:
|
|
Pub Dt:
|
06/26/2008
| | | | |
|
Title:
|
DAMASCENE REPLACEMENT METAL GATE PROCESS WITH CONTROLLED GATE PROFILE AND LENGTH USING Si1-xGex AS SACRIFICIAL MATERIAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/13/2011
|
Application #:
|
12034385
|
Filing Dt:
|
02/20/2008
|
|
Publication #:
|
|
Pub Dt:
|
08/20/2009
| | | | |
|
Title:
|
LOCATION-BASED SEARCH-RESULT RANKING FOR BLOG DOCUMENTS AND THE LIKE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/06/2010
|
Application #:
|
12034745
|
Filing Dt:
|
02/21/2008
|
|
Publication #:
|
|
Pub Dt:
|
08/27/2009
| | | | |
|
Title:
|
BALL GRID ARRAY PACKAGE LAYOUT SUPPORTING MANY VOLTAGE SPLITS AND FLEXIBLE SPLIT LOCATIONS
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12034750
|
Filing Dt:
|
02/21/2008
|
|
Publication #:
|
|
Pub Dt:
|
06/12/2008
| | | | |
|
Title:
|
Substrate Laser Marking
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/28/2011
|
Application #:
|
12038911
|
Filing Dt:
|
02/28/2008
|
|
Publication #:
|
|
Pub Dt:
|
09/03/2009
| | | | |
|
Title:
|
PROCESS OF GROUNDING HEAT SPREADER/STIFFENER TO A FLIP CHIP PACKAGE USING SOLDER AND FILM ADHESIVE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/09/2010
|
Application #:
|
12046169
|
Filing Dt:
|
03/11/2008
|
|
Publication #:
|
|
Pub Dt:
|
07/03/2008
| | | | |
|
Title:
|
PROBABILISTIC NOISE ANALYSIS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/02/2010
|
Application #:
|
12060387
|
Filing Dt:
|
04/01/2008
|
|
Publication #:
|
|
Pub Dt:
|
06/18/2009
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGE FOR HIGH-SPEED SIGNALS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/13/2012
|
Application #:
|
12061728
|
Filing Dt:
|
04/03/2008
|
|
Publication #:
|
|
Pub Dt:
|
10/08/2009
| | | | |
|
Title:
|
HEAT DISSIPATION FOR INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/17/2013
|
Application #:
|
12072478
|
Filing Dt:
|
02/26/2008
|
|
Publication #:
|
|
Pub Dt:
|
08/27/2009
| | | | |
|
Title:
|
Multiple derating factor sets for delay calculation and library generation in multi-corner STA sign-off flow
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/28/2009
|
Application #:
|
12079124
|
Filing Dt:
|
03/25/2008
|
|
Publication #:
|
|
Pub Dt:
|
07/24/2008
| | | | |
|
Title:
|
LEADFRAME DESIGNS FOR PLASTIC OVERMOLD PACKAGES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/22/2011
|
Application #:
|
12103825
|
Filing Dt:
|
04/16/2008
|
|
Publication #:
|
|
Pub Dt:
|
10/22/2009
| | | | |
|
Title:
|
ON CHIP LOCAL MOSFET SIZING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/14/2010
|
Application #:
|
12109501
|
Filing Dt:
|
04/25/2008
|
|
Publication #:
|
|
Pub Dt:
|
10/29/2009
| | | | |
|
Title:
|
UNIFIED LAYER STACK ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/09/2013
|
Application #:
|
12111836
|
Filing Dt:
|
04/29/2008
|
|
Publication #:
|
|
Pub Dt:
|
10/29/2009
| | | | |
|
Title:
|
OPTIMIZATION OF LIBRARY SLEW RATIO BASED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/12/2011
|
Application #:
|
12112076
|
Filing Dt:
|
04/30/2008
|
|
Publication #:
|
|
Pub Dt:
|
11/05/2009
| | | | |
|
Title:
|
HIGH VOLTAGE TOLERANT METAL-OXIDE-SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12114589
|
Filing Dt:
|
05/02/2008
|
|
Publication #:
|
|
Pub Dt:
|
11/13/2008
| | | | |
|
Title:
|
TRANSISTOR FABRICATION METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/19/2011
|
Application #:
|
12117379
|
Filing Dt:
|
05/08/2008
|
|
Publication #:
|
|
Pub Dt:
|
09/04/2008
| | | | |
|
Title:
|
YIELD PROFILE MANIPULATOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/30/2010
|
Application #:
|
12117381
|
Filing Dt:
|
05/08/2008
|
|
Publication #:
|
|
Pub Dt:
|
11/12/2009
| | | | |
|
Title:
|
OPTIMIZING TEST CODE GENERATION FOR VERIFICATION ENVIRONMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/07/2011
|
Application #:
|
12117760
|
Filing Dt:
|
05/09/2008
|
|
Publication #:
|
|
Pub Dt:
|
09/04/2008
| | | | |
|
Title:
|
METHOD AND COMPUTER PROGRAM FOR CONFIGURING AN INTEGRATED CIRCUIT DESIGN FOR STATIC TIMING ANALYSIS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/30/2009
|
Application #:
|
12119575
|
Filing Dt:
|
05/13/2008
|
|
Title:
|
PAD CURRENT SPLITTING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/28/2012
|
Application #:
|
12120894
|
Filing Dt:
|
05/15/2008
|
|
Publication #:
|
|
Pub Dt:
|
11/19/2009
| | | | |
|
Title:
|
CHARACTERIZING PERFORMANCE OF AN ELECTRONIC SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/17/2011
|
Application #:
|
12120965
|
Filing Dt:
|
05/15/2008
|
|
Publication #:
|
|
Pub Dt:
|
03/19/2009
| | | | |
|
Title:
|
RULES AND DIRECTIVES FOR VALIDATING CORRECT DATA USED IN THE DESIGN OF SEMICONDUCTOR PRODUCTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/08/2013
|
Application #:
|
12121363
|
Filing Dt:
|
05/15/2008
|
|
Publication #:
|
|
Pub Dt:
|
11/19/2009
| | | | |
|
Title:
|
FLIPCHIP BUMP PATTERNS FOR EFFICIENT I-MESH POWER DISTRIBUTION SCHEMES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/11/2011
|
Application #:
|
12122307
|
Filing Dt:
|
05/16/2008
|
|
Publication #:
|
|
Pub Dt:
|
10/23/2008
| | | | |
|
Title:
|
LANGUAGE AND TEMPLATES FOR USE IN THE DESIGN OF SEMICONDUCTOR PRODUCTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/05/2011
|
Application #:
|
12139185
|
Filing Dt:
|
06/13/2008
|
|
Publication #:
|
|
Pub Dt:
|
10/09/2008
| | | | |
|
Title:
|
ASYMMETRIC ALIGNMENT OF SUBSTRATE INTERCONNECT TO SEMICONDUCTOR DIE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/26/2013
|
Application #:
|
12140773
|
Filing Dt:
|
06/17/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/18/2008
| | | | |
|
Title:
|
APPLICATION OF GATE EDGE LINER TO MAINTAIN GATE LENGTH CD IN A REPLACEMENT GATE TRANSISTOR FLOW
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/24/2011
|
Application #:
|
12144248
|
Filing Dt:
|
06/23/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/24/2009
| | | | |
|
Title:
|
METHOD FOR ESTIMATION OF TRACE INFORMATION BANDWIDTH REQUIREMENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/29/2009
|
Application #:
|
12150846
|
Filing Dt:
|
05/01/2008
|
|
Publication #:
|
|
Pub Dt:
|
08/28/2008
| | | | |
|
Title:
|
ACCURATE PIN-BASED MEMORY POWER MODEL USING ARC-BASED CHARACTERIZATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/02/2010
|
Application #:
|
12151108
|
Filing Dt:
|
05/02/2008
|
|
Publication #:
|
|
Pub Dt:
|
11/05/2009
| | | | |
|
Title:
|
ELECTRONIC PACKAGES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/25/2010
|
Application #:
|
12154794
|
Filing Dt:
|
05/27/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/03/2009
| | | | |
|
Title:
|
METHOD OF MAKING ELECTRONIC ENTITIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/06/2011
|
Application #:
|
12156281
|
Filing Dt:
|
05/30/2008
|
|
Publication #:
|
|
Pub Dt:
|
09/25/2008
| | | | |
|
Title:
|
METHOD AND SYSTEM FOR REDUCING INTER-LAYER CAPACITANCE IN INTEGRATED CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/17/2010
|
Application #:
|
12160233
|
Filing Dt:
|
07/08/2008
|
|
Publication #:
|
|
Pub Dt:
|
01/01/2009
| | | | |
|
Title:
|
HIGH THERMAL PERFORMANCE PACKAGING FOR CIRCUIT DIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2012
|
Application #:
|
12160553
|
Filing Dt:
|
07/10/2008
|
|
Publication #:
|
|
Pub Dt:
|
09/30/2010
| | | | |
|
Title:
|
SOLDERING METHOD AND RELATED DEVICE FOR IMPROVED RESISTANCE TO BRITTLE FRACTURE WITH AN INTERMETALLIC COMPOUND REGION COUPLING A SOLDER MASS TO AN NI LAYER WHICH HAS A LOW CONCENTRATION OF P, WHEREIN THE AMOUNT OF P IN THE UNDERLYING NI LAYER IS CONTROLLED AS A FUN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/06/2009
|
Application #:
|
12163453
|
Filing Dt:
|
06/27/2008
|
|
Publication #:
|
|
Pub Dt:
|
10/23/2008
| | | | |
|
Title:
|
CONTROLLING WARPING IN INTEGRATED CIRCUIT DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/29/2009
|
Application #:
|
12167381
|
Filing Dt:
|
07/03/2008
|
|
Publication #:
|
|
Pub Dt:
|
11/06/2008
| | | | |
|
Title:
|
MASK SET FOR VARIABLE MASK FIELD EXPOSURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/09/2011
|
Application #:
|
12169814
|
Filing Dt:
|
07/09/2008
|
|
Publication #:
|
|
Pub Dt:
|
10/30/2008
| | | | |
|
Title:
|
ADVISORY ALERT OF LOW SIGNAL STRENGTH FOR CELL PHONE USER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/29/2009
|
Application #:
|
12171903
|
Filing Dt:
|
07/11/2008
|
|
Publication #:
|
|
Pub Dt:
|
11/20/2008
| | | | |
|
Title:
|
METHODS AND APPARATUS FOR WIRE BONDING WITH WIRE LENGTH ADJUSTMENT IN AN INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/09/2010
|
Application #:
|
12174479
|
Filing Dt:
|
07/16/2008
|
|
Publication #:
|
|
Pub Dt:
|
11/06/2008
| | | | |
|
Title:
|
PACKAGE CONFIGURATION AND MANUFACTURING METHOD ENABLING THE ADDITION OF DECOUPLING CAPACITORS TO STANDARD PACKAGE DESIGNS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/11/2013
|
Application #:
|
12182330
|
Filing Dt:
|
07/30/2008
|
|
Title:
|
ELECTRONIC DESIGN AUTOMATION TOOL AND METHOD FOR EMPLOYING UNSENSITIZED CRITICAL PATH INFORMATION TO REDUCE LEAKAGE POWER IN AN INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/11/2011
|
Application #:
|
12186159
|
Filing Dt:
|
08/05/2008
|
|
Publication #:
|
|
Pub Dt:
|
11/27/2008
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR MAPPING DESIGN MEMORIES TO INTEGRATED CIRCUIT LAYOUT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/18/2013
|
Application #:
|
12187464
|
Filing Dt:
|
08/07/2008
|
|
Publication #:
|
|
Pub Dt:
|
11/27/2008
| | | | |
|
Title:
|
Methods for Measurement and Prediction of Hold-Time and Exceeding Hold Time Limits Due to Cells with Tied Input Pins
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/28/2011
|
Application #:
|
12190784
|
Filing Dt:
|
08/13/2008
|
|
Title:
|
SYSTEM AND METHOD FOR REDUCING THE GENERATION OF INCONSEQUENTIAL VIOLATIONS RESULTING FROM TIMING ANALYSES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/12/2010
|
Application #:
|
12191171
|
Filing Dt:
|
08/13/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/11/2008
| | | | |
|
Title:
|
METHODS AND STRUCTURE FOR FORMING COPPER BARRIER LAYERS INTEGRAL WITH SEMICONDUCTOR SUBSTRATES STRUCTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/24/2012
|
Application #:
|
12193566
|
Filing Dt:
|
08/18/2008
|
|
Publication #:
|
|
Pub Dt:
|
02/18/2010
| | | | |
|
Title:
|
SYNTHESIZED LOGIC REPLACEMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/05/2011
|
Application #:
|
12194706
|
Filing Dt:
|
08/20/2008
|
|
Publication #:
|
|
Pub Dt:
|
02/25/2010
| | | | |
|
Title:
|
THERMAL MONITORING AND MANAGEMENT OF INTEGRATED CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/10/2012
|
Application #:
|
12201575
|
Filing Dt:
|
08/29/2008
|
|
Publication #:
|
|
Pub Dt:
|
01/01/2009
| | | | |
|
Title:
|
VIRTUAL DATA REPRESENTATION THROUGH SELECTIVE BIDIRECTIONAL TRANSLATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/27/2010
|
Application #:
|
12204290
|
Filing Dt:
|
09/04/2008
|
|
Publication #:
|
|
Pub Dt:
|
02/05/2009
| | | | |
|
Title:
|
PSEUDO LOW VOLUME RETICLE (PLVR) DESIGN FOR ASIC MANUFACTURING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/21/2011
|
Application #:
|
12206048
|
Filing Dt:
|
09/08/2008
|
|
Publication #:
|
|
Pub Dt:
|
06/04/2009
| | | | |
|
Title:
|
DUAL PATH STATIC TIMING ANALYSIS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/08/2013
|
Application #:
|
12206786
|
Filing Dt:
|
09/09/2008
|
|
Publication #:
|
|
Pub Dt:
|
03/11/2010
| | | | |
|
Title:
|
PACKAGE WITH POWER AND GROUND THROUGH VIA
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/17/2010
|
Application #:
|
12208929
|
Filing Dt:
|
09/11/2008
|
|
Publication #:
|
|
Pub Dt:
|
01/08/2009
| | | | |
|
Title:
|
THERMALLY STABLE BICMOS FABRICATION METHOD AND BIPOLAR JUNCTION TRANSISTOR FORMED ACCORDING TO THE METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/25/2011
|
Application #:
|
12211238
|
Filing Dt:
|
09/16/2008
|
|
Publication #:
|
|
Pub Dt:
|
03/18/2010
| | | | |
|
Title:
|
WAIVER MECHANISM FOR PHYSICAL VERIFICATION OF SYSTEM DESIGNS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2012
|
Application #:
|
12212736
|
Filing Dt:
|
09/18/2008
|
|
Publication #:
|
|
Pub Dt:
|
09/17/2009
| | | | |
|
Title:
|
AUTOMATED SPECIFICATION BASED FUNCTIONAL TEST GENERATION INFRASTRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/01/2010
|
Application #:
|
12220182
|
Filing Dt:
|
07/22/2008
|
|
Publication #:
|
|
Pub Dt:
|
01/28/2010
| | | | |
|
Title:
|
MANUFACTURE OF DEVICES INCLUDING SOLDER BUMPS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/15/2009
|
Application #:
|
12228720
|
Filing Dt:
|
08/15/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/18/2008
| | | | |
|
Title:
|
PLASTIC OVERMOLDED PACKAGES WITH MECHANCIALLY DECOUPLED LID ATTACH ATTACHMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2012
|
Application #:
|
12229446
|
Filing Dt:
|
08/22/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/25/2008
| | | | |
|
Title:
|
DISABLING UNUSED IO RESOURCES IN PLATFORM-BASED INTEGRATED CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/07/2012
|
Application #:
|
12240210
|
Filing Dt:
|
09/29/2008
|
|
Publication #:
|
|
Pub Dt:
|
04/01/2010
| | | | |
|
Title:
|
DESIGN OPTIMIZATION WITH ADAPTIVE BODY BIASING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/11/2010
|
Application #:
|
12243137
|
Filing Dt:
|
10/01/2008
|
|
Publication #:
|
|
Pub Dt:
|
01/29/2009
| | | | |
|
Title:
|
MULTIPLE DOPING LEVEL BIPOLAR JUNCTIONS TRANSISTORS AND METHOD FOR FORMING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/16/2011
|
Application #:
|
12243768
|
Filing Dt:
|
10/01/2008
|
|
Publication #:
|
|
Pub Dt:
|
04/01/2010
| | | | |
|
Title:
|
CONTROL SIGNAL SOURCE REPLICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/31/2012
|
Application #:
|
12246206
|
Filing Dt:
|
10/06/2008
|
|
Publication #:
|
|
Pub Dt:
|
07/30/2009
| | | | |
|
Title:
|
METHOD AND SYSTEM FOR SUBSPACE BEAMFORMING FOR NEAR CAPACITY MULTIPLE INPUT MULTIPLE OUTPUT (MIMO) PERFORMANCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/30/2013
|
Application #:
|
12247992
|
Filing Dt:
|
10/08/2008
|
|
Publication #:
|
|
Pub Dt:
|
11/12/2009
| | | | |
|
Title:
|
CRITICAL PATH MONITOR FOR AN INTEGRATED CIRCUIT AND METHOD OF OPERATION THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/30/2011
|
Application #:
|
12248016
|
Filing Dt:
|
10/08/2008
|
|
Publication #:
|
|
Pub Dt:
|
11/12/2009
| | | | |
|
Title:
|
ELECTRONIC DESIGN AUTOMATION TOOL AND METHOD FOR OPTIMIZING THE PLACEMENT OF PROCESS MONITORS IN AN INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/24/2012
|
Application #:
|
12248187
|
Filing Dt:
|
10/09/2008
|
|
Publication #:
|
|
Pub Dt:
|
04/16/2009
| | | | |
|
Title:
|
LOW DEPTH CIRCUIT DESIGN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/12/2013
|
Application #:
|
12248677
|
Filing Dt:
|
10/09/2008
|
|
Publication #:
|
|
Pub Dt:
|
04/15/2010
| | | | |
|
Title:
|
CHANNEL LENGTH SCALING FOR FOOTPRINT COMPATIBLE DIGITAL LIBRARY CELL DESIGN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/15/2012
|
Application #:
|
12251088
|
Filing Dt:
|
10/14/2008
|
|
Publication #:
|
|
Pub Dt:
|
04/15/2010
| | | | |
|
Title:
|
CIRCUIT TIMING ANALYSIS INCORPORATING THE EFFECTS OF TEMPERATURE INVERSION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/17/2012
|
Application #:
|
12251110
|
Filing Dt:
|
10/14/2008
|
|
Publication #:
|
|
Pub Dt:
|
04/15/2010
| | | | |
|
Title:
|
REDUCING PATH DELAY SENSITIVITY TO TEMPERATURE VARIATION IN TIMING-CRITICAL PATHS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/14/2011
|
Application #:
|
12253403
|
Filing Dt:
|
10/17/2008
|
|
Publication #:
|
|
Pub Dt:
|
02/12/2009
| | | | |
|
Title:
|
ELECTRICAL DEVICES HAVING ADJUSTABLE CAPACITANCE
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12256677
|
Filing Dt:
|
10/23/2008
|
|
Publication #:
|
|
Pub Dt:
|
02/26/2009
| | | | |
|
Title:
|
METHOD TO REDUCE BORON PENETRATION IN A SiGe BIPOLAR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/23/2009
|
Application #:
|
12283820
|
Filing Dt:
|
09/15/2008
|
|
Publication #:
|
|
Pub Dt:
|
01/22/2009
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGE AND SYSTEM INTERFACE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/05/2011
|
Application #:
|
12290054
|
Filing Dt:
|
10/27/2008
|
|
Publication #:
|
|
Pub Dt:
|
04/29/2010
| | | | |
|
Title:
|
MATERIAL REMOVING PROCESSES IN DEVICE FORMATION AND THE DEVICES FORMED THEREBY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/23/2011
|
Application #:
|
12315998
|
Filing Dt:
|
12/09/2008
|
|
Publication #:
|
|
Pub Dt:
|
04/09/2009
| | | | |
|
Title:
|
METHOD AND SYSTEM FOR OUTPUTTING A SEQUENCE OF COMMANDS AND DATA DESCRIBED BY A FLOWCHART
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/20/2010
|
Application #:
|
12319603
|
Filing Dt:
|
01/09/2009
|
|
Publication #:
|
|
Pub Dt:
|
05/21/2009
| | | | |
|
Title:
|
METHOD OF FABRICATING A VERTICAL TRANSISTOR AND CAPACITOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/31/2010
|
Application #:
|
12327987
|
Filing Dt:
|
12/04/2008
|
|
Publication #:
|
|
Pub Dt:
|
06/10/2010
| | | | |
|
Title:
|
PREFERENTIALLY COOLED ELECTRONIC DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/28/2012
|
Application #:
|
12331561
|
Filing Dt:
|
12/10/2008
|
|
Publication #:
|
|
Pub Dt:
|
09/24/2009
| | | | |
|
Title:
|
WIRE BONDING OVER ACTIVE CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/01/2011
|
Application #:
|
12336104
|
Filing Dt:
|
12/16/2008
|
|
Publication #:
|
|
Pub Dt:
|
04/16/2009
| | | | |
|
Title:
|
DECODER USING A MEMORY FOR STORING STATE METRICS IMPLEMENTING A DECODER TRELLIS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/08/2013
|
Application #:
|
12336472
|
Filing Dt:
|
12/16/2008
|
|
Publication #:
|
|
Pub Dt:
|
06/17/2010
| | | | |
|
Title:
|
METHOD FOR GENERATING TEST PATTERNS FOR SMALL DELAY DEFECTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/04/2012
|
Application #:
|
12337519
|
Filing Dt:
|
12/17/2008
|
|
Publication #:
|
|
Pub Dt:
|
04/23/2009
| | | | |
|
Title:
|
SEMICONDUCTOR PACKAGE HAVING INCREASED RESISTANCE TO ELECTROSTATIC DISCHARGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/2013
|
Application #:
|
12339407
|
Filing Dt:
|
12/19/2008
|
|
Publication #:
|
|
Pub Dt:
|
06/24/2010
| | | | |
|
Title:
|
FILL PATTERNING FOR SYMMETRICAL CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/10/2012
|
Application #:
|
12340234
|
Filing Dt:
|
12/19/2008
|
|
Publication #:
|
|
Pub Dt:
|
06/18/2009
| | | | |
|
Title:
|
MOMENT COMPUTATION ALGORITHMS IN VLSI SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/16/2010
|
Application #:
|
12340813
|
Filing Dt:
|
12/22/2008
|
|
Publication #:
|
|
Pub Dt:
|
04/23/2009
| | | | |
|
Title:
|
INDUCTOR FORMED IN AN INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/01/2011
|
Application #:
|
12344016
|
Filing Dt:
|
12/24/2008
|
|
Publication #:
|
|
Pub Dt:
|
06/24/2010
| | | | |
|
Title:
|
HOT-ELECTRON INJECTION TESTING OF TRANSISTORS ON A WAFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2012
|
Application #:
|
12347916
|
Filing Dt:
|
12/31/2008
|
|
Publication #:
|
|
Pub Dt:
|
07/01/2010
| | | | |
|
Title:
|
ARCHITECTURALLY INDEPENDENT NOISE SENSITIVITY ANALYSIS OF INTEGRATED CIRCUITS HAVING A MEMORY STORAGE DEVICE AND A NOISE SENSITIVITY ANALYZER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/09/2013
|
Application #:
|
12354768
|
Filing Dt:
|
01/15/2009
|
|
Publication #:
|
|
Pub Dt:
|
07/30/2009
| | | | |
|
Title:
|
PROGRAMMABLE NANOTUBE INTERCONNECT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/20/2011
|
Application #:
|
12356600
|
Filing Dt:
|
01/21/2009
|
|
Publication #:
|
|
Pub Dt:
|
05/21/2009
| | | | |
|
Title:
|
ROBUST SHALLOW TRENCH ISOLATION STRUCTURES AND A METHOD FOR FORMING SHALLOW TRENCH ISOLATION STRUCTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/22/2012
|
Application #:
|
12360850
|
Filing Dt:
|
01/27/2009
|
|
Publication #:
|
|
Pub Dt:
|
06/25/2009
| | | | |
|
Title:
|
RF TRANSCEIVER HAVING ADAPTIVE MODULATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/12/2014
|
Application #:
|
12364918
|
Filing Dt:
|
02/03/2009
|
|
Publication #:
|
|
Pub Dt:
|
02/04/2010
| | | | |
|
Title:
|
METHODS FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING VOLTAGE SCALING AND INTEGRATED CIRCUITS DESIGNED THEREBY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/02/2012
|
Application #:
|
12365010
|
Filing Dt:
|
02/03/2009
|
|
Publication #:
|
|
Pub Dt:
|
02/11/2010
| | | | |
|
Title:
|
SYSTEMATIC, NORMALIZED METRIC FOR ANALYZING AND COMPARING OPTIMIZATION TECHNIQUES FOR INTEGRATED CIRCUITS EMPLOYING VOLTAGE SCALING AND INTEGRATED CIRCUITS DESIGNED THEREBY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/20/2011
|
Application #:
|
12365084
|
Filing Dt:
|
02/03/2009
|
|
Publication #:
|
|
Pub Dt:
|
11/12/2009
| | | | |
|
Title:
|
SYSTEMATIC BENCHMARKING SYSTEM AND METHOD FOR STANDARDIZED DATA CREATION, ANALYSIS AND COMPARISON OF SEMICONDUCTOR TECHNOLOGY NODE CHARACTERISTICS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2012
|
Application #:
|
12367078
|
Filing Dt:
|
02/06/2009
|
|
Publication #:
|
|
Pub Dt:
|
06/04/2009
| | | | |
|
Title:
|
PORTABLE CELL PHONE AND A PROXIMITY REGULATION SYSTEM FOR USE WITH A PORTABLE CELL PHONE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/27/2012
|
Application #:
|
12380058
|
Filing Dt:
|
02/23/2009
|
|
Publication #:
|
|
Pub Dt:
|
10/22/2009
| | | | |
|
Title:
|
SYSTEM AND METHOD FOR DATA CARD EMULATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/17/2013
|
Application #:
|
12388741
|
Filing Dt:
|
02/19/2009
|
|
Publication #:
|
|
Pub Dt:
|
06/11/2009
| | | | |
|
Title:
|
INTELLIGENT TIMING ANALYSIS AND CONSTRAINT GENERATION GUI
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/18/2012
|
Application #:
|
12421198
|
Filing Dt:
|
04/09/2009
|
|
Publication #:
|
|
Pub Dt:
|
10/14/2010
| | | | |
|
Title:
|
AUTOMATED TIMING OPTIMIZATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2013
|
Application #:
|
12421481
|
Filing Dt:
|
04/09/2009
|
|
Publication #:
|
|
Pub Dt:
|
10/14/2010
| | | | |
|
Title:
|
METHOD AND AN APPARATUS FOR EVALUATING SMALL DELAY DEFECT COVERAGE OF A TEST PATTERN SET ON AN IC
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/18/2012
|
Application #:
|
12423001
|
Filing Dt:
|
04/14/2009
|
|
Publication #:
|
|
Pub Dt:
|
10/14/2010
| | | | |
|
Title:
|
SYSTEM AND METHOD FOR CLOCK OPTIMIZATION TO ACHIEVE TIMING SIGNOFF IN AN ELECTRONIC CIRCUIT AND ELECTRONIC DESIGN AUTOMATION TOOL INCORPORATING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2013
|
Application #:
|
12430025
|
Filing Dt:
|
04/24/2009
|
|
Publication #:
|
|
Pub Dt:
|
08/26/2010
| | | | |
|
Title:
|
IDLE MODE POWER CONSUMPTION REDUCTION IN WIRELESS COMMUNICATIONS
|
|
