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Total properties:
22
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Patent #:
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Issue Dt:
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04/30/2002
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Application #:
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09656675
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Filing Dt:
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09/07/2000
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Title:
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USING A NEGATIVE GATE ERASE TO INCREASE THE CYCLING ENDURANCE OF A NON-VOLATILE MEMORY CELL WITH AN OXIDE-NITRIDE-OXIDE (ONO) STRUCTURE
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Patent #:
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Issue Dt:
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03/12/2002
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Application #:
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09657029
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Filing Dt:
|
09/07/2000
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Title:
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Using negative gate erase voltage to simultaneously erase two bits from a non-volatile memory cell with an oxide-nitride-oxide (ONO) gate structure
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Patent #:
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Issue Dt:
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04/15/2003
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Application #:
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09657143
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Filing Dt:
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09/07/2000
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Title:
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USING A NEGATIVE GATE ERASE VOLTAGE APPLIED IN STEPS OF DECREASING AMOUNTS TO REDUCE ERASE TIME FOR A NON-VOLATILE MEMORY CELL WITH AN OXIDE-NITRIDE-OXIDE (ONO) STRUCTURE
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Patent #:
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Issue Dt:
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06/03/2003
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Application #:
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09909527
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Filing Dt:
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07/20/2001
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Title:
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MICROCONTROLLER INPUT/OUTPUT NODES WITH BOTH PROGRAMMABLE PULL-UP AND PULL-DOWN RESISTIVE LOADS AND PROGRAMMABLE DRIVE STRENGTH
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Patent #:
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Issue Dt:
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03/23/2004
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Application #:
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09920378
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Filing Dt:
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07/31/2001
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Title:
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SEMICONDUCTOR DEVICE HAVING SILICON-RICH LAYER AND METHOD OF MANUFACTURING SUCH A DEVICE
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Patent #:
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Issue Dt:
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12/23/2003
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Application #:
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09929829
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Filing Dt:
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08/13/2001
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Title:
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METHOD TO ELIMINATE INVERSE NARROW WIDTH EFFECT IN SMALL GEOMETRY MOS TRANSISTORS
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Patent #:
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Issue Dt:
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05/20/2003
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Application #:
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09968465
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Filing Dt:
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10/01/2001
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Publication #:
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Pub Dt:
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05/08/2003
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Title:
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SALICIDED GATE FOR VIRTUAL GROUND ARRAYS
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Patent #:
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Issue Dt:
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01/06/2004
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Application #:
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10036757
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Filing Dt:
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12/31/2001
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Title:
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USE OF HIGH-K DIELECTRIC MATERIALS IN MODIFIED ONO STRUCTURE FOR SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
|
12/07/2004
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Application #:
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10054515
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Filing Dt:
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10/22/2001
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Title:
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METHOD OF MANUFACTURING A TOP INSULATING LAYER FOR A SONOS-TYPE DEVICE
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Patent #:
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Issue Dt:
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11/29/2005
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Application #:
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10184715
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Filing Dt:
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06/28/2002
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Title:
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METHOD OF MANUFACTURING AN OXIDE-NITRIDE-OXIDE (ONO) DIELECTIC FOR SONOS-TYPE DEVICES
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Patent #:
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Issue Dt:
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11/16/2004
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Application #:
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10185470
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Filing Dt:
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06/28/2002
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Title:
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METHOD OF MANUFACTURING A DIELECTRIC LAYER FOR A SILICON-OXIDE-NITRIDE-OXIDE-SILICON (SONOS) TYPE DEVICES
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Patent #:
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Issue Dt:
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12/20/2005
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Application #:
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10308410
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Filing Dt:
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12/03/2002
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Title:
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ALUMINUM-FILLED VIA STRUCTURE WITH BARRIER LAYER
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Patent #:
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Issue Dt:
|
10/12/2004
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Application #:
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10646080
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Filing Dt:
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08/22/2003
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Title:
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USE OF HIGH-K DIELECTRIC MATERIAL IN MODIFIED ONO STRUCTURE FOR SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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12/21/2004
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Application #:
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10739674
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Filing Dt:
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12/18/2003
|
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Title:
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METHOD TO ELIMINATE INVERSE NARROW WIDTH EFFECT IN SMALL GEOMETRY MOS TRANSISTORS
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|
|
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Patent #:
|
|
Issue Dt:
|
11/18/2008
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Application #:
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11097527
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Filing Dt:
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03/31/2005
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Publication #:
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Pub Dt:
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10/05/2006
| | | | |
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Title:
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CIRCUIT AND METHOD FOR MONITORING THE STATUS OF A CLOCK SIGNAL
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|
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Patent #:
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Issue Dt:
|
03/23/2010
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Application #:
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11321854
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Filing Dt:
|
12/29/2005
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|
Publication #:
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|
Pub Dt:
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07/05/2007
| | | | |
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Title:
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LOW POWER BANDGAP REFERENCE CIRCUIT WITH INCREASED ACCURACY AND REDUCED AREA CONSUMPTION
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Patent #:
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Issue Dt:
|
02/09/2010
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Application #:
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11391535
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Filing Dt:
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03/28/2006
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Title:
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MEMORY DEVICE AND METHOD FOR FAST CROSS ROW DATA ACCESS
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Patent #:
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|
Issue Dt:
|
02/17/2009
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Application #:
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11425634
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Filing Dt:
|
06/21/2006
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Title:
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AGILE, LOW PHASE NOISE CLOCK SYNTHESIZER AND JITTER ATTENUATOR
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|
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Patent #:
|
|
Issue Dt:
|
03/10/2009
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Application #:
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11512545
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Filing Dt:
|
08/29/2006
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Publication #:
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|
Pub Dt:
|
06/07/2007
| | | | |
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Title:
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POINT AND CLICK EXPRESSION BUILDER
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|
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Patent #:
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NONE
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Issue Dt:
|
|
Application #:
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11588543
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Filing Dt:
|
10/27/2006
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Publication #:
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|
Pub Dt:
|
05/03/2007
| | | | |
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Title:
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SWITCH PRE-DRIVER SYSTEM AND METHOD
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|
|
|
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Patent #:
|
|
Issue Dt:
|
04/14/2009
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Application #:
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11699951
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Filing Dt:
|
01/30/2007
|
|
Title:
|
DELAY CIRCUIT LIMIT DETECTION CIRCUIT AND METHOD
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/17/2012
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Application #:
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12690067
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Filing Dt:
|
01/19/2010
|
|
Title:
|
HIGH VOLTAGE SWITCH PRE-DRIVER CIRCUIT
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|
