Patent Assignment Details
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For pending or abandoned applications please consult USPTO staff.
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Reel/Frame: | 045467/0534 | |
| Pages: | 18 |
| | Recorded: | 04/06/2018 | | |
Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
10
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Patent #:
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Issue Dt:
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02/19/2019
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Application #:
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15936759
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Filing Dt:
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03/27/2018
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Title:
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Method for Processing a Semiconductor Wafer Using Non-Contact Electrical Measurements Indicative of at Least One Tip-to-Tip Short or Leakage, at Least One Tip-to-Side Short or Leakage, and at Least One Side-to-Side Short or Leakage, Where Such Measurements Are Obtained from Non-Contact Pads Associated with Respective Tip-to-Tip Short, Tip-to-Side Short, and Side-to-Side Short Test Areas
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Patent #:
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Issue Dt:
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02/05/2019
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Application #:
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15936825
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Filing Dt:
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03/27/2018
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Title:
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Method for Processing a Semiconductor Wafer Using Non-Contact Electrical Measurements Indicative of at Least One Tip-to-Tip Short or Leakage, at Least One Tip-to-Side Short or Leakage, and at Least One Chamfer Short or Leakage, Where Such Measurements Are Obtainedfrom Non-Contact Pads Associated with Respective Tip-to-Tip Short, Tip-to-Side Short, and Chamfer Short Test Areas
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Patent #:
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Issue Dt:
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02/19/2019
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Application #:
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15936934
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Filing Dt:
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03/27/2018
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Title:
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Method for Processing a Semiconductor Wafer Using Non-Contact Electrical Measurements Indicative of at Least One Tip-to-Tip Short or Leakage, at Least One Tip-to-Side Short or Leakage, and at Least One Corner Short or Leakage, Where Such Measurements Are Obtained from Non-Contact Pads Associated with Respective Tip-to-Tip Short, Tip-to-Side Short, and Corner Short Test Areas
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Patent #:
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Issue Dt:
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02/05/2019
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Application #:
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15937182
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Filing Dt:
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03/27/2018
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Title:
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Method for Processing a Semiconductor Wafer Using Non-Contact Electrical Measurements Indicative of at Least One Tip-to-Tip Short or Leakage, at Least One Side-to-Side Short or Leakage, and at Least One Chamfer Short or Leakage, Where Such Measurements Are Obtained from Non-Contact Pads Associated with Respective Tip-to-Tip Short, Side-to-Side Short, and Chamfer Short Test Areas
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Patent #:
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Issue Dt:
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02/05/2019
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Application #:
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15937356
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Filing Dt:
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03/27/2018
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Title:
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Method for Processing a Semiconductor Wafer Using Non-Contact Electrical Measurements Indicative of at Least One Tip-to-Tip Short or Leakage, at Least One Side-to-Side Short or Leakage, and at Least One Via Open or Resistance, Where Such Measurements Are Obtained from Non-Contact Pads Associated with Respective Tip-to-Tip Short, Side-to-Side Short, and Via Open Test Areas
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Patent #:
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Issue Dt:
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02/05/2019
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Application #:
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15942470
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Filing Dt:
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03/31/2018
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Title:
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Method for Processing a Semiconductor Wafer Using Non-Contact Electrical Measurements Indicative of at Least One Tip-to-Side Short or Leakage, at Least One Chamfer Short or Leakage, and at Least One Corner Short or Leakage, Where Such Measurements Are Obtained from Non-Contact Pads Associated with Respective Tip-to-Side Short, Chamfer Short, and Corner Short Test Areas
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Patent #:
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Issue Dt:
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02/05/2019
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Application #:
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15942473
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Filing Dt:
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03/31/2018
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Title:
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Method for Processing a Semiconductor Wafer Using Non-Contact Electrical Measurements Indicative of at Least One Tip-to-Side Short or Leakage, at Least One Chamfer Short or Leakage, and at Least One Via Open or Resistance, Where Such Measurements Are Obtained fromNon-Contact Pads Associated with Respective Tip-to-Side Short, Chamfer Short, and Via Open Test Areas
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Patent #:
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Issue Dt:
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12/01/2020
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Application #:
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15942475
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Filing Dt:
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03/31/2018
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Title:
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Method for Processing a Semiconductor Wafer Using Non-Contact Electrical Measurements Indicative of at Least One Tip-to-Side Short or Leakage, at Least One Corner Short or Leakage, and at Least One Via Open or Resistance, Where Such Measurements Are Obtained from Non-Contact Pads Associated with Respective Tip-to-Side Short, Corner Short, and Via Open Test Areas
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Patent #:
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Issue Dt:
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02/05/2019
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Application #:
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15942483
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Filing Dt:
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03/31/2018
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Title:
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Method for Processing a Semiconductor Wafer Using Non-Contact Electrical Measurements Indicative of at Least One Side-to-Side Short or Leakage, at Least One Corner Short or Leakage, and at Least One Via Open or Resistance, Where Such Measurements Are Obtained fromNon-Contact Pads Associated with Respective Side-to-Side Short, Corner Short, and Via Open Test Areas
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Patent #:
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Issue Dt:
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02/05/2019
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Application #:
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15942485
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Filing Dt:
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03/31/2018
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Title:
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Method for Processing a Semiconductor Wafer Using Non-Contact Electrical Measurements Indicative of at Least One Chamfer Short or Leakage, at Least One Corner Short or Leakage, and at Least One Via Open or Resistance, Where Such Measurements Are Obtained from Non-Contact Pads Associated with Respective Chamfer Short, Corner Short, and Via Open Test Areas
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Assignee
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333 W. SAN CARLOS ST. |
STE 1000 |
SAN JOSE, CALIFORNIA 95110 |
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Correspondence name and address
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DAVID GARROD, PH.D., ESQ.
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711 IVY STREET
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PITTSBURGH, PA 15232
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