skip navigationU S P T O SealUnited States Patent and Trademark Office AOTW logo
Home|Site Index|Search|Guides|Contacts|eBusiness|eBiz alerts|News|Help
Assignments on the Web > Patent Query
Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:045467/0534   Pages: 18
Recorded: 04/06/2018
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 10
1
Patent #:
Issue Dt:
02/19/2019
Application #:
15936759
Filing Dt:
03/27/2018
Title:
Method for Processing a Semiconductor Wafer Using Non-Contact Electrical Measurements Indicative of at Least One Tip-to-Tip Short or Leakage, at Least One Tip-to-Side Short or Leakage, and at Least One Side-to-Side Short or Leakage, Where Such Measurements Are Obtained from Non-Contact Pads Associated with Respective Tip-to-Tip Short, Tip-to-Side Short, and Side-to-Side Short Test Areas
2
Patent #:
Issue Dt:
02/05/2019
Application #:
15936825
Filing Dt:
03/27/2018
Title:
Method for Processing a Semiconductor Wafer Using Non-Contact Electrical Measurements Indicative of at Least One Tip-to-Tip Short or Leakage, at Least One Tip-to-Side Short or Leakage, and at Least One Chamfer Short or Leakage, Where Such Measurements Are Obtainedfrom Non-Contact Pads Associated with Respective Tip-to-Tip Short, Tip-to-Side Short, and Chamfer Short Test Areas
3
Patent #:
Issue Dt:
02/19/2019
Application #:
15936934
Filing Dt:
03/27/2018
Title:
Method for Processing a Semiconductor Wafer Using Non-Contact Electrical Measurements Indicative of at Least One Tip-to-Tip Short or Leakage, at Least One Tip-to-Side Short or Leakage, and at Least One Corner Short or Leakage, Where Such Measurements Are Obtained from Non-Contact Pads Associated with Respective Tip-to-Tip Short, Tip-to-Side Short, and Corner Short Test Areas
4
Patent #:
Issue Dt:
02/05/2019
Application #:
15937182
Filing Dt:
03/27/2018
Title:
Method for Processing a Semiconductor Wafer Using Non-Contact Electrical Measurements Indicative of at Least One Tip-to-Tip Short or Leakage, at Least One Side-to-Side Short or Leakage, and at Least One Chamfer Short or Leakage, Where Such Measurements Are Obtained from Non-Contact Pads Associated with Respective Tip-to-Tip Short, Side-to-Side Short, and Chamfer Short Test Areas
5
Patent #:
Issue Dt:
02/05/2019
Application #:
15937356
Filing Dt:
03/27/2018
Title:
Method for Processing a Semiconductor Wafer Using Non-Contact Electrical Measurements Indicative of at Least One Tip-to-Tip Short or Leakage, at Least One Side-to-Side Short or Leakage, and at Least One Via Open or Resistance, Where Such Measurements Are Obtained from Non-Contact Pads Associated with Respective Tip-to-Tip Short, Side-to-Side Short, and Via Open Test Areas
6
Patent #:
Issue Dt:
02/05/2019
Application #:
15942470
Filing Dt:
03/31/2018
Title:
Method for Processing a Semiconductor Wafer Using Non-Contact Electrical Measurements Indicative of at Least One Tip-to-Side Short or Leakage, at Least One Chamfer Short or Leakage, and at Least One Corner Short or Leakage, Where Such Measurements Are Obtained from Non-Contact Pads Associated with Respective Tip-to-Side Short, Chamfer Short, and Corner Short Test Areas
7
Patent #:
Issue Dt:
02/05/2019
Application #:
15942473
Filing Dt:
03/31/2018
Title:
Method for Processing a Semiconductor Wafer Using Non-Contact Electrical Measurements Indicative of at Least One Tip-to-Side Short or Leakage, at Least One Chamfer Short or Leakage, and at Least One Via Open or Resistance, Where Such Measurements Are Obtained fromNon-Contact Pads Associated with Respective Tip-to-Side Short, Chamfer Short, and Via Open Test Areas
8
Patent #:
Issue Dt:
12/01/2020
Application #:
15942475
Filing Dt:
03/31/2018
Title:
Method for Processing a Semiconductor Wafer Using Non-Contact Electrical Measurements Indicative of at Least One Tip-to-Side Short or Leakage, at Least One Corner Short or Leakage, and at Least One Via Open or Resistance, Where Such Measurements Are Obtained from Non-Contact Pads Associated with Respective Tip-to-Side Short, Corner Short, and Via Open Test Areas
9
Patent #:
Issue Dt:
02/05/2019
Application #:
15942483
Filing Dt:
03/31/2018
Title:
Method for Processing a Semiconductor Wafer Using Non-Contact Electrical Measurements Indicative of at Least One Side-to-Side Short or Leakage, at Least One Corner Short or Leakage, and at Least One Via Open or Resistance, Where Such Measurements Are Obtained fromNon-Contact Pads Associated with Respective Side-to-Side Short, Corner Short, and Via Open Test Areas
10
Patent #:
Issue Dt:
02/05/2019
Application #:
15942485
Filing Dt:
03/31/2018
Title:
Method for Processing a Semiconductor Wafer Using Non-Contact Electrical Measurements Indicative of at Least One Chamfer Short or Leakage, at Least One Corner Short or Leakage, and at Least One Via Open or Resistance, Where Such Measurements Are Obtained from Non-Contact Pads Associated with Respective Chamfer Short, Corner Short, and Via Open Test Areas
Assignors
1
Exec Dt:
04/21/2016
2
Exec Dt:
04/15/2016
3
Exec Dt:
04/20/2016
4
Exec Dt:
05/06/2016
5
Exec Dt:
04/13/2016
6
Exec Dt:
04/12/2016
7
Exec Dt:
04/28/2016
8
Exec Dt:
04/26/2016
9
Exec Dt:
04/13/2016
10
Exec Dt:
04/13/2016
11
Exec Dt:
04/12/2016
12
Exec Dt:
04/18/2016
13
Exec Dt:
04/14/2016
14
Exec Dt:
04/15/2016
15
Exec Dt:
04/28/2016
16
Exec Dt:
04/25/2016
17
Exec Dt:
04/18/2016
18
Exec Dt:
04/21/2016
19
Exec Dt:
04/26/2016
20
Exec Dt:
04/13/2016
21
Exec Dt:
04/28/2016
22
Exec Dt:
04/13/2016
23
Exec Dt:
04/13/2016
24
Exec Dt:
04/12/2016
25
Exec Dt:
04/21/2016
26
Exec Dt:
04/13/2016
Assignee
1
333 W. SAN CARLOS ST.
STE 1000
SAN JOSE, CALIFORNIA 95110
Correspondence name and address
DAVID GARROD, PH.D., ESQ.
711 IVY STREET
PITTSBURGH, PA 15232

Search Results as of: 05/04/2024 06:23 AM
If you have any comments or questions concerning the data displayed, contact PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified: August 25, 2017 v.2.6
| .HOME | INDEX| SEARCH | eBUSINESS | CONTACT US | PRIVACY STATEMENT