Patent Assignment Details
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Reel/Frame: | 045920/0492 | |
| Pages: | 4 |
| | Recorded: | 05/29/2018 | | |
Attorney Dkt #: | TSMP20180458US00 |
Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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Issue Dt:
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12/24/2019
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Application #:
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15991184
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Filing Dt:
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05/29/2018
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Publication #:
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Pub Dt:
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12/05/2019
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Title:
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Methods of Manufacturing Transistor Gate Structures by Local Thinning of Dummy Gate Stacks using an Etch Barrier
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Assignee
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8, LI-HSIN RD. 6 |
HSINCHU SCIENCE PARK |
HSINCHU, TAIWAN 300-78 |
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Correspondence name and address
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SLATER MATSIL, LLP/TSMC
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17950 PRESTON ROAD, SUITE 1000
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DALLAS, TX 75252
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