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Patent #:
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Issue Dt:
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12/05/2000
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Application #:
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09216978
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Filing Dt:
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12/21/1998
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Title:
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"STACK ARRRANGEMENT FOR TWO SEMICONDUCTOR MEMORY CHIPS AND PRINTED BOARD FOR ACCEPTING A PURALITY OF SUCH STACK ARRANGEMENTS"
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Patent #:
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Issue Dt:
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12/05/2000
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Application #:
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09243973
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Filing Dt:
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02/04/1999
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Title:
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PROGRAM/ERASE ENDURANCE OF EEPROM MEMORY CELLS
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Patent #:
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Issue Dt:
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11/14/2000
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Application #:
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09243974
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Filing Dt:
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02/04/1999
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Title:
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REDUNDANCY METHOD AND STRUCTURE FOR 2-BIT NON-VOLATILE MEMORY CELLS
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Patent #:
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Issue Dt:
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06/27/2000
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Application #:
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09243976
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Filing Dt:
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02/04/1999
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Title:
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BIT LINE CONTROL CIRCUIT FOR A MEMORY ARRAY USING 2-BIT NON-VOLATILE MEMORY CELLS
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Patent #:
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Issue Dt:
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02/12/2002
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Application #:
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09244316
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Filing Dt:
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02/04/1999
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Title:
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METHODS FOR FABRICATING A SEMICONDUCTOR CHIP HAVING CMOS DEVICES AND A FIELDLESS ARRAY
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Patent #:
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Issue Dt:
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01/30/2001
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Application #:
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09244317
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Filing Dt:
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02/04/1999
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Title:
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EEPROM ARRAY USING 2-BIT NON-VOLATILE MEMORY CELLS WITH SERIAL READ OPERATIONS
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Patent #:
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Issue Dt:
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07/03/2001
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Application #:
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09244529
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Filing Dt:
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02/04/1999
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Title:
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EEPROM ARRAY USING 2-BIT NON-VOLATILE MEMORY CELLS AND METHOD OF IMPLEMENTING SAME
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Patent #:
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Issue Dt:
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03/28/2000
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Application #:
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09258059
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Filing Dt:
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02/26/1999
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Title:
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PROGRAMMABLE CONFIGURATION FOR EEPROMS INCLUDING 2-BIT NON-VOLATILE MEMORY CELL ARRAYS
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Patent #:
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Issue Dt:
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04/17/2001
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Application #:
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09340979
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Filing Dt:
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06/28/1999
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Title:
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AREA EFFICIENT COLUMN SELECT CIRCUITRY FOR 2-BIT NON-VOLATILE MEMORY CELLS
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Patent #:
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Issue Dt:
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12/11/2001
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Application #:
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09460277
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Filing Dt:
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12/13/1999
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Title:
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DEVICE FOR PROTECTION OF SENSITIVE GATE DIELECTRICS OF ADVANCED NON-VOLATILE MEMORY DEVICES FROM DAMAGE DUE TO PLASMA CHARGING
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Patent #:
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Issue Dt:
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10/02/2001
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Application #:
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09474376
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Filing Dt:
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12/29/1999
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Title:
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STRUCTURE AND METHOD FOR PROTECTING INTEGRATED CIRCUITS DURING PLASMA PROCESSING
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Patent #:
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Issue Dt:
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10/01/2002
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Application #:
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09522245
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Filing Dt:
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03/09/2000
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Title:
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METHODS FOR MAKING SEMICONDUCTOR CHIP HAVING BOTH SELF ALIGNED SILICIDE REGIONS AND NON-SELF ALIGNED SILICIDE REGIONS
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Patent #:
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Issue Dt:
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01/15/2002
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Application #:
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09730611
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Filing Dt:
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12/05/2000
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Title:
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Content-addressable memory for virtual ground flash architectures
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Patent #:
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Issue Dt:
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02/26/2002
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Application #:
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09821336
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Filing Dt:
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03/28/2001
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Title:
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Symmetrical non-volatile memory array architecture without neighbor effect
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Patent #:
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Issue Dt:
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07/16/2002
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Application #:
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09927277
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Filing Dt:
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08/09/2001
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Title:
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METHOD AND APPARATUS FOR CONTROLLING ERASE OPERATIONS OF A NON-VOLATILE MEMORY SYSTEM
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Patent #:
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Issue Dt:
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03/11/2003
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Application #:
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09963912
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Filing Dt:
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09/25/2001
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Publication #:
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Pub Dt:
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03/27/2003
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Title:
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NON-VOLATILE MEMORY ARRAY WITH EQUALIZED BIT LINE POTENTIALS
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Patent #:
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Issue Dt:
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06/24/2003
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Application #:
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09978447
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Filing Dt:
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10/15/2001
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Publication #:
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Pub Dt:
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02/07/2002
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Title:
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METHODS FOR FABRICATING A SEMICONDUCTOR CHIP HAVING CMOS DEVICES AND FIELDLESS ARRAY
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Patent #:
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Issue Dt:
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02/03/2004
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Application #:
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10226487
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Filing Dt:
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08/22/2002
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Publication #:
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Pub Dt:
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01/02/2003
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Title:
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SEMICONDUCTOR CHIP HAVING BOTH POLYCIDE AND SALICIDE GATES AND METHODS FOR MAKING SAME
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Patent #:
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Issue Dt:
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02/01/2005
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Application #:
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10376461
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Filing Dt:
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02/28/2003
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Publication #:
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Pub Dt:
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09/02/2004
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Title:
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SELECTIVE SILICIDATION SCHEME FOR MEMORY DEVICES
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Patent #:
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Issue Dt:
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10/21/2008
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Application #:
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11065312
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Filing Dt:
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02/23/2005
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Publication #:
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Pub Dt:
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06/30/2005
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Title:
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PROTECTION AGAINTS IN-PROCESS CHARGING IN SILICON-OXIDE-NITRIDE-OXIDE-SILICON (SONOS) MEMORIES
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Patent #:
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Issue Dt:
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08/28/2007
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Application #:
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11246046
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Filing Dt:
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10/07/2005
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Publication #:
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Pub Dt:
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04/27/2006
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Title:
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MEMORY CIRCUIT WITH FLEXIBLE BITLINE-RELATED AND/OR WORDLINE-RELATED DEFECT MEMORY CELL SUBSTITUTION
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Patent #:
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Issue Dt:
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10/09/2007
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Application #:
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11304168
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Filing Dt:
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12/13/2005
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Publication #:
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Pub Dt:
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06/15/2006
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Title:
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INTEGRATOR-BASED CURRENT SENSING CIRCUIT FOR READING MEMORY CELLS
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Patent #:
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Issue Dt:
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07/05/2011
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Application #:
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12205668
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Filing Dt:
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09/05/2008
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Publication #:
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Pub Dt:
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03/12/2009
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Title:
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TIMING CONTROL CIRCUIT AND SEMICONDUCTOR STORAGE DEVICE
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Patent #:
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Issue Dt:
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05/24/2011
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Application #:
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12230235
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Filing Dt:
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08/26/2008
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Publication #:
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Pub Dt:
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03/05/2009
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Title:
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SEMICONDUCTOR MEMORY DEVICE HAVING VERTICAL TRANSISTORS
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Patent #:
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Issue Dt:
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02/22/2011
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Application #:
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12232381
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Filing Dt:
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09/16/2008
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Publication #:
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Pub Dt:
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03/19/2009
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Title:
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METHOD OF FORMING SEMICONDUCTOR DEVICE HAVING THREE-DIMENSIONAL CHANNEL STRUCTURE
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Patent #:
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Issue Dt:
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04/05/2011
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Application #:
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12234060
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Filing Dt:
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09/19/2008
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Publication #:
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Pub Dt:
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03/26/2009
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Title:
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SEMICONDUCTOR MEMORY DEVICE HAVING A CAPACITOR STRUCTURE WITH A DESIRED CAPACITANCE AND MANUFACTURING METHOD THEREFOR
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Patent #:
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Issue Dt:
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09/07/2010
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Application #:
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12235663
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Filing Dt:
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09/23/2008
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Publication #:
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Pub Dt:
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03/26/2009
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Title:
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SEMICONDUCTOR DEVICE WITH REDUCED GATE-OVERLAP CAPACITANCE AND METHOD OF FORMING THE SAME
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Patent #:
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Issue Dt:
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04/10/2012
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Application #:
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12238593
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Filing Dt:
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09/26/2008
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Publication #:
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Pub Dt:
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04/02/2009
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Title:
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HIGH AND LOW VOLTAGE VERTICAL CHANNEL TRANSISTORS
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Patent #:
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Issue Dt:
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03/08/2011
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Application #:
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12239048
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Filing Dt:
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09/26/2008
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Publication #:
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Pub Dt:
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04/02/2009
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Title:
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SEMICONDUCTOR DEVICE INCLUDING VERTICAL MOS TRANSISTORS
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Patent #:
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Issue Dt:
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03/13/2012
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Application #:
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12239900
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Filing Dt:
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09/29/2008
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Publication #:
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Pub Dt:
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04/02/2009
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Title:
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ADDRESS LINE WIRING STRUCTURE AND PRINTED WIRING BOARD HAVING SAME
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Patent #:
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Issue Dt:
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05/17/2011
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Application #:
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12246649
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Filing Dt:
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10/07/2008
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Publication #:
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Pub Dt:
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04/09/2009
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Title:
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HOLE PATTERN FORMING METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD
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Patent #:
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Issue Dt:
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04/12/2011
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Application #:
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12255817
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Filing Dt:
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10/22/2008
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Publication #:
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Pub Dt:
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04/23/2009
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Title:
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SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND DATA PROCESSING SYSTEM
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|
|
|
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Patent #:
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|
Issue Dt:
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12/13/2011
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Application #:
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12256541
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Filing Dt:
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10/23/2008
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Publication #:
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Pub Dt:
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04/30/2009
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
|
|
|
|
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Patent #:
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|
Issue Dt:
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08/23/2011
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Application #:
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12258547
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Filing Dt:
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10/27/2008
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Publication #:
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Pub Dt:
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04/30/2009
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
|
|
|
|
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Patent #:
|
|
Issue Dt:
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11/30/2010
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Application #:
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12259527
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Filing Dt:
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10/28/2008
|
|
Publication #:
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|
Pub Dt:
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04/30/2009
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Title:
|
SEMICONDUCTOR DEVICE HAVING MOS TRANSISTORS WHICH ARE SERIALLY CONNECTED VIA CONTACTS AND CONDUCTION LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
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07/06/2010
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Application #:
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12259923
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Filing Dt:
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10/28/2008
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Publication #:
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Pub Dt:
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05/07/2009
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Title:
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VOLTAGE DETECTING CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME
|
|
|
|
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Patent #:
|
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Issue Dt:
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02/01/2011
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Application #:
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12260790
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Filing Dt:
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10/29/2008
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Publication #:
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Pub Dt:
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04/30/2009
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Title:
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SEMICONDUCTOR DEVICE AND REFRESH METHOD
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Patent #:
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Issue Dt:
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03/22/2011
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Application #:
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12260842
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Filing Dt:
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10/29/2008
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Publication #:
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Pub Dt:
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12/03/2009
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Title:
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SEMICONDUCTOR MEMORY DEVICE AND METHOD OF TESTING SEMICONDUCTOR MEMORY DEVICE
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Patent #:
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Issue Dt:
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02/11/2014
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Application #:
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12285089
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Filing Dt:
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09/29/2008
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Publication #:
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Pub Dt:
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04/02/2009
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Title:
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circuit including first and second transistors coupled between an outpout terminal and a power supply
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Patent #:
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Issue Dt:
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11/15/2011
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Application #:
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12285165
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Filing Dt:
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09/30/2008
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Publication #:
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Pub Dt:
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04/16/2009
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Title:
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SEMICONDUCTOR STORAGE DEVICE AND HIGH-SPEED ADDRESS-LATCHING METHOD
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Patent #:
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Issue Dt:
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12/18/2012
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Application #:
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12285222
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Filing Dt:
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09/30/2008
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Publication #:
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Pub Dt:
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04/30/2009
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Title:
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WAFER OF CIRCUIT BOARD AND JOINING STRUCTURE OF WAFER OR CIRCUIT BOARD
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|
|
|
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Patent #:
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Issue Dt:
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05/03/2011
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Application #:
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12285719
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Filing Dt:
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10/14/2008
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Publication #:
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Pub Dt:
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04/16/2009
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Title:
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SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME
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Patent #:
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Issue Dt:
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04/19/2011
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Application #:
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12285832
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Filing Dt:
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10/15/2008
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Publication #:
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Pub Dt:
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04/16/2009
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
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Patent #:
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Issue Dt:
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06/21/2011
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Application #:
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12285928
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Filing Dt:
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10/16/2008
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Publication #:
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Pub Dt:
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04/23/2009
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Title:
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SEMICONDUCTOR MEMORY DEVICE AND METHOD OF PROVIDING PRODUCT FAMILIES OF THE SAME
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Patent #:
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Issue Dt:
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08/03/2010
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Application #:
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12285979
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Filing Dt:
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10/17/2008
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Publication #:
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Pub Dt:
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04/23/2009
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Title:
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SEMICONDUCTOR DEVICE AND DRIVER CONTROL METHOD
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Patent #:
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Issue Dt:
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07/26/2011
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Application #:
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12289002
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Filing Dt:
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10/17/2008
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Publication #:
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Pub Dt:
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04/23/2009
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Title:
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METHOD OF PRODUCING PHASE CHANGE MEMORY DEVICE
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|
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Patent #:
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Issue Dt:
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05/31/2011
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Application #:
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12289196
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Filing Dt:
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10/22/2008
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Publication #:
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Pub Dt:
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04/30/2009
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Title:
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SEMICONDUCTOR DEVICE INCLUDING ANTI-FUSE CIRCUIT, AND METHOD OF WRITING ADDRESS TO ANTI-FUSE CIRCUIT
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|
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Patent #:
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Issue Dt:
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11/08/2011
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Application #:
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12289349
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Filing Dt:
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10/27/2008
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Publication #:
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Pub Dt:
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04/30/2009
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Title:
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SEMICONDUCTOR MEMORY DEVICE HAVING A DOUBLE BRANCHING BIDIRECTIONAL BUFFER
|
|
|
|
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Patent #:
|
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Issue Dt:
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04/26/2011
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Application #:
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12289372
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Filing Dt:
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10/27/2008
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Publication #:
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Pub Dt:
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05/14/2009
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Title:
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TRANSISTOR IN A WIRING INTERLAYER INSULATING FILM
|
|
|
|
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Patent #:
|
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Issue Dt:
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03/01/2011
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Application #:
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12292432
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Filing Dt:
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11/19/2008
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Publication #:
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Pub Dt:
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04/15/2010
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Title:
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SEMICONDUCTOR DEVICE AND TEST METHOD THEREFOR
|
|
|
|
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Patent #:
|
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Issue Dt:
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08/17/2010
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Application #:
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12292664
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Filing Dt:
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11/24/2008
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Publication #:
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Pub Dt:
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06/04/2009
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Title:
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SIGNAL TRANSMISSION CIRCUIT AND CHARACTERISTIC ADJUSTMENT METHOD THEREOF, MEMORY MODULE, AND MANUFACTURING METHOD OF CIRCUIT BOARD
|
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Patent #:
|
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Issue Dt:
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01/25/2011
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Application #:
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12292957
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Filing Dt:
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12/01/2008
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Publication #:
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Pub Dt:
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05/20/2010
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Title:
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DLL CIRCUIT AND SEMICONDUCTOR DEVICE HAVING THE SAME
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Patent #:
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Issue Dt:
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07/12/2011
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Application #:
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12314010
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Filing Dt:
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12/02/2008
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Publication #:
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Pub Dt:
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06/11/2009
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Title:
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SEMICONDUCTOR WAFER INCLUDING CRACKING STOPPER STRUCTURE AND METHOD OF FORMING THE SAME
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Patent #:
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Issue Dt:
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07/06/2010
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Application #:
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12314207
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Filing Dt:
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12/05/2008
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Publication #:
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Pub Dt:
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06/11/2009
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Title:
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TIMING CONTROL CIRCUIT, TIMING GENERATION SYSTEM, TIMING CONTROL METHOD AND SEMICONDUCTOR MEMORY DEVICE
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Patent #:
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Issue Dt:
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06/22/2010
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Application #:
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12314303
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Filing Dt:
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12/08/2008
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Publication #:
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Pub Dt:
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06/11/2009
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Title:
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METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE WITH RECESS GATE TRANSISTOR
|
|
|
|
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Patent #:
|
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Issue Dt:
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12/06/2011
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Application #:
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12314494
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Filing Dt:
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12/11/2008
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Publication #:
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Pub Dt:
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06/25/2009
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Title:
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SEMICONDUCTOR STORAGE DEVICE HAVING REDUNDANCY AREA
|
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Patent #:
|
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Issue Dt:
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03/08/2011
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Application #:
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12314860
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Filing Dt:
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12/17/2008
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Publication #:
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Pub Dt:
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07/16/2009
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Title:
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SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/09/2011
|
Application #:
|
12314895
|
Filing Dt:
|
12/18/2008
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Publication #:
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Pub Dt:
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07/02/2009
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|
Title:
|
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE INCLUDING MOUNTING AND DICING CHIPS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/24/2012
|
Application #:
|
12318417
|
Filing Dt:
|
12/29/2008
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Publication #:
|
|
Pub Dt:
|
05/20/2010
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|
Title:
|
SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/04/2014
|
Application #:
|
12318700
|
Filing Dt:
|
01/06/2009
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Publication #:
|
|
Pub Dt:
|
07/30/2009
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Title:
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SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/12/2011
|
Application #:
|
12318731
|
Filing Dt:
|
01/07/2009
|
|
Publication #:
|
|
Pub Dt:
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07/16/2009
| | | | |
|
Title:
|
SEMICONDUCTOR MEMORY DEVICE AND DATA PROCESSING SYSTEM INCLUDING THE SEMICONDUCTOR MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/07/2012
|
Application #:
|
12318798
|
Filing Dt:
|
01/08/2009
|
|
Publication #:
|
|
Pub Dt:
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08/20/2009
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Title:
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SEMICONDUCTOR DEVICE INCLUDING FIRST SUBSTRATE HAVING PLURALITY OF WIRES AND A PLURALITY OF FIRST ELECTRODES AND A SECOND SUBSTRAE INCLUDING A SEMICONDUCTOR CHIP BEING MOUNTED THEREON, AND SECOND ELECTRODES CONNECTED WITH FIRST ELECTRODES OF FIRST SUBSTRATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/11/2011
|
Application #:
|
12320323
|
Filing Dt:
|
01/23/2009
|
|
Publication #:
|
|
Pub Dt:
|
08/06/2009
| | | | |
|
Title:
|
SEMICONDUCTOR STORAGE DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/02/2011
|
Application #:
|
12320585
|
Filing Dt:
|
01/29/2009
|
|
Publication #:
|
|
Pub Dt:
|
07/30/2009
| | | | |
|
Title:
|
SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/08/2011
|
Application #:
|
12320785
|
Filing Dt:
|
02/04/2009
|
|
Publication #:
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Pub Dt:
|
08/13/2009
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND LAYOUT METHOD THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/14/2012
|
Application #:
|
12320891
|
Filing Dt:
|
02/06/2009
|
|
Publication #:
|
|
Pub Dt:
|
08/13/2009
| | | | |
|
Title:
|
SEMICONDUCTOR MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/10/2011
|
Application #:
|
12320892
|
Filing Dt:
|
02/06/2009
|
|
Publication #:
|
|
Pub Dt:
|
08/13/2009
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|
Title:
|
SEMICONDUCTOR MEMORY DEVICE, CONTROL METHOD THEREFOR, AND METHOD FOR DETERMINING REPAIR POSSIBILITY OF DEFECTIVE ADDRESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/16/2010
|
Application #:
|
12325026
|
Filing Dt:
|
11/28/2008
|
|
Publication #:
|
|
Pub Dt:
|
03/04/2010
| | | | |
|
Title:
|
SEMICONDUCTOR MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/01/2011
|
Application #:
|
12326993
|
Filing Dt:
|
12/03/2008
|
|
Publication #:
|
|
Pub Dt:
|
06/11/2009
| | | | |
|
Title:
|
METHOD OF FORMING SEMICONDUCTOR DEVICE INCLUDING CAPACITOR AND SEMICONDUCTOR DEVICE INCLUDING CAPACITOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/22/2011
|
Application #:
|
12327649
|
Filing Dt:
|
12/03/2008
|
|
Publication #:
|
|
Pub Dt:
|
06/04/2009
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/21/2011
|
Application #:
|
12328129
|
Filing Dt:
|
12/04/2008
|
|
Publication #:
|
|
Pub Dt:
|
06/18/2009
| | | | |
|
Title:
|
SEPARATE TESTING OF CONTINUITY BETWEEN AN INTERNAL TERMINAL IN EACH CHIP AND AN EXTERNAL TERMINAL IN A STACKED SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/09/2010
|
Application #:
|
12331709
|
Filing Dt:
|
12/10/2008
|
|
Publication #:
|
|
Pub Dt:
|
06/18/2009
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/28/2010
|
Application #:
|
12335964
|
Filing Dt:
|
12/16/2008
|
|
Publication #:
|
|
Pub Dt:
|
05/06/2010
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/17/2012
|
Application #:
|
12348132
|
Filing Dt:
|
01/02/2009
|
|
Publication #:
|
|
Pub Dt:
|
07/16/2009
| | | | |
|
Title:
|
WIRING BOARD FOR SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/28/2011
|
Application #:
|
12349809
|
Filing Dt:
|
01/07/2009
|
|
Publication #:
|
|
Pub Dt:
|
07/23/2009
| | | | |
|
Title:
|
MODULE WITH STACKED SEMICONDUCTOR DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2012
|
Application #:
|
12357895
|
Filing Dt:
|
01/22/2009
|
|
Publication #:
|
|
Pub Dt:
|
07/23/2009
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE INCLUDING SEMICONDUCTOR CHIPS WITH DIFFERENT THICKNESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2012
|
Application #:
|
12357992
|
Filing Dt:
|
01/22/2009
|
|
Publication #:
|
|
Pub Dt:
|
07/30/2009
| | | | |
|
Title:
|
BAND-GAP REFERENCE VOLTAGE SOURCE CIRCUIT WITH SWITCHABLE BIAS VOLTAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/19/2011
|
Application #:
|
12360645
|
Filing Dt:
|
01/27/2009
|
|
Publication #:
|
|
Pub Dt:
|
08/06/2009
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/05/2011
|
Application #:
|
12361073
|
Filing Dt:
|
01/28/2009
|
|
Publication #:
|
|
Pub Dt:
|
07/30/2009
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE HAVING A MODE REGISTER AND A PLURALITY OF VOLTAGE GENERATORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/06/2011
|
Application #:
|
12361117
|
Filing Dt:
|
01/28/2009
|
|
Publication #:
|
|
Pub Dt:
|
08/13/2009
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE HAVING MOS-TRANSISTOR FORMED ON SEMICONDUCTOR SUBSTRATE AND METHOD FOR MANUFACTURING THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/13/2013
|
Application #:
|
12362670
|
Filing Dt:
|
01/30/2009
|
|
Publication #:
|
|
Pub Dt:
|
08/06/2009
| | | | |
|
Title:
|
WIRING BOARD FOR SEMICONDUCTOR DEVICES, SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE, AND MOTHERBOARD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/22/2011
|
Application #:
|
12364820
|
Filing Dt:
|
02/03/2009
|
|
Publication #:
|
|
Pub Dt:
|
08/06/2009
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/12/2011
|
Application #:
|
12366219
|
Filing Dt:
|
02/05/2009
|
|
Publication #:
|
|
Pub Dt:
|
08/13/2009
| | | | |
|
Title:
|
EXPOSURE MASK AND PATTERN FORMING METHOD THEREFOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/29/2011
|
Application #:
|
12379825
|
Filing Dt:
|
03/03/2009
|
|
Publication #:
|
|
Pub Dt:
|
09/03/2009
| | | | |
|
Title:
|
PHASE CHANGE MEMORY DEVICE AND FABRICATION METHOD THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/25/2011
|
Application #:
|
12382495
|
Filing Dt:
|
03/17/2009
|
|
Publication #:
|
|
Pub Dt:
|
10/15/2009
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE HAVING SINGLE-ENDED SENSING AMPLIFIER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/23/2011
|
Application #:
|
12382524
|
Filing Dt:
|
03/18/2009
|
|
Publication #:
|
|
Pub Dt:
|
09/24/2009
| | | | |
|
Title:
|
MULTI-PORT MEMORY AND COMPUTER SYSTEM PROVIDED WITH THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/19/2012
|
Application #:
|
12385503
|
Filing Dt:
|
04/09/2009
|
|
Publication #:
|
|
Pub Dt:
|
10/15/2009
| | | | |
|
Title:
|
STANDARD CELL HAVING COMPENSATION CAPACITANCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/15/2011
|
Application #:
|
12385949
|
Filing Dt:
|
04/24/2009
|
|
Publication #:
|
|
Pub Dt:
|
10/29/2009
| | | | |
|
Title:
|
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF PERFORMING DATA REDUCTION TEST
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/01/2011
|
Application #:
|
12385958
|
Filing Dt:
|
04/24/2009
|
|
Publication #:
|
|
Pub Dt:
|
10/29/2009
| | | | |
|
Title:
|
CURRENT SENSING CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/11/2011
|
Application #:
|
12385959
|
Filing Dt:
|
04/24/2009
|
|
Publication #:
|
|
Pub Dt:
|
10/29/2009
| | | | |
|
Title:
|
SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/18/2011
|
Application #:
|
12392547
|
Filing Dt:
|
02/25/2009
|
|
Publication #:
|
|
Pub Dt:
|
08/27/2009
| | | | |
|
Title:
|
STACKED MEMORY AND FUSE CHIP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/22/2011
|
Application #:
|
12396517
|
Filing Dt:
|
03/03/2009
|
|
Publication #:
|
|
Pub Dt:
|
09/10/2009
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/12/2011
|
Application #:
|
12407250
|
Filing Dt:
|
03/19/2009
|
|
Publication #:
|
|
Pub Dt:
|
09/24/2009
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE HAVING SHIELD STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/26/2011
|
Application #:
|
12416432
|
Filing Dt:
|
04/01/2009
|
|
Publication #:
|
|
Pub Dt:
|
10/08/2009
| | | | |
|
Title:
|
SEMICONDUCTOR MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/10/2012
|
Application #:
|
12421049
|
Filing Dt:
|
04/09/2009
|
|
Publication #:
|
|
Pub Dt:
|
10/15/2009
| | | | |
|
Title:
|
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/13/2012
|
Application #:
|
12426488
|
Filing Dt:
|
04/20/2009
|
|
Publication #:
|
|
Pub Dt:
|
10/22/2009
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/10/2011
|
Application #:
|
12426624
|
Filing Dt:
|
04/20/2009
|
|
Publication #:
|
|
Pub Dt:
|
10/29/2009
| | | | |
|
Title:
|
SEMICONDUCTOR MEMORY DEVICE AND TEST METHOD THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/04/2011
|
Application #:
|
12435780
|
Filing Dt:
|
05/05/2009
|
|
Publication #:
|
|
Pub Dt:
|
11/19/2009
| | | | |
|
Title:
|
POWER SUPPLY VOLTAGE DROPPING CIRCUIT USING AN N-CHANNEL TRANSISTOR OUTPUT STAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/06/2011
|
Application #:
|
12436285
|
Filing Dt:
|
05/06/2009
|
|
Publication #:
|
|
Pub Dt:
|
11/19/2009
| | | | |
|
Title:
|
SEMICONDUCTOR MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/18/2011
|
Application #:
|
12453730
|
Filing Dt:
|
05/20/2009
|
|
Publication #:
|
|
Pub Dt:
|
11/26/2009
| | | | |
|
Title:
|
CALIBRATION CIRCUIT
|
|
