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Reel/Frame:047039/0957   Pages: 8
Recorded: 10/02/2018
Attorney Dkt #:GLOBALFOUNDRIES-US
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 21
1
Patent #:
6346470
Issue Dt:
02/12/2002
Application #:
09294454
Filing Dt:
04/19/1999
Title:
METHOD FOR REDUCING ELECTROMIGRATION IN SEMICONDUCTOR INTERCONNECT LINES
2
Patent #:
6121150
Issue Dt:
09/19/2000
Application #:
09296557
Filing Dt:
04/22/1999
Title:
SPUTTER-RESISTANT HARDMASK FOR DAMASCENE TRENCH/VIA FORMATION
3
Patent #:
6689689
Issue Dt:
02/10/2004
Application #:
09477821
Filing Dt:
01/05/2000
Title:
SELECTIVE DEPOSITION PROCESS FOR ALLOYING DAMASCENE-TYPE CU INTERCONNECT LINES
4
Patent #:
6455425
Issue Dt:
09/24/2002
Application #:
09484412
Filing Dt:
01/18/2000
Publication #:
US20020027261
Pub Dt:
03/07/2002
Title:
SELECTIVE DEPOSITION PROCESS FOR PASSIVATING TOP INTERFACE OF DAMASCENE-TYPE CU INTERCONNECT LINES
5
Patent #:
6563222
Issue Dt:
05/13/2003
Application #:
09999703
Filing Dt:
10/24/2001
Title:
METHOD AND APPARATUS FOR REDUCING ELECTROMIGRATION IN SEMICONDUCTOR INTERCONNECT LINES
6
Patent #:
6835618
Issue Dt:
12/28/2004
Application #:
10633499
Filing Dt:
08/05/2003
Title:
EPITAXIALLY GROWN FIN FOR FINFET
7
Patent #:
7183152
Issue Dt:
02/27/2007
Application #:
10975475
Filing Dt:
10/29/2004
Title:
EPITAXIALLY GROWN FIN FOR FINFET
8
Patent #:
7413985
Issue Dt:
08/19/2008
Application #:
11853994
Filing Dt:
09/12/2007
Publication #:
US20080132064
Pub Dt:
06/05/2008
Title:
METHOD FOR FORMING A SELF-ALIGNED NITROGEN-CONTAINING COPPER SILICIDE CAPPING LAYER IN A MICROSTRUCTURE DEVICE
9
Patent #:
7829466
Issue Dt:
11/09/2010
Application #:
12365300
Filing Dt:
02/04/2009
Publication #:
US20100197096
Pub Dt:
08/05/2010
Title:
METHODS FOR FABRICATING FINFET STRUCTURES HAVING DIFFERENT CHANNEL LENGTHS
10
Patent #:
8198192
Issue Dt:
06/12/2012
Application #:
12775555
Filing Dt:
05/07/2010
Publication #:
US20100289089
Pub Dt:
11/18/2010
Title:
ADJUSTING THRESHOLD VOLTAGE FOR SOPHISTICATED TRANSISTORS BY DIFFUSING A GATE DIELECTRIC CAP LAYER MATERIAL PRIOR TO GATE DIELECTRIC STABILIZATION
11
Patent #:
7960287
Issue Dt:
06/14/2011
Application #:
12891365
Filing Dt:
09/27/2010
Publication #:
US20110014791
Pub Dt:
01/20/2011
Title:
METHODS FOR FABRICATING FINFET STRUCTURES HAVING DIFFERENT CHANNEL LENGTHS
12
Patent #:
8222103
Issue Dt:
07/17/2012
Application #:
13027739
Filing Dt:
02/15/2011
Title:
SEMICONDUCTOR DEVICE WITH EMBEDDED LOW-K METALLIZATION
13
Patent #:
8664113
Issue Dt:
03/04/2014
Application #:
13096898
Filing Dt:
04/28/2011
Publication #:
US20120273958
Pub Dt:
11/01/2012
Title:
MULTILAYER INTERCONNECT STRUCTURE AND METHOD FOR INTEGRATED CIRCUITS
14
Patent #:
8461008
Issue Dt:
06/11/2013
Application #:
13210086
Filing Dt:
08/15/2011
Publication #:
US20130045580
Pub Dt:
02/21/2013
Title:
METHODS FOR FABRICATING FINFET INTEGRATED CIRCUITS IN BULK SEMICONDUCTOR SUBSTRATES
15
Patent #:
8431482
Issue Dt:
04/30/2013
Application #:
13362981
Filing Dt:
01/31/2012
Title:
INTEGRATED CIRCUITS AND METHODS FOR PROCESSING INTEGRATED CIRCUITS WITH EMBEDDED FEATURES
16
Patent #:
8525289
Issue Dt:
09/03/2013
Application #:
13444955
Filing Dt:
04/12/2012
Publication #:
US20120193727
Pub Dt:
08/02/2012
Title:
ADJUSTING THRESHOLD VOLTAGE FOR SOPHISTICATED TRANSISTORS BY DIFFUSING A GATE DIELECTRIC CAP LAYER MATERIAL PRIOR TO GATE DIELECTRIC STABILIZATION
17
Patent #:
9023715
Issue Dt:
05/05/2015
Application #:
13454520
Filing Dt:
04/24/2012
Publication #:
US20130280883
Pub Dt:
10/24/2013
Title:
METHODS OF FORMING BULK FINFET DEVICES SO AS TO REDUCE PUNCH THROUGH LEAKAGE CURRENTS
18
Patent #:
8969932
Issue Dt:
03/03/2015
Application #:
13711779
Filing Dt:
12/12/2012
Publication #:
US20140159126
Pub Dt:
06/12/2014
Title:
METHODS OF FORMING A FINFET SEMICONDUCTOR DEVICE WITH UNDOPED FINS
19
Patent #:
8704372
Issue Dt:
04/22/2014
Application #:
13849415
Filing Dt:
03/22/2013
Publication #:
US20130241062
Pub Dt:
09/19/2013
Title:
INTEGRATED CIRCUITS AND METHODS FOR PROCESSING INTEGRATED CIRCUITS WITH EMBEDDED FEATURES
20
Patent #:
8796859
Issue Dt:
08/05/2014
Application #:
13953125
Filing Dt:
07/29/2013
Publication #:
US20130313725
Pub Dt:
11/28/2013
Title:
MULTILAYER INTERCONNECT STRUCTURE AND METHOD FOR INTEGRATED CIRCUITS
21
Patent #:
9105507
Issue Dt:
08/11/2015
Application #:
14595924
Filing Dt:
01/13/2015
Publication #:
US20150123214
Pub Dt:
05/07/2015
Title:
METHODS OF FORMING A FINFET SEMICONDUCTOR DEVICE WITH UNDOPED FINS
Assignor
1
GLOBALFOUNDRIES INC.
Exec Dt:
09/25/2018
Assignee
1
TESSERA ADVANCED TECHNOLOGIES, INC.
3025 ORCHARD PARKWAY
SAN JOSE, CALIFORNIA 95134
Correspondence name and address
TESSERA INTELLECTUAL PROPERTIES CORP. C/
3025 ORCHARD PARKWAY
SAN JOSE, CA 95134

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