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Patent #:
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06/16/2009
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Application #:
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11486819
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Filing Dt:
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07/14/2006
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Publication #:
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Pub Dt:
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11/16/2006
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Title:
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SEMICONDUCTOR DEVICE INCLUDING CONTAINER HAVING EPITAXIAL SILICON THEREIN
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Patent #:
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12/25/2007
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Application #:
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11486872
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Filing Dt:
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07/14/2006
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Publication #:
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Pub Dt:
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11/16/2006
| | | | |
Title:
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METHOD OF RESETTING PHASE CHANGE MEMORY BITS THROUGH A SERIES OF PULSES OF INCREASING AMPLITUDE
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Patent #:
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Issue Dt:
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07/08/2008
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Application #:
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11487080
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Filing Dt:
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07/14/2006
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Publication #:
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Pub Dt:
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11/16/2006
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Title:
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METHODS FOR FORMING AN ENRICHED METAL OXIDE SURFACE
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Patent #:
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Issue Dt:
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04/13/2010
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11487209
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Filing Dt:
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07/14/2006
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Publication #:
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Pub Dt:
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01/17/2008
| | | | |
Title:
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BOTTOM ELECTRODE CONTACTS FOR SEMICONDUCTOR DEVICES AND METHODS OF FORMING SAME
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Patent #:
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Issue Dt:
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02/05/2013
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Application #:
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11487246
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Filing Dt:
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07/14/2006
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Publication #:
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Pub Dt:
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01/17/2008
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Title:
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SEMICONDUCTOR DEVICE FABRICATION AND DRY DEVELOP PROCESS SUITABLE FOR CRITICAL DIMENSION TUNABILITY AND PROFILE CONTROL
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Patent #:
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Issue Dt:
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03/30/2010
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Application #:
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11487403
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Filing Dt:
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07/17/2006
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Publication #:
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Pub Dt:
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11/16/2006
| | | | |
Title:
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METHODS OF ELIMINATING PATTERN COLLAPSE ON PHOTORESIST PATTERNS
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Patent #:
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02/26/2008
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Application #:
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11487857
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Filing Dt:
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07/17/2006
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Publication #:
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Pub Dt:
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11/16/2006
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Title:
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HANDLING DEFECTIVE MEMORY BLOCKS OF NAND MEMORY DEVICES
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Patent #:
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10/13/2009
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11488384
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Filing Dt:
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07/17/2006
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Publication #:
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Pub Dt:
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01/17/2008
| | | | |
Title:
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CAPACITORLESS ONE TRANSISTOR DRAM CELL, INTEGRATED CIRCUITRY COMPRISING AN ARRAY OF CAPACITORLESS ONE TRANSISTOR DRAM CELLS, AND METHOD OF FORMING LINES OF CAPACITORLESS ONE TRANSISTOR DRAM CELLS
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Patent #:
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11/06/2007
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11488579
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07/17/2006
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Publication #:
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Pub Dt:
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11/16/2006
| | | | |
Title:
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METHODS OF FORMING A REACTION PRODUCT AND METHODS OF FORMING A CONDUCTIVE METAL SILICIDE BY REACTION OF METAL WITH SILICON
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Patent #:
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12/22/2009
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11488587
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Filing Dt:
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07/17/2006
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Pub Dt:
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01/17/2008
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Title:
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METHODS OF FORMING CAPACITORS
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Patent #:
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04/13/2010
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11488934
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07/17/2006
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Publication #:
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Pub Dt:
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11/23/2006
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Title:
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NUCLEATION METHOD FOR ATOMIC LAYER DEPOSITION OF COBALT ON BARE SILICON DURING THE FORMATION OF A SEMICONDUCTOR DEVICE
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03/04/2008
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11488962
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07/19/2006
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11/23/2006
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Title:
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VERTICAL NROM NAND FLASH MEMORY ARRAY
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Patent #:
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02/26/2008
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11489119
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Filing Dt:
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07/19/2006
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Publication #:
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Pub Dt:
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11/16/2006
| | | | |
Title:
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APPARATUS AND METHOD TO REDUCE UNDESIRABLE EFFECTS CAUSED BY A FAULT IN A MEMORY DEVICE
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Patent #:
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06/09/2009
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Application #:
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11489321
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Filing Dt:
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07/19/2006
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Publication #:
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Pub Dt:
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11/16/2006
| | | | |
Title:
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ERASE BLOCK DATA SPLITTING
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Patent #:
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Issue Dt:
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01/05/2010
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Application #:
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11489778
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Filing Dt:
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07/20/2006
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Publication #:
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Pub Dt:
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11/16/2006
| | | | |
Title:
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MEMORY DEVICE CONTROLLER
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Patent #:
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Issue Dt:
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08/21/2007
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Application #:
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11489880
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Filing Dt:
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07/20/2006
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Publication #:
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Pub Dt:
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11/16/2006
| | | | |
Title:
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ONE-TRANSISTOR COMPOSITE-GATE MEMORY
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Patent #:
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Issue Dt:
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09/08/2009
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Application #:
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11489904
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Filing Dt:
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07/20/2006
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Publication #:
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Pub Dt:
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11/16/2006
| | | | |
Title:
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MEMORY DEVICE CONTROLLER
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Patent #:
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Issue Dt:
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09/15/2009
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Application #:
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11490073
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Filing Dt:
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07/21/2006
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Publication #:
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Pub Dt:
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01/25/2007
| | | | |
Title:
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SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING THE SAME
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Patent #:
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04/28/2009
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11490214
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Filing Dt:
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07/20/2006
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Pub Dt:
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02/22/2007
| | | | |
Title:
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CURRENT DIFFERENTIAL BUFFER
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Patent #:
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01/27/2009
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11490294
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Filing Dt:
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07/20/2006
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Publication #:
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Pub Dt:
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11/16/2006
| | | | |
Title:
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DRAM CELLS WITH VERTICAL TRANSISTORS
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Patent #:
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Issue Dt:
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10/13/2009
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11490619
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07/21/2006
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Publication #:
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Pub Dt:
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11/16/2006
| | | | |
Title:
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MEMORY ARRAY BURIED DIGIT LINE
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Patent #:
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07/07/2009
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11490681
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Filing Dt:
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07/21/2006
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Publication #:
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Pub Dt:
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11/16/2006
| | | | |
Title:
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METHODS OF FORMING FIELD EFFECT TRANSISTORS
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Patent #:
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Issue Dt:
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04/15/2008
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Application #:
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11490712
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Filing Dt:
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07/20/2006
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Publication #:
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Pub Dt:
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11/16/2006
| | | | |
Title:
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METHOD OF FORMING A FIELD EFFECT TRANSISTOR INCLUDING DEPOSITING AND REMOVING INSULATIVE MATERIAL EFFECTIVE TO EXPOSE TRANSISTOR GATE CONDUCTIVE MATERIAL BUT NOT TRANSISTOR GATE SEMICONDUCTIVE MATERIAL
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Patent #:
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NONE
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11490767
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Filing Dt:
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07/21/2006
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Publication #:
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Pub Dt:
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11/23/2006
| | | | |
Title:
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Single-ended pseudo-differential output driver
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Patent #:
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Issue Dt:
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04/21/2009
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11491066
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Filing Dt:
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07/21/2006
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Publication #:
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Pub Dt:
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11/16/2006
| | | | |
Title:
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VERTICAL TRANSISTORS
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Patent #:
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Issue Dt:
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07/15/2008
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Application #:
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11491331
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Filing Dt:
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07/21/2006
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Publication #:
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Pub Dt:
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11/16/2006
| | | | |
Title:
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PROGRAM FAILURE RECOVERY
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Patent #:
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Issue Dt:
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11/23/2010
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11491383
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Filing Dt:
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07/20/2006
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Publication #:
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Pub Dt:
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11/16/2006
| | | | |
Title:
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ATOMIC LAYER DEPOSITION METHOD OF DEPOSITING AN OXIDE ON A SUBSTRATE
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Patent #:
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Issue Dt:
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05/06/2008
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Application #:
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11491461
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Filing Dt:
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07/21/2006
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Publication #:
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Pub Dt:
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11/16/2006
| | | | |
Title:
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MEMORY ARRAY BURIED DIGIT LINE
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Patent #:
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Issue Dt:
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10/27/2009
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11491640
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Filing Dt:
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07/24/2006
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Publication #:
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Pub Dt:
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07/19/2007
| | | | |
Title:
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MEMORY WITH TEST MODE OUTPUT
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Patent #:
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Issue Dt:
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06/23/2015
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Application #:
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11492138
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Filing Dt:
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07/24/2006
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Publication #:
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Pub Dt:
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11/16/2006
| | | | |
Title:
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Method and apparatus for fabricating a memory device with a dielectric etch stop layer
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Patent #:
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Issue Dt:
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01/18/2011
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Application #:
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11492250
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Filing Dt:
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07/25/2006
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Publication #:
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Pub Dt:
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07/19/2007
| | | | |
Title:
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CIRCUITS AND METHODS FOR REPAIRING DEFECTS IN MEMORY DEVICES
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Patent #:
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Issue Dt:
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02/24/2009
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11492251
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Filing Dt:
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07/25/2006
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Publication #:
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Pub Dt:
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11/23/2006
| | | | |
Title:
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MEMORY UTILIZING OXIDE-NITRIDE NANOLAMINATES
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Patent #:
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Issue Dt:
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11/16/2010
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Application #:
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11492254
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Filing Dt:
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07/25/2006
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Publication #:
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Pub Dt:
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07/19/2007
| | | | |
Title:
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CIRCUITS AND METHODS FOR REPAIRING DEFECTS IN MEMORY DEVICES
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Patent #:
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NONE
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Application #:
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11492272
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Filing Dt:
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07/25/2006
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Publication #:
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Pub Dt:
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11/23/2006
| | | | |
Title:
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Memory block erasing in a flash memory device
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Patent #:
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Issue Dt:
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01/05/2010
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Application #:
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11492342
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Filing Dt:
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07/25/2006
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Publication #:
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Pub Dt:
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02/07/2008
| | | | |
Title:
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MULTI-LAYER STRUCTURES FOR PARAMETER MEASUREMENT
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Patent #:
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Issue Dt:
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08/19/2008
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11492479
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Filing Dt:
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07/25/2006
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Publication #:
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Pub Dt:
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11/23/2006
| | | | |
Title:
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DIE-WAFER PACKAGE AND METHOD OF FABRICATING SAME
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Patent #:
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Issue Dt:
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04/07/2009
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11492596
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Filing Dt:
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07/25/2006
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Publication #:
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Pub Dt:
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11/23/2006
| | | | |
Title:
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MEMORY BLOCK ERASING IN A FLASH MEMORY DEVICE
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Patent #:
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Issue Dt:
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11/16/2010
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Application #:
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11492620
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Filing Dt:
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07/25/2006
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Publication #:
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Pub Dt:
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11/23/2006
| | | | |
Title:
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RECESSED GATE DIELECTRIC ANTIFUSE
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Patent #:
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Issue Dt:
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11/20/2007
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Application #:
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11492650
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Filing Dt:
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07/25/2006
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Publication #:
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Pub Dt:
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11/16/2006
| | | | |
Title:
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PLATING BUSS AND A METHOD OF USE THEREOF
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Patent #:
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Issue Dt:
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11/09/2010
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Application #:
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11492655
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Filing Dt:
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07/25/2006
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Publication #:
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Pub Dt:
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03/01/2007
| | | | |
Title:
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HIGH PERMEABILITY LAYERED FILMS TO REDUCE NOISE IN HIGH SPEED INTERCONNECTS
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Patent #:
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Issue Dt:
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02/10/2009
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Application #:
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11492749
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Filing Dt:
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07/25/2006
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Publication #:
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Pub Dt:
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11/16/2006
| | | | |
Title:
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MEMORY UTILIZING OXIDE-NITRIDE NANOLAMINATES
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Patent #:
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Issue Dt:
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11/09/2010
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Application #:
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11492764
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Filing Dt:
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07/26/2006
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Publication #:
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Pub Dt:
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11/30/2006
| | | | |
Title:
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TAPED SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE
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Patent #:
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Issue Dt:
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05/27/2008
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Application #:
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11492765
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Filing Dt:
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07/26/2006
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Publication #:
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Pub Dt:
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01/31/2008
| | | | |
Title:
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METHOD AND APPARATUS FOR CHARGING LARGE CAPACITANCES
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Patent #:
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Issue Dt:
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06/29/2010
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Application #:
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11492823
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Filing Dt:
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07/26/2006
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Publication #:
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Pub Dt:
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02/01/2007
| | | | |
Title:
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METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND THE SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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11/02/2010
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Application #:
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11493053
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Filing Dt:
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07/26/2006
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Publication #:
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Pub Dt:
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11/23/2006
| | | | |
Title:
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METHOD TO ADDRESS CARBON INCORPORATION IN AN INTERPOLY OXIDE
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Patent #:
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Issue Dt:
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06/01/2010
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Application #:
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11493112
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Filing Dt:
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07/26/2006
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Publication #:
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Pub Dt:
|
11/23/2006
| | | | |
Title:
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ZIRCONIUM-DOPED TANTALUM OXIDE FILMS
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Patent #:
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Issue Dt:
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09/08/2009
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Application #:
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11493113
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Filing Dt:
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07/26/2006
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Publication #:
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Pub Dt:
|
11/23/2006
| | | | |
Title:
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CAPACITIVELY-COUPLED LEVEL RESTORE CIRCUITS FOR LOW VOLTAGE SWING LOGIC CIRCUITS
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Patent #:
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Issue Dt:
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12/04/2007
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Application #:
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11493127
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Filing Dt:
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07/26/2006
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Publication #:
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Pub Dt:
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11/23/2006
| | | | |
Title:
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COMMAND SEQUENCE FOR OPTIMIZED POWER CONSUMPTION
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Patent #:
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Issue Dt:
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03/17/2009
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Application #:
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11493128
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Filing Dt:
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07/26/2006
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Publication #:
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Pub Dt:
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11/23/2006
| | | | |
Title:
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SEMICONDUCTORS BONDED ON GLASS SUBSTRATES
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Patent #:
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Issue Dt:
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03/18/2008
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Application #:
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11493199
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Filing Dt:
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07/26/2006
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Publication #:
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Pub Dt:
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02/14/2008
| | | | |
Title:
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PUBLIC KEY CRYPTOGRAPHY USING MATRICES
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Patent #:
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Issue Dt:
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02/17/2009
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Application #:
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11493335
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Filing Dt:
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07/26/2006
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Publication #:
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Pub Dt:
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12/28/2006
| | | | |
Title:
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TECHNIQUES TO CREATE LOW K ILD FORMING VOIDS BETWEEN METAL LINES
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Patent #:
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Issue Dt:
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10/02/2007
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Application #:
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11493872
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Filing Dt:
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07/26/2006
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Publication #:
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Pub Dt:
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11/23/2006
| | | | |
Title:
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DELAY CIRCUIT WITH RESET-BASED FORWARD PATH STATIC DELAY
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Patent #:
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Issue Dt:
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10/28/2008
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Application #:
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11493960
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Filing Dt:
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07/27/2006
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Publication #:
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Pub Dt:
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11/23/2006
| | | | |
Title:
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SWITCHED CAPACITOR DRAM SENSE AMPLIFIER WITH IMMUNITY TO MISMATCH AND OFFSETS
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Patent #:
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Issue Dt:
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10/28/2008
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Application #:
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11493961
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Filing Dt:
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07/27/2006
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Publication #:
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Pub Dt:
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11/23/2006
| | | | |
Title:
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SWTICHED CAPACITOR DRAM SENSE AMPLIFIER WITH IMMUNITY TO MISMATCH AND OFFSETS
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Patent #:
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Issue Dt:
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04/10/2007
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Application #:
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11493966
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Filing Dt:
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07/27/2006
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Publication #:
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Pub Dt:
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11/23/2006
| | | | |
Title:
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CMOS AMPLIFIERS WITH FREQUENCY COMPENSATING CAPACITORS
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Patent #:
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Issue Dt:
|
11/10/2015
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Application #:
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11493967
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Filing Dt:
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07/27/2006
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Publication #:
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Pub Dt:
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11/23/2006
| | | | |
Title:
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SYSTEMS AND METHODS FOR FORMING ZIRCONIUM AND/OR HAFNIUM-CONTAINING LAYERS
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Patent #:
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Issue Dt:
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08/26/2008
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Application #:
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11494027
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Filing Dt:
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07/27/2006
|
Publication #:
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Pub Dt:
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12/28/2006
| | | | |
Title:
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CMOS AMPLIFIERS WITH FREQUENCY COMPENSATING CAPACITORS
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Patent #:
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Issue Dt:
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06/23/2009
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Application #:
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11494038
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Filing Dt:
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07/27/2006
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Publication #:
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Pub Dt:
|
11/23/2006
| | | | |
Title:
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METHODS OF TESTING MEMORY DEVICES
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Patent #:
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Issue Dt:
|
05/06/2008
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Application #:
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11494319
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Filing Dt:
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07/27/2006
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Publication #:
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Pub Dt:
|
11/30/2006
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Title:
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STRAINED SI/SIGE/SOI ISLANDS AND PROCESSES OF MAKING SAME
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Patent #:
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Issue Dt:
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09/18/2007
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Application #:
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11494356
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Filing Dt:
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07/26/2006
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Publication #:
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Pub Dt:
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11/23/2006
| | | | |
Title:
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LOW VOLTAGE CMOS DIFFERENTIAL AMPLIFIER
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Patent #:
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Issue Dt:
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08/19/2008
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Application #:
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11494420
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Filing Dt:
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07/27/2006
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Publication #:
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Pub Dt:
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11/23/2006
| | | | |
Title:
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SILICON PILLARS FOR VERTICAL TRANSISTORS
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Patent #:
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Issue Dt:
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03/10/2009
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Application #:
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11494432
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Filing Dt:
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07/27/2006
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Publication #:
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Pub Dt:
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01/31/2008
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Title:
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PORTABLE ELECTRONIC DEVICE WITH BUILT-IN TERMINAL COVER STRUCTURE
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Patent #:
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Issue Dt:
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10/04/2011
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Application #:
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11494808
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Filing Dt:
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07/28/2006
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Publication #:
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Pub Dt:
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02/08/2007
| | | | |
Title:
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POWER SINK FOR IC TEMPERATURE CONTROL
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Patent #:
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Issue Dt:
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03/16/2010
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Application #:
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11494844
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Filing Dt:
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07/28/2006
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Publication #:
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Pub Dt:
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11/23/2006
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Title:
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METHOD TO CHEMICALLY REMOVE METAL IMPURITIES FROM POLYCIDE GATE SIDEWALLS
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Patent #:
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Issue Dt:
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08/19/2008
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Application #:
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11494982
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Filing Dt:
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07/28/2006
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Publication #:
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Pub Dt:
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11/23/2006
| | | | |
Title:
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METHODS FOR FORMING VIAS IN MICROELECTRONIC DEVICES, AND METHODS FOR PACKAGING MICROELECTRONIC DEVICES
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Patent #:
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Issue Dt:
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12/18/2007
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Application #:
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11495233
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Filing Dt:
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07/28/2006
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Publication #:
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Pub Dt:
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11/30/2006
| | | | |
Title:
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METHOD, APPARATUS, AND SYSTEM FOR LOW VOLTAGE TEMPERATURE SENSING
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Patent #:
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Issue Dt:
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09/16/2008
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Application #:
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11495245
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Filing Dt:
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07/28/2006
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Publication #:
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Pub Dt:
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11/23/2006
| | | | |
Title:
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NAND FLASH CELL STRUCTURE
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Patent #:
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Issue Dt:
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06/16/2009
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Application #:
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11495418
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Filing Dt:
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07/28/2006
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Publication #:
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Pub Dt:
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11/23/2006
| | | | |
Title:
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DUAL EDGE COMMAND
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Patent #:
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Issue Dt:
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04/28/2009
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Application #:
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11495438
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Filing Dt:
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07/28/2006
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Publication #:
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Pub Dt:
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12/07/2006
| | | | |
Title:
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PROCESS OF FORMING A SEMICONDUCTOR ASSEMBLY HAVING A CONTACT STRUCTURE AND CONTACT LINER
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Patent #:
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Issue Dt:
|
02/10/2009
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Application #:
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11495473
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Filing Dt:
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07/28/2006
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Publication #:
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Pub Dt:
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01/25/2007
| | | | |
Title:
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METHOD OF MAKING VERTICAL TRANSISTOR STRUCTURES HAVING VERTICAL-SURROUNDING-GATES WITH SELF-ALIGNED FEATURES
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Patent #:
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Issue Dt:
|
01/12/2016
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Application #:
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11495499
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Filing Dt:
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07/28/2006
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Publication #:
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Pub Dt:
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11/23/2006
| | | | |
Title:
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METHOD AND APPARATUS FOR FABRICATING A MEMORY DEVICE WITH A DIELECTRIC ETCH STOP LAYER
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|
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Patent #:
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Issue Dt:
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12/01/2009
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Application #:
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11495507
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Filing Dt:
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07/28/2006
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Publication #:
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Pub Dt:
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01/31/2008
| | | | |
Title:
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NAND FLASH MEMORY PROGRAMMING
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Patent #:
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Issue Dt:
|
10/13/2009
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Application #:
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11495550
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Filing Dt:
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07/31/2006
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Publication #:
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Pub Dt:
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02/15/2007
| | | | |
Title:
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SEMICONDUCTOR DEVICE HAVING A SENSE AMPLIFIER ARRAY WITH ADJACENT ECC
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Patent #:
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Issue Dt:
|
07/20/2010
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Application #:
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11495654
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Filing Dt:
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07/28/2006
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Publication #:
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Pub Dt:
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11/23/2006
| | | | |
Title:
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DUAL WORK FUNCTION METAL GATES AND METHODS OF FORMING
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Patent #:
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Issue Dt:
|
10/14/2014
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Application #:
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11495805
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Filing Dt:
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07/28/2006
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Publication #:
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Pub Dt:
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11/15/2007
| | | | |
Title:
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RECESSED ANTIFUSE STRUCTURES AND METHODS OF MAKING THE SAME
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Patent #:
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Issue Dt:
|
05/20/2008
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Application #:
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11495848
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Filing Dt:
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07/28/2006
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Publication #:
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Pub Dt:
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11/23/2006
| | | | |
Title:
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METHOD AND APPARATUS FOR TIMING DOMAIN CROSSING
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|
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Patent #:
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Issue Dt:
|
11/18/2008
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Application #:
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11495866
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Filing Dt:
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07/27/2006
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Publication #:
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Pub Dt:
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11/23/2006
| | | | |
Title:
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DIGITAL DATA APPARATUSES AND DIGITAL DATA OPERATIONAL METHODS
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|
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Patent #:
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Issue Dt:
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02/09/2010
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Application #:
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11495869
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Filing Dt:
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07/28/2006
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Publication #:
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Pub Dt:
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11/23/2006
| | | | |
Title:
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METHOD AND APPARATUS FOR FABRICATING A MEMORY DEVICE WITH A DIELECTRIC ETCH STOP LAYER
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|
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Patent #:
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Issue Dt:
|
04/22/2008
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Application #:
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11495886
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Filing Dt:
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07/28/2006
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Publication #:
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Pub Dt:
|
02/08/2007
| | | | |
Title:
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NAND FLASH MEMORY WITH ERASE VERIFY BASED ON SHORTER EVALUATION TIME
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|
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Patent #:
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Issue Dt:
|
05/08/2007
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Application #:
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11496169
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Filing Dt:
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07/31/2006
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Publication #:
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Pub Dt:
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11/23/2006
| | | | |
Title:
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CONTROLLING MULTIPLE SIGNAL POLARITY IN A SEMICONDUCTOR DEVICE
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|
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Patent #:
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Issue Dt:
|
08/17/2010
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Application #:
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11496180
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Filing Dt:
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07/31/2006
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Publication #:
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Pub Dt:
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12/07/2006
| | | | |
Title:
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SEMICONDUCTOR COMPONENTS AND METHODS OF FABRICATION WITH CIRCUIT SIDE CONTACTS, CONDUCTIVE VIAS AND BACKSIDE CONDUCTORS
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|
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Patent #:
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|
Issue Dt:
|
03/30/2010
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Application #:
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11496196
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Filing Dt:
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07/31/2006
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Publication #:
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Pub Dt:
|
09/03/2009
| | | | |
Title:
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MEMORY UTILIZING OXIDE-CONDUCTOR NANOLAMINATES
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|
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Patent #:
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Issue Dt:
|
12/11/2007
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Application #:
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11496210
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Filing Dt:
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07/31/2006
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Publication #:
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Pub Dt:
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11/30/2006
| | | | |
Title:
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SOLDERMASK OPENING TO PREVENT DELAMINATION
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|
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Patent #:
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|
Issue Dt:
|
04/13/2010
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Application #:
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11496302
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Filing Dt:
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07/31/2006
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Publication #:
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Pub Dt:
|
11/23/2006
| | | | |
Title:
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METHOD AND APPARATUS FOR ADDRESS FIFO FOR HIGH-BANDWIDTH COMMAND/ADDRESS BUSSES IN DIGITAL STORAGE SYSTEM
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|
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Patent #:
|
|
Issue Dt:
|
02/17/2009
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Application #:
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11496342
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Filing Dt:
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07/31/2006
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Publication #:
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Pub Dt:
|
11/30/2006
| | | | |
Title:
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VERTICAL TRANSISTOR WITH HORIZONTAL GATE LAYERS
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|
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Patent #:
|
|
Issue Dt:
|
03/18/2008
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Application #:
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11496605
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Filing Dt:
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07/31/2006
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Publication #:
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Pub Dt:
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11/30/2006
| | | | |
Title:
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DOUBLE SIDED CONTAINER PROCESS USED DURING THE MANUFACTURE OF A SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
|
08/25/2009
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Application #:
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11496655
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Filing Dt:
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07/31/2006
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Publication #:
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Pub Dt:
|
11/23/2006
| | | | |
Title:
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METHOD OF MAKING VERTICAL TRANSISTOR WITH HORIZONTAL GATE LAYERS
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|
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Patent #:
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Issue Dt:
|
03/10/2009
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Application #:
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11496930
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Filing Dt:
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07/31/2006
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Publication #:
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Pub Dt:
|
11/23/2006
| | | | |
Title:
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METHODS OF FORMING SEMICONDUCTOR CONSTRUCTIONS
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|
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Patent #:
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Issue Dt:
|
08/26/2008
|
Application #:
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11497126
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Filing Dt:
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08/01/2006
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Publication #:
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Pub Dt:
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11/23/2006
| | | | |
Title:
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METHODS OF REDUCING COUPLING NOISE BETWEEN WORDLINES
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|
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Patent #:
|
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Issue Dt:
|
02/19/2008
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Application #:
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11497136
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Filing Dt:
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08/01/2006
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Publication #:
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Pub Dt:
|
11/23/2006
| | | | |
Title:
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VERTICAL DEVICE 4F¿ EEPROM MEMORY
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|
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Patent #:
|
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Issue Dt:
|
12/02/2008
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Application #:
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11497176
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Filing Dt:
|
08/01/2006
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Publication #:
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Pub Dt:
|
12/07/2006
| | | | |
Title:
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MEMORY DEVICES HAVING REDUCED COUPLING NOISE BETWEEN WORDLINES
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|
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Patent #:
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Issue Dt:
|
10/21/2008
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Application #:
|
11497598
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Filing Dt:
|
07/31/2006
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Publication #:
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|
Pub Dt:
|
11/23/2006
| | | | |
Title:
|
METHOD OF FORMING INTEGRATED CIRCUITRY
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|
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Patent #:
|
|
Issue Dt:
|
02/03/2009
|
Application #:
|
11497632
|
Filing Dt:
|
08/02/2006
|
Publication #:
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|
Pub Dt:
|
02/07/2008
| | | | |
Title:
|
STRAINED SEMICONDUCTOR, DEVICES AND SYSTEMS AND METHODS OF FORMATION
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|
|
Patent #:
|
|
Issue Dt:
|
11/24/2009
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Application #:
|
11497665
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Filing Dt:
|
08/01/2006
|
Publication #:
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Pub Dt:
|
11/30/2006
| | | | |
Title:
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ISOLATION TRENCH
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|
|
Patent #:
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Issue Dt:
|
07/20/2010
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Application #:
|
11497688
|
Filing Dt:
|
07/31/2006
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Publication #:
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|
Pub Dt:
|
11/23/2006
| | | | |
Title:
|
METHODS OF FABRICATING INTEGRATED CIRCUITRY
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|
|
Patent #:
|
|
Issue Dt:
|
05/04/2010
|
Application #:
|
11497689
|
Filing Dt:
|
07/31/2006
|
Publication #:
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|
Pub Dt:
|
11/23/2006
| | | | |
Title:
|
METHODS OF FORMING LAYERS COMPRISING EPITAXIAL SILICON
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|
|
Patent #:
|
|
Issue Dt:
|
04/12/2011
|
Application #:
|
11497692
|
Filing Dt:
|
07/31/2006
|
Publication #:
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Pub Dt:
|
11/23/2006
| | | | |
Title:
|
ATOMIC LAYER DEPOSITION METHOD OF FORMING CONDUCTIVE METAL NITRIDE-COMPRISING LAYERS
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|
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Patent #:
|
|
Issue Dt:
|
11/04/2008
|
Application #:
|
11497701
|
Filing Dt:
|
08/01/2006
|
Publication #:
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|
Pub Dt:
|
11/30/2006
| | | | |
Title:
|
TRANSISTOR STRUCTURES AND TRANSISTORS WITH A GERMANIUM-CONTAINING CHANNELS
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|
|
Patent #:
|
|
Issue Dt:
|
03/02/2010
|
Application #:
|
11497702
|
Filing Dt:
|
08/01/2006
|
Publication #:
|
|
Pub Dt:
|
02/15/2007
| | | | |
Title:
|
ETCHING METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/27/2010
|
Application #:
|
11497849
|
Filing Dt:
|
08/02/2006
|
Publication #:
|
|
Pub Dt:
|
02/28/2008
| | | | |
Title:
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INTEGRATED TESTING APPARATUS, SYSTEMS, AND METHODS
|
|