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NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:047243/0001   Pages: 959
Recorded: 08/23/2018
Attorney Dkt #:4816.238
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
1
Patent #:
Issue Dt:
06/16/2009
Application #:
11486819
Filing Dt:
07/14/2006
Publication #:
Pub Dt:
11/16/2006
Title:
SEMICONDUCTOR DEVICE INCLUDING CONTAINER HAVING EPITAXIAL SILICON THEREIN
2
Patent #:
Issue Dt:
12/25/2007
Application #:
11486872
Filing Dt:
07/14/2006
Publication #:
Pub Dt:
11/16/2006
Title:
METHOD OF RESETTING PHASE CHANGE MEMORY BITS THROUGH A SERIES OF PULSES OF INCREASING AMPLITUDE
3
Patent #:
Issue Dt:
07/08/2008
Application #:
11487080
Filing Dt:
07/14/2006
Publication #:
Pub Dt:
11/16/2006
Title:
METHODS FOR FORMING AN ENRICHED METAL OXIDE SURFACE
4
Patent #:
Issue Dt:
04/13/2010
Application #:
11487209
Filing Dt:
07/14/2006
Publication #:
Pub Dt:
01/17/2008
Title:
BOTTOM ELECTRODE CONTACTS FOR SEMICONDUCTOR DEVICES AND METHODS OF FORMING SAME
5
Patent #:
Issue Dt:
02/05/2013
Application #:
11487246
Filing Dt:
07/14/2006
Publication #:
Pub Dt:
01/17/2008
Title:
SEMICONDUCTOR DEVICE FABRICATION AND DRY DEVELOP PROCESS SUITABLE FOR CRITICAL DIMENSION TUNABILITY AND PROFILE CONTROL
6
Patent #:
Issue Dt:
03/30/2010
Application #:
11487403
Filing Dt:
07/17/2006
Publication #:
Pub Dt:
11/16/2006
Title:
METHODS OF ELIMINATING PATTERN COLLAPSE ON PHOTORESIST PATTERNS
7
Patent #:
Issue Dt:
02/26/2008
Application #:
11487857
Filing Dt:
07/17/2006
Publication #:
Pub Dt:
11/16/2006
Title:
HANDLING DEFECTIVE MEMORY BLOCKS OF NAND MEMORY DEVICES
8
Patent #:
Issue Dt:
10/13/2009
Application #:
11488384
Filing Dt:
07/17/2006
Publication #:
Pub Dt:
01/17/2008
Title:
CAPACITORLESS ONE TRANSISTOR DRAM CELL, INTEGRATED CIRCUITRY COMPRISING AN ARRAY OF CAPACITORLESS ONE TRANSISTOR DRAM CELLS, AND METHOD OF FORMING LINES OF CAPACITORLESS ONE TRANSISTOR DRAM CELLS
9
Patent #:
Issue Dt:
11/06/2007
Application #:
11488579
Filing Dt:
07/17/2006
Publication #:
Pub Dt:
11/16/2006
Title:
METHODS OF FORMING A REACTION PRODUCT AND METHODS OF FORMING A CONDUCTIVE METAL SILICIDE BY REACTION OF METAL WITH SILICON
10
Patent #:
Issue Dt:
12/22/2009
Application #:
11488587
Filing Dt:
07/17/2006
Publication #:
Pub Dt:
01/17/2008
Title:
METHODS OF FORMING CAPACITORS
11
Patent #:
Issue Dt:
04/13/2010
Application #:
11488934
Filing Dt:
07/17/2006
Publication #:
Pub Dt:
11/23/2006
Title:
NUCLEATION METHOD FOR ATOMIC LAYER DEPOSITION OF COBALT ON BARE SILICON DURING THE FORMATION OF A SEMICONDUCTOR DEVICE
12
Patent #:
Issue Dt:
03/04/2008
Application #:
11488962
Filing Dt:
07/19/2006
Publication #:
Pub Dt:
11/23/2006
Title:
VERTICAL NROM NAND FLASH MEMORY ARRAY
13
Patent #:
Issue Dt:
02/26/2008
Application #:
11489119
Filing Dt:
07/19/2006
Publication #:
Pub Dt:
11/16/2006
Title:
APPARATUS AND METHOD TO REDUCE UNDESIRABLE EFFECTS CAUSED BY A FAULT IN A MEMORY DEVICE
14
Patent #:
Issue Dt:
06/09/2009
Application #:
11489321
Filing Dt:
07/19/2006
Publication #:
Pub Dt:
11/16/2006
Title:
ERASE BLOCK DATA SPLITTING
15
Patent #:
Issue Dt:
01/05/2010
Application #:
11489778
Filing Dt:
07/20/2006
Publication #:
Pub Dt:
11/16/2006
Title:
MEMORY DEVICE CONTROLLER
16
Patent #:
Issue Dt:
08/21/2007
Application #:
11489880
Filing Dt:
07/20/2006
Publication #:
Pub Dt:
11/16/2006
Title:
ONE-TRANSISTOR COMPOSITE-GATE MEMORY
17
Patent #:
Issue Dt:
09/08/2009
Application #:
11489904
Filing Dt:
07/20/2006
Publication #:
Pub Dt:
11/16/2006
Title:
MEMORY DEVICE CONTROLLER
18
Patent #:
Issue Dt:
09/15/2009
Application #:
11490073
Filing Dt:
07/21/2006
Publication #:
Pub Dt:
01/25/2007
Title:
SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING THE SAME
19
Patent #:
Issue Dt:
04/28/2009
Application #:
11490214
Filing Dt:
07/20/2006
Publication #:
Pub Dt:
02/22/2007
Title:
CURRENT DIFFERENTIAL BUFFER
20
Patent #:
Issue Dt:
01/27/2009
Application #:
11490294
Filing Dt:
07/20/2006
Publication #:
Pub Dt:
11/16/2006
Title:
DRAM CELLS WITH VERTICAL TRANSISTORS
21
Patent #:
Issue Dt:
10/13/2009
Application #:
11490619
Filing Dt:
07/21/2006
Publication #:
Pub Dt:
11/16/2006
Title:
MEMORY ARRAY BURIED DIGIT LINE
22
Patent #:
Issue Dt:
07/07/2009
Application #:
11490681
Filing Dt:
07/21/2006
Publication #:
Pub Dt:
11/16/2006
Title:
METHODS OF FORMING FIELD EFFECT TRANSISTORS
23
Patent #:
Issue Dt:
04/15/2008
Application #:
11490712
Filing Dt:
07/20/2006
Publication #:
Pub Dt:
11/16/2006
Title:
METHOD OF FORMING A FIELD EFFECT TRANSISTOR INCLUDING DEPOSITING AND REMOVING INSULATIVE MATERIAL EFFECTIVE TO EXPOSE TRANSISTOR GATE CONDUCTIVE MATERIAL BUT NOT TRANSISTOR GATE SEMICONDUCTIVE MATERIAL
24
Patent #:
NONE
Issue Dt:
Application #:
11490767
Filing Dt:
07/21/2006
Publication #:
Pub Dt:
11/23/2006
Title:
Single-ended pseudo-differential output driver
25
Patent #:
Issue Dt:
04/21/2009
Application #:
11491066
Filing Dt:
07/21/2006
Publication #:
Pub Dt:
11/16/2006
Title:
VERTICAL TRANSISTORS
26
Patent #:
Issue Dt:
07/15/2008
Application #:
11491331
Filing Dt:
07/21/2006
Publication #:
Pub Dt:
11/16/2006
Title:
PROGRAM FAILURE RECOVERY
27
Patent #:
Issue Dt:
11/23/2010
Application #:
11491383
Filing Dt:
07/20/2006
Publication #:
Pub Dt:
11/16/2006
Title:
ATOMIC LAYER DEPOSITION METHOD OF DEPOSITING AN OXIDE ON A SUBSTRATE
28
Patent #:
Issue Dt:
05/06/2008
Application #:
11491461
Filing Dt:
07/21/2006
Publication #:
Pub Dt:
11/16/2006
Title:
MEMORY ARRAY BURIED DIGIT LINE
29
Patent #:
Issue Dt:
10/27/2009
Application #:
11491640
Filing Dt:
07/24/2006
Publication #:
Pub Dt:
07/19/2007
Title:
MEMORY WITH TEST MODE OUTPUT
30
Patent #:
Issue Dt:
06/23/2015
Application #:
11492138
Filing Dt:
07/24/2006
Publication #:
Pub Dt:
11/16/2006
Title:
Method and apparatus for fabricating a memory device with a dielectric etch stop layer
31
Patent #:
Issue Dt:
01/18/2011
Application #:
11492250
Filing Dt:
07/25/2006
Publication #:
Pub Dt:
07/19/2007
Title:
CIRCUITS AND METHODS FOR REPAIRING DEFECTS IN MEMORY DEVICES
32
Patent #:
Issue Dt:
02/24/2009
Application #:
11492251
Filing Dt:
07/25/2006
Publication #:
Pub Dt:
11/23/2006
Title:
MEMORY UTILIZING OXIDE-NITRIDE NANOLAMINATES
33
Patent #:
Issue Dt:
11/16/2010
Application #:
11492254
Filing Dt:
07/25/2006
Publication #:
Pub Dt:
07/19/2007
Title:
CIRCUITS AND METHODS FOR REPAIRING DEFECTS IN MEMORY DEVICES
34
Patent #:
NONE
Issue Dt:
Application #:
11492272
Filing Dt:
07/25/2006
Publication #:
Pub Dt:
11/23/2006
Title:
Memory block erasing in a flash memory device
35
Patent #:
Issue Dt:
01/05/2010
Application #:
11492342
Filing Dt:
07/25/2006
Publication #:
Pub Dt:
02/07/2008
Title:
MULTI-LAYER STRUCTURES FOR PARAMETER MEASUREMENT
36
Patent #:
Issue Dt:
08/19/2008
Application #:
11492479
Filing Dt:
07/25/2006
Publication #:
Pub Dt:
11/23/2006
Title:
DIE-WAFER PACKAGE AND METHOD OF FABRICATING SAME
37
Patent #:
Issue Dt:
04/07/2009
Application #:
11492596
Filing Dt:
07/25/2006
Publication #:
Pub Dt:
11/23/2006
Title:
MEMORY BLOCK ERASING IN A FLASH MEMORY DEVICE
38
Patent #:
Issue Dt:
11/16/2010
Application #:
11492620
Filing Dt:
07/25/2006
Publication #:
Pub Dt:
11/23/2006
Title:
RECESSED GATE DIELECTRIC ANTIFUSE
39
Patent #:
Issue Dt:
11/20/2007
Application #:
11492650
Filing Dt:
07/25/2006
Publication #:
Pub Dt:
11/16/2006
Title:
PLATING BUSS AND A METHOD OF USE THEREOF
40
Patent #:
Issue Dt:
11/09/2010
Application #:
11492655
Filing Dt:
07/25/2006
Publication #:
Pub Dt:
03/01/2007
Title:
HIGH PERMEABILITY LAYERED FILMS TO REDUCE NOISE IN HIGH SPEED INTERCONNECTS
41
Patent #:
Issue Dt:
02/10/2009
Application #:
11492749
Filing Dt:
07/25/2006
Publication #:
Pub Dt:
11/16/2006
Title:
MEMORY UTILIZING OXIDE-NITRIDE NANOLAMINATES
42
Patent #:
Issue Dt:
11/09/2010
Application #:
11492764
Filing Dt:
07/26/2006
Publication #:
Pub Dt:
11/30/2006
Title:
TAPED SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE
43
Patent #:
Issue Dt:
05/27/2008
Application #:
11492765
Filing Dt:
07/26/2006
Publication #:
Pub Dt:
01/31/2008
Title:
METHOD AND APPARATUS FOR CHARGING LARGE CAPACITANCES
44
Patent #:
Issue Dt:
06/29/2010
Application #:
11492823
Filing Dt:
07/26/2006
Publication #:
Pub Dt:
02/01/2007
Title:
METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND THE SEMICONDUCTOR DEVICE
45
Patent #:
Issue Dt:
11/02/2010
Application #:
11493053
Filing Dt:
07/26/2006
Publication #:
Pub Dt:
11/23/2006
Title:
METHOD TO ADDRESS CARBON INCORPORATION IN AN INTERPOLY OXIDE
46
Patent #:
Issue Dt:
06/01/2010
Application #:
11493112
Filing Dt:
07/26/2006
Publication #:
Pub Dt:
11/23/2006
Title:
ZIRCONIUM-DOPED TANTALUM OXIDE FILMS
47
Patent #:
Issue Dt:
09/08/2009
Application #:
11493113
Filing Dt:
07/26/2006
Publication #:
Pub Dt:
11/23/2006
Title:
CAPACITIVELY-COUPLED LEVEL RESTORE CIRCUITS FOR LOW VOLTAGE SWING LOGIC CIRCUITS
48
Patent #:
Issue Dt:
12/04/2007
Application #:
11493127
Filing Dt:
07/26/2006
Publication #:
Pub Dt:
11/23/2006
Title:
COMMAND SEQUENCE FOR OPTIMIZED POWER CONSUMPTION
49
Patent #:
Issue Dt:
03/17/2009
Application #:
11493128
Filing Dt:
07/26/2006
Publication #:
Pub Dt:
11/23/2006
Title:
SEMICONDUCTORS BONDED ON GLASS SUBSTRATES
50
Patent #:
Issue Dt:
03/18/2008
Application #:
11493199
Filing Dt:
07/26/2006
Publication #:
Pub Dt:
02/14/2008
Title:
PUBLIC KEY CRYPTOGRAPHY USING MATRICES
51
Patent #:
Issue Dt:
02/17/2009
Application #:
11493335
Filing Dt:
07/26/2006
Publication #:
Pub Dt:
12/28/2006
Title:
TECHNIQUES TO CREATE LOW K ILD FORMING VOIDS BETWEEN METAL LINES
52
Patent #:
Issue Dt:
10/02/2007
Application #:
11493872
Filing Dt:
07/26/2006
Publication #:
Pub Dt:
11/23/2006
Title:
DELAY CIRCUIT WITH RESET-BASED FORWARD PATH STATIC DELAY
53
Patent #:
Issue Dt:
10/28/2008
Application #:
11493960
Filing Dt:
07/27/2006
Publication #:
Pub Dt:
11/23/2006
Title:
SWITCHED CAPACITOR DRAM SENSE AMPLIFIER WITH IMMUNITY TO MISMATCH AND OFFSETS
54
Patent #:
Issue Dt:
10/28/2008
Application #:
11493961
Filing Dt:
07/27/2006
Publication #:
Pub Dt:
11/23/2006
Title:
SWTICHED CAPACITOR DRAM SENSE AMPLIFIER WITH IMMUNITY TO MISMATCH AND OFFSETS
55
Patent #:
Issue Dt:
04/10/2007
Application #:
11493966
Filing Dt:
07/27/2006
Publication #:
Pub Dt:
11/23/2006
Title:
CMOS AMPLIFIERS WITH FREQUENCY COMPENSATING CAPACITORS
56
Patent #:
Issue Dt:
11/10/2015
Application #:
11493967
Filing Dt:
07/27/2006
Publication #:
Pub Dt:
11/23/2006
Title:
SYSTEMS AND METHODS FOR FORMING ZIRCONIUM AND/OR HAFNIUM-CONTAINING LAYERS
57
Patent #:
Issue Dt:
08/26/2008
Application #:
11494027
Filing Dt:
07/27/2006
Publication #:
Pub Dt:
12/28/2006
Title:
CMOS AMPLIFIERS WITH FREQUENCY COMPENSATING CAPACITORS
58
Patent #:
Issue Dt:
06/23/2009
Application #:
11494038
Filing Dt:
07/27/2006
Publication #:
Pub Dt:
11/23/2006
Title:
METHODS OF TESTING MEMORY DEVICES
59
Patent #:
Issue Dt:
05/06/2008
Application #:
11494319
Filing Dt:
07/27/2006
Publication #:
Pub Dt:
11/30/2006
Title:
STRAINED SI/SIGE/SOI ISLANDS AND PROCESSES OF MAKING SAME
60
Patent #:
Issue Dt:
09/18/2007
Application #:
11494356
Filing Dt:
07/26/2006
Publication #:
Pub Dt:
11/23/2006
Title:
LOW VOLTAGE CMOS DIFFERENTIAL AMPLIFIER
61
Patent #:
Issue Dt:
08/19/2008
Application #:
11494420
Filing Dt:
07/27/2006
Publication #:
Pub Dt:
11/23/2006
Title:
SILICON PILLARS FOR VERTICAL TRANSISTORS
62
Patent #:
Issue Dt:
03/10/2009
Application #:
11494432
Filing Dt:
07/27/2006
Publication #:
Pub Dt:
01/31/2008
Title:
PORTABLE ELECTRONIC DEVICE WITH BUILT-IN TERMINAL COVER STRUCTURE
63
Patent #:
Issue Dt:
10/04/2011
Application #:
11494808
Filing Dt:
07/28/2006
Publication #:
Pub Dt:
02/08/2007
Title:
POWER SINK FOR IC TEMPERATURE CONTROL
64
Patent #:
Issue Dt:
03/16/2010
Application #:
11494844
Filing Dt:
07/28/2006
Publication #:
Pub Dt:
11/23/2006
Title:
METHOD TO CHEMICALLY REMOVE METAL IMPURITIES FROM POLYCIDE GATE SIDEWALLS
65
Patent #:
Issue Dt:
08/19/2008
Application #:
11494982
Filing Dt:
07/28/2006
Publication #:
Pub Dt:
11/23/2006
Title:
METHODS FOR FORMING VIAS IN MICROELECTRONIC DEVICES, AND METHODS FOR PACKAGING MICROELECTRONIC DEVICES
66
Patent #:
Issue Dt:
12/18/2007
Application #:
11495233
Filing Dt:
07/28/2006
Publication #:
Pub Dt:
11/30/2006
Title:
METHOD, APPARATUS, AND SYSTEM FOR LOW VOLTAGE TEMPERATURE SENSING
67
Patent #:
Issue Dt:
09/16/2008
Application #:
11495245
Filing Dt:
07/28/2006
Publication #:
Pub Dt:
11/23/2006
Title:
NAND FLASH CELL STRUCTURE
68
Patent #:
Issue Dt:
06/16/2009
Application #:
11495418
Filing Dt:
07/28/2006
Publication #:
Pub Dt:
11/23/2006
Title:
DUAL EDGE COMMAND
69
Patent #:
Issue Dt:
04/28/2009
Application #:
11495438
Filing Dt:
07/28/2006
Publication #:
Pub Dt:
12/07/2006
Title:
PROCESS OF FORMING A SEMICONDUCTOR ASSEMBLY HAVING A CONTACT STRUCTURE AND CONTACT LINER
70
Patent #:
Issue Dt:
02/10/2009
Application #:
11495473
Filing Dt:
07/28/2006
Publication #:
Pub Dt:
01/25/2007
Title:
METHOD OF MAKING VERTICAL TRANSISTOR STRUCTURES HAVING VERTICAL-SURROUNDING-GATES WITH SELF-ALIGNED FEATURES
71
Patent #:
Issue Dt:
01/12/2016
Application #:
11495499
Filing Dt:
07/28/2006
Publication #:
Pub Dt:
11/23/2006
Title:
METHOD AND APPARATUS FOR FABRICATING A MEMORY DEVICE WITH A DIELECTRIC ETCH STOP LAYER
72
Patent #:
Issue Dt:
12/01/2009
Application #:
11495507
Filing Dt:
07/28/2006
Publication #:
Pub Dt:
01/31/2008
Title:
NAND FLASH MEMORY PROGRAMMING
73
Patent #:
Issue Dt:
10/13/2009
Application #:
11495550
Filing Dt:
07/31/2006
Publication #:
Pub Dt:
02/15/2007
Title:
SEMICONDUCTOR DEVICE HAVING A SENSE AMPLIFIER ARRAY WITH ADJACENT ECC
74
Patent #:
Issue Dt:
07/20/2010
Application #:
11495654
Filing Dt:
07/28/2006
Publication #:
Pub Dt:
11/23/2006
Title:
DUAL WORK FUNCTION METAL GATES AND METHODS OF FORMING
75
Patent #:
Issue Dt:
10/14/2014
Application #:
11495805
Filing Dt:
07/28/2006
Publication #:
Pub Dt:
11/15/2007
Title:
RECESSED ANTIFUSE STRUCTURES AND METHODS OF MAKING THE SAME
76
Patent #:
Issue Dt:
05/20/2008
Application #:
11495848
Filing Dt:
07/28/2006
Publication #:
Pub Dt:
11/23/2006
Title:
METHOD AND APPARATUS FOR TIMING DOMAIN CROSSING
77
Patent #:
Issue Dt:
11/18/2008
Application #:
11495866
Filing Dt:
07/27/2006
Publication #:
Pub Dt:
11/23/2006
Title:
DIGITAL DATA APPARATUSES AND DIGITAL DATA OPERATIONAL METHODS
78
Patent #:
Issue Dt:
02/09/2010
Application #:
11495869
Filing Dt:
07/28/2006
Publication #:
Pub Dt:
11/23/2006
Title:
METHOD AND APPARATUS FOR FABRICATING A MEMORY DEVICE WITH A DIELECTRIC ETCH STOP LAYER
79
Patent #:
Issue Dt:
04/22/2008
Application #:
11495886
Filing Dt:
07/28/2006
Publication #:
Pub Dt:
02/08/2007
Title:
NAND FLASH MEMORY WITH ERASE VERIFY BASED ON SHORTER EVALUATION TIME
80
Patent #:
Issue Dt:
05/08/2007
Application #:
11496169
Filing Dt:
07/31/2006
Publication #:
Pub Dt:
11/23/2006
Title:
CONTROLLING MULTIPLE SIGNAL POLARITY IN A SEMICONDUCTOR DEVICE
81
Patent #:
Issue Dt:
08/17/2010
Application #:
11496180
Filing Dt:
07/31/2006
Publication #:
Pub Dt:
12/07/2006
Title:
SEMICONDUCTOR COMPONENTS AND METHODS OF FABRICATION WITH CIRCUIT SIDE CONTACTS, CONDUCTIVE VIAS AND BACKSIDE CONDUCTORS
82
Patent #:
Issue Dt:
03/30/2010
Application #:
11496196
Filing Dt:
07/31/2006
Publication #:
Pub Dt:
09/03/2009
Title:
MEMORY UTILIZING OXIDE-CONDUCTOR NANOLAMINATES
83
Patent #:
Issue Dt:
12/11/2007
Application #:
11496210
Filing Dt:
07/31/2006
Publication #:
Pub Dt:
11/30/2006
Title:
SOLDERMASK OPENING TO PREVENT DELAMINATION
84
Patent #:
Issue Dt:
04/13/2010
Application #:
11496302
Filing Dt:
07/31/2006
Publication #:
Pub Dt:
11/23/2006
Title:
METHOD AND APPARATUS FOR ADDRESS FIFO FOR HIGH-BANDWIDTH COMMAND/ADDRESS BUSSES IN DIGITAL STORAGE SYSTEM
85
Patent #:
Issue Dt:
02/17/2009
Application #:
11496342
Filing Dt:
07/31/2006
Publication #:
Pub Dt:
11/30/2006
Title:
VERTICAL TRANSISTOR WITH HORIZONTAL GATE LAYERS
86
Patent #:
Issue Dt:
03/18/2008
Application #:
11496605
Filing Dt:
07/31/2006
Publication #:
Pub Dt:
11/30/2006
Title:
DOUBLE SIDED CONTAINER PROCESS USED DURING THE MANUFACTURE OF A SEMICONDUCTOR DEVICE
87
Patent #:
Issue Dt:
08/25/2009
Application #:
11496655
Filing Dt:
07/31/2006
Publication #:
Pub Dt:
11/23/2006
Title:
METHOD OF MAKING VERTICAL TRANSISTOR WITH HORIZONTAL GATE LAYERS
88
Patent #:
Issue Dt:
03/10/2009
Application #:
11496930
Filing Dt:
07/31/2006
Publication #:
Pub Dt:
11/23/2006
Title:
METHODS OF FORMING SEMICONDUCTOR CONSTRUCTIONS
89
Patent #:
Issue Dt:
08/26/2008
Application #:
11497126
Filing Dt:
08/01/2006
Publication #:
Pub Dt:
11/23/2006
Title:
METHODS OF REDUCING COUPLING NOISE BETWEEN WORDLINES
90
Patent #:
Issue Dt:
02/19/2008
Application #:
11497136
Filing Dt:
08/01/2006
Publication #:
Pub Dt:
11/23/2006
Title:
VERTICAL DEVICE 4F¿ EEPROM MEMORY
91
Patent #:
Issue Dt:
12/02/2008
Application #:
11497176
Filing Dt:
08/01/2006
Publication #:
Pub Dt:
12/07/2006
Title:
MEMORY DEVICES HAVING REDUCED COUPLING NOISE BETWEEN WORDLINES
92
Patent #:
Issue Dt:
10/21/2008
Application #:
11497598
Filing Dt:
07/31/2006
Publication #:
Pub Dt:
11/23/2006
Title:
METHOD OF FORMING INTEGRATED CIRCUITRY
93
Patent #:
Issue Dt:
02/03/2009
Application #:
11497632
Filing Dt:
08/02/2006
Publication #:
Pub Dt:
02/07/2008
Title:
STRAINED SEMICONDUCTOR, DEVICES AND SYSTEMS AND METHODS OF FORMATION
94
Patent #:
Issue Dt:
11/24/2009
Application #:
11497665
Filing Dt:
08/01/2006
Publication #:
Pub Dt:
11/30/2006
Title:
ISOLATION TRENCH
95
Patent #:
Issue Dt:
07/20/2010
Application #:
11497688
Filing Dt:
07/31/2006
Publication #:
Pub Dt:
11/23/2006
Title:
METHODS OF FABRICATING INTEGRATED CIRCUITRY
96
Patent #:
Issue Dt:
05/04/2010
Application #:
11497689
Filing Dt:
07/31/2006
Publication #:
Pub Dt:
11/23/2006
Title:
METHODS OF FORMING LAYERS COMPRISING EPITAXIAL SILICON
97
Patent #:
Issue Dt:
04/12/2011
Application #:
11497692
Filing Dt:
07/31/2006
Publication #:
Pub Dt:
11/23/2006
Title:
ATOMIC LAYER DEPOSITION METHOD OF FORMING CONDUCTIVE METAL NITRIDE-COMPRISING LAYERS
98
Patent #:
Issue Dt:
11/04/2008
Application #:
11497701
Filing Dt:
08/01/2006
Publication #:
Pub Dt:
11/30/2006
Title:
TRANSISTOR STRUCTURES AND TRANSISTORS WITH A GERMANIUM-CONTAINING CHANNELS
99
Patent #:
Issue Dt:
03/02/2010
Application #:
11497702
Filing Dt:
08/01/2006
Publication #:
Pub Dt:
02/15/2007
Title:
ETCHING METHODS
100
Patent #:
Issue Dt:
04/27/2010
Application #:
11497849
Filing Dt:
08/02/2006
Publication #:
Pub Dt:
02/28/2008
Title:
INTEGRATED TESTING APPARATUS, SYSTEMS, AND METHODS
Assignor
1
Exec Dt:
06/29/2018
Assignee
1
8000 S. FEDERAL WAY
BOISE, IDAHO 83707
Correspondence name and address
WSGR, C/O QUI LU FLOOD, SENIOR PARALEGAL
ONE MARKET, SPEAR TOWER, SUITE 3300
SAN FRANCISCO, CA 94105

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