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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:047243/0001   Pages: 959
Recorded: 08/23/2018
Attorney Dkt #:4816.238
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
1
Patent #:
Issue Dt:
04/06/1999
Application #:
08874241
Filing Dt:
06/13/1997
Title:
MEMORY ARCHITECTURE AND DECODER ADDRESSING
2
Patent #:
Issue Dt:
03/14/2000
Application #:
08874389
Filing Dt:
06/13/1997
Title:
METHOD OF FABRICATING INTEGRATED CIRCUIT WIRING WITH LOW RC TIME DELAY
3
Patent #:
Issue Dt:
05/04/1999
Application #:
08874496
Filing Dt:
06/13/1997
Title:
VARIABLE LOADING APPARATUS FOR OUTPUT LOADING OF INTEGRATED CIRCUITS
4
Patent #:
Issue Dt:
12/28/1999
Application #:
08874602
Filing Dt:
06/13/1997
Title:
AUTOMATED LOAD DETERMINATION FOR PARTITIONED SIMULATION
5
Patent #:
Issue Dt:
08/31/1999
Application #:
08877066
Filing Dt:
06/17/1997
Title:
SINGLE-CELL REFERENCE SIGNAL GENERATING CIRCUIT FOR READING NONVOLATILE MEMORY
6
Patent #:
Issue Dt:
07/18/2000
Application #:
08877527
Filing Dt:
06/16/1997
Title:
METHOD OF ETCHING THERMALLY GROWN OXIDE SUBSTANTIALLY SELECTIVELY RELATIVE TO DEPOSITED OXIDE
7
Patent #:
Issue Dt:
08/24/1999
Application #:
08877613
Filing Dt:
06/17/1997
Title:
TREATMENT OF A SURFACE HAVING AN EXPOSE SILICON./SILICA INTERFACE
8
Patent #:
Issue Dt:
10/19/1999
Application #:
08877788
Filing Dt:
06/18/1997
Title:
METHOD FOR ETCHING NITRIDE FEATURES IN INTEGRATED CIRCUIT CONSTRUCTION
9
Patent #:
Issue Dt:
09/08/1998
Application #:
08877921
Filing Dt:
06/18/1997
Title:
CIRCUIT AND METHOD FOR GENERATING A READ REFERENCE SIGNAL FOR NONVOLATILE MEMORY CELLS
10
Patent #:
Issue Dt:
03/23/1999
Application #:
08877922
Filing Dt:
06/18/1997
Title:
READ CIRCUIT AND METHOD FOR NONVOLATILE MEMORY CELLS WITH AN EQUALIZING STRUCTURE
11
Patent #:
Issue Dt:
05/11/1999
Application #:
08877927
Filing Dt:
06/18/1997
Title:
LOW-SUPPLY-VOLTAGE NONVOLATILE MEMORY DEVICE WITH VOLTAGE BOOSTING
12
Patent #:
Issue Dt:
05/04/1999
Application #:
08878657
Filing Dt:
06/19/1997
Title:
VARIABLE VOLTAGE ISOLATION GATE AND METHOD
13
Patent #:
Issue Dt:
07/27/1999
Application #:
08878752
Filing Dt:
06/19/1997
Title:
MEMORY DEVICE HAVING TWO OR MORE MEMORY ARRAYS AND A TESTPATH CONNECTED TO ONE OF THE MEMORY ARRAYS AND NOT OPERABLY CONNECTED TO ANOTHER MEMORY ARRAY, AND A METHOD OF OPERATING THE TESTPATH
14
Patent #:
Issue Dt:
03/09/1999
Application #:
08878935
Filing Dt:
06/19/1997
Title:
PLASTIC LEAD FRAMES FOR SEMICONDUCTOR DEVICES, PACKAGES INCLUDING SAME, AND METHODS OF FABRICATION
15
Patent #:
Issue Dt:
10/03/2000
Application #:
08879017
Filing Dt:
06/18/1997
Title:
METHOD AND CIRCUIT FOR READING LOW-SUPPLY-VOLTAGE NONVOLATILE MEMORY CELLS
16
Patent #:
Issue Dt:
02/01/2000
Application #:
08879400
Filing Dt:
06/20/1997
Title:
COMPUTER SYSTEM CAPABLE OF SYMMETRICAL PROCESSING
17
Patent #:
Issue Dt:
02/29/2000
Application #:
08879409
Filing Dt:
06/20/1997
Title:
METHOD AND APPARATUS FOR COMPRESSED DATA TESTING OF MORE THAN ONE MEMORY ARRAY
18
Patent #:
Issue Dt:
03/23/1999
Application #:
08879833
Filing Dt:
06/19/1997
Title:
METHOD AND APPARATUS FOR TESTING OF DIELECTRIC DEFECTS IN A PACKAGED SEMICONDUCTOR MEMORY DEVICE
19
Patent #:
Issue Dt:
08/31/1999
Application #:
08879983
Filing Dt:
06/20/1997
Title:
LOW CURRENT REDUNDANCY ANTI-FUSE ASSEMBLY
20
Patent #:
Issue Dt:
03/28/2000
Application #:
08880085
Filing Dt:
06/20/1997
Title:
METHOD FOR SYMMETRICALLY PROCESSING
21
Patent #:
Issue Dt:
09/14/1999
Application #:
08880251
Filing Dt:
06/23/1997
Title:
METHOD OF CHECKING DATA INTEGRITY FOR A RAID 1 SYSTEM
22
Patent #:
Issue Dt:
09/28/1999
Application #:
08880275
Filing Dt:
06/23/1997
Title:
PROCESS OF FORMING TITANIUM SILICIDE INTERCONNECTS
23
Patent #:
Issue Dt:
05/09/2000
Application #:
08880350
Filing Dt:
06/23/1997
Title:
A SYSTEM AND METHOD FOR PROVIDING A FAST AND EFFICIENT COMPARISON OF CYCLIC REDUNDANCY CHECK (CRC/CHECK SUM) VALUES OF TWO MIRRORED DISKS
24
Patent #:
Issue Dt:
06/13/2000
Application #:
08880351
Filing Dt:
06/23/1997
Title:
METHOD FOR TESTING A CONTROLLER WITH RANDOM CONSTRAINTS
25
Patent #:
Issue Dt:
11/14/2000
Application #:
08880356
Filing Dt:
06/23/1997
Title:
PROCESSING METHODS OF FORMING A CAPACITOR
26
Patent #:
Issue Dt:
04/18/2000
Application #:
08880840
Filing Dt:
06/23/1997
Title:
METHOD FOR MOUNTING AN ELEMENT
27
Patent #:
Issue Dt:
03/27/2001
Application #:
08881519
Filing Dt:
06/24/1997
Title:
METHOD FOR FORMING A DIELECTRIC
28
Patent #:
Issue Dt:
11/03/1998
Application #:
08881716
Filing Dt:
06/23/1997
Title:
APPARATUS FOR TESTING A CONTROLLER WITH RANDOM CONTRAINTS
29
Patent #:
Issue Dt:
10/19/1999
Application #:
08881737
Filing Dt:
06/24/1997
Title:
METHOD OF MAKING SEMICONDUCTOR DEVICE INCORPORATING AN ELECTRICAL CONTACT TO AN INTERMAL CONDUCTIVE LAYER
30
Patent #:
Issue Dt:
07/27/1999
Application #:
08883027
Filing Dt:
06/26/1997
Title:
METHOD OF SPUTTER DEPOSITION OF METALS ONTO SUBSTRATES AND METHOD OF FORMING PLASMA
31
Patent #:
Issue Dt:
08/31/1999
Application #:
08883181
Filing Dt:
06/26/1997
Title:
CIRCUIT AND METHOD TO PREVENT INADVERTENT TEST MODE ENTRY
32
Patent #:
Issue Dt:
11/16/1999
Application #:
08883822
Filing Dt:
06/27/1997
Title:
CLOCK CIRCUIT FOR READING A MUTILEVEL NON VOLATILE MEMORY CELLS DEVICE
33
Patent #:
Issue Dt:
11/02/1999
Application #:
08884902
Filing Dt:
06/30/1997
Title:
PACKAGING FOR BARE DICE EMPLOYING EMR-SENSITIVE ADHESIVES
34
Patent #:
Issue Dt:
10/19/1999
Application #:
08885060
Filing Dt:
06/30/1997
Title:
A METHOD FOR FORMING A CAPACITOR, THE FIRST CAPACITOR PLATE OF THE CAPACITOR INCLUDING ELECTRICALLY COUPLED FIRST AND SECOND CONDUCTIVE LAYERS SEPARATED BY AN INTERVENING INSULATIVE LAYER, WHEREIN THE FIRST AND SECOND CONDUCTIVE LAYERS CONSTITUTE DIFFERENT MATERIALS
35
Patent #:
Issue Dt:
07/27/1999
Application #:
08885127
Filing Dt:
06/30/1997
Title:
TRAY FOR PROCESSING AND/OR SHIPPING INTEGRATED CIRCUIT DEVICE
36
Patent #:
Issue Dt:
03/16/1999
Application #:
08885535
Filing Dt:
06/30/1997
Title:
METHOD AND APPARATUS FOR SIMULTANEOUS MEMORY SUBARRAY TESTING
37
Patent #:
Issue Dt:
05/30/2000
Application #:
08885803
Filing Dt:
06/30/1997
Title:
SCALABLE RECEIVER STRUCTURE FOR EFFICIENT BIT SEQUENCE DECODING
38
Patent #:
Issue Dt:
08/31/1999
Application #:
08886384
Filing Dt:
07/01/1997
Title:
FIELD EFFECT TRANSISTOR ASSEMBLIES AND TRANSISTOR GATE BLOCK STACKS
39
Patent #:
Issue Dt:
04/20/1999
Application #:
08886529
Filing Dt:
07/02/1997
Title:
POSITIONER FOR OVERHANGING COMPONENTS
40
Patent #:
Issue Dt:
01/04/2000
Application #:
08886707
Filing Dt:
07/01/1997
Title:
METHOD FOR FORMING A SEMICONDUCTOR BURIED CONTACT WITH A REMOVABLE SPACER
41
Patent #:
Issue Dt:
12/12/2000
Application #:
08887381
Filing Dt:
07/02/1997
Title:
VARIED-THICKNESS HEAT SINK FOR INTEGRATED CIRCUIT (IC) PACKAGES AND METHOD OF FABRICATING IC PACKAGES
42
Patent #:
Issue Dt:
12/31/2002
Application #:
08887547
Filing Dt:
07/03/1997
Title:
METHOD FOR IMPROVING A STEPPER SIGNAL IN A PLANARIZED SURFACE OVER ALIGNMENT TOPOGRAPHY
43
Patent #:
Issue Dt:
08/10/1999
Application #:
08887687
Filing Dt:
07/03/1997
Title:
INTERLOCKING CONDUCTIVE PLUG FOR USE WITH AN INTEGRATED CIRCUIT
44
Patent #:
Issue Dt:
08/03/1999
Application #:
08887801
Filing Dt:
07/03/1997
Title:
SEMICONDUCTOR CIRCUIT INTERCONNECTIONS AND METHODS OF MAKING SUCH INTERCONNECTIONS
45
Patent #:
Issue Dt:
02/13/2001
Application #:
08887915
Filing Dt:
07/02/1997
Title:
A ROUGH ELECTRODE (HIGH SURFACE AREA) FROM TI AND TIN
46
Patent #:
Issue Dt:
03/21/2000
Application #:
08888075
Filing Dt:
07/03/1997
Title:
CARRIER AND SYSTEM FOR TESTING BUMPED SEMICONDUCTOR COMPONENTS
47
Patent #:
Issue Dt:
09/21/1999
Application #:
08888336
Filing Dt:
07/02/1997
Title:
LEAD FRAME ASSEMBLIES WITH VOLTAGE REFERENCE PLANE AND IC PACKAGES INCLUDING SAME
48
Patent #:
Issue Dt:
04/23/2002
Application #:
08888501
Filing Dt:
07/07/1997
Title:
SYSTEM AND METHOD FOR INVALIDATING CACHE MEMORY
49
Patent #:
Issue Dt:
02/24/1998
Application #:
08888857
Filing Dt:
07/07/1997
Title:
METHOD AND APPARATUS FOR LEAK CHECKING UNPACKAGED SEMICONDUCTOR DICE
50
Patent #:
Issue Dt:
03/30/1999
Application #:
08888994
Filing Dt:
07/07/1997
Title:
WAFER PROCESSING APPARATUS
51
Patent #:
Issue Dt:
02/20/2001
Application #:
08889395
Filing Dt:
07/08/1997
Title:
SEMICONDUCTOR-ON-INSULATOR MEMORY CELL WITH BURIED WORD AND BODY LINES
52
Patent #:
Issue Dt:
06/01/1999
Application #:
08889396
Filing Dt:
07/08/1997
Title:
METHOD OF MAKING MEMORY CELL WITH VERTICAL TRANSISTOR AND BURIED WORD AND BODY LINES
53
Patent #:
Issue Dt:
11/21/2000
Application #:
08889462
Filing Dt:
07/08/1997
Title:
MEMORY CELL HAVING A VERTICAL TRANSISTOR WITH BURIED SOURCE/DRAIN AND DUAL GATES
54
Patent #:
Issue Dt:
06/06/2000
Application #:
08889463
Filing Dt:
07/08/1997
Title:
FOUR F2 FOLDED BIT LINE DRAM CELL STRUCTURE HAVING BURIED BIT AND WORD LINES
55
Patent #:
Issue Dt:
09/07/1999
Application #:
08889535
Filing Dt:
07/08/1997
Title:
METHOD FOR TESTING INTERCONNECTS AND SEMICONDUCTOR DICE
56
Patent #:
Issue Dt:
08/10/1999
Application #:
08889553
Filing Dt:
07/08/1997
Title:
YIGH DENSITY FLASH MEMORY
57
Patent #:
Issue Dt:
10/26/1999
Application #:
08889554
Filing Dt:
07/08/1997
Title:
ULTRA HIGH DENSITY FLASH MEMORY
58
Patent #:
Issue Dt:
05/09/2000
Application #:
08889653
Filing Dt:
07/08/1997
Title:
LOW NOISE OUTPUT BUFFER FOR SEMICONDUCTOR ELECTRONIC CIRCUITS
59
Patent #:
Issue Dt:
04/25/2000
Application #:
08890257
Filing Dt:
07/09/1997
Title:
METHOD AND APPARATUS FOR ENABLING REDUNDANT MEMORY
60
Patent #:
Issue Dt:
08/15/2000
Application #:
08890368
Filing Dt:
07/14/1997
Title:
TREATMENT OF A SURFACE HAVING AN EXPOSED SILICON/SILICA INTERFACE
61
Patent #:
Issue Dt:
11/16/1999
Application #:
08890414
Filing Dt:
07/09/1997
Title:
PACKAGE STACK VIA BOTTOM LEADED PLASTIC (BLP) PACKAGING
62
Patent #:
Issue Dt:
03/28/2000
Application #:
08891097
Filing Dt:
07/10/1997
Title:
METHOD AND APPARATUS FOR COLLISION-FREE DATA TRANSFERS IN A MEMORY DEVICE WITH SELECTABLE DATA OR ADDRESS PATHS
63
Patent #:
Issue Dt:
04/20/1999
Application #:
08891279
Filing Dt:
07/10/1997
Title:
ENCAPSULANT DAM STANDOFF FOR SHELL-ENCLOSED DIE ASSEMBLIES
64
Patent #:
Issue Dt:
04/25/2000
Application #:
08891669
Filing Dt:
07/10/1997
Title:
CIRCUIT FOR PROGRAMMING ANTIFUSE BITS
65
Patent #:
Issue Dt:
06/20/2000
Application #:
08892114
Filing Dt:
07/14/1997
Title:
A METHOD OF FORMING FOAMED POLYMERIC MATERIAL FOR AN INTEGRATED CIRCUIT
66
Patent #:
Issue Dt:
12/08/1998
Application #:
08892605
Filing Dt:
07/14/1997
Title:
CIRCUIT AND METHOD FOR ANTIFUSE STRESS TEST
67
Patent #:
Issue Dt:
10/19/1999
Application #:
08892718
Filing Dt:
07/15/1997
Title:
ALUMINUM-CONTAINING FILMS DERIVED FROM USING HYDROGEN AND OXYGEN GAS IN SPUTTTER DEPOSITION
68
Patent #:
Issue Dt:
04/24/2001
Application #:
08892930
Filing Dt:
07/15/1997
Title:
METHOD OF USING HYDROGEN GAS IN SPUTTER DEPOSITION OF ALUMINUM-CONTAINING FILMS AND ALUMINUM-CONTAINING FILMS DERIVED THEREFROM
69
Patent #:
Issue Dt:
12/22/1998
Application #:
08893931
Filing Dt:
07/14/1997
Title:
A PROCESS FOR FORMING CAPACITOR ARRAY STRUCTURE FOR SEMICONDUCTOR DEVICES
70
Patent #:
Issue Dt:
05/04/1999
Application #:
08893938
Filing Dt:
07/15/1997
Title:
MOBILE STATION LOCATING SYSTEM AND METHOD
71
Patent #:
Issue Dt:
03/16/1999
Application #:
08895620
Filing Dt:
07/17/1997
Title:
FOCUS SPOT DETECTION METHOD AND SYSTEM
72
Patent #:
Issue Dt:
10/08/2002
Application #:
08896490
Filing Dt:
07/18/1997
Publication #:
Pub Dt:
08/16/2001
Title:
LOW CURRENT REDUNDANCY ANTI -FUSE APPARATUS
73
Patent #:
Issue Dt:
12/08/1998
Application #:
08896701
Filing Dt:
07/18/1997
Title:
LOW CURRENCY REDUNDANCY ANTI-FUSE METHOD AND APPARATUS
74
Patent #:
Issue Dt:
11/28/2000
Application #:
08896702
Filing Dt:
07/18/1997
Title:
LOW CURRENT REDUNDANCY ANTI-FUSE METHOD AND APPARATUS
75
Patent #:
Issue Dt:
06/05/2001
Application #:
08896936
Filing Dt:
07/18/1997
Title:
DYNAMIC BUFFER ALLOCATION FOR A COMPUTER SYSTEM
76
Patent #:
Issue Dt:
06/06/2000
Application #:
08896938
Filing Dt:
07/18/1997
Title:
SYSTEM FOR DYNAMIC BUFFER ALLOCATION COMPRISING CONTROL LOGIC FOR CONTROLLING A FIRST ADDRESS BUFFER AND A FIRST DATA BUFFER AS A MATCHED PAIR
77
Patent #:
Issue Dt:
08/10/1999
Application #:
08897364
Filing Dt:
07/22/1997
Title:
FABRICATION OF SEMICONDUCTOR STRUCTURES BY ION IMPLANTATION
78
Patent #:
Issue Dt:
09/28/1999
Application #:
08897492
Filing Dt:
07/21/1997
Title:
CHARGE-PUMPING TO INCREASE ELECTRON COLLECTION EFFICIENCY
79
Patent #:
Issue Dt:
11/02/1999
Application #:
08897799
Filing Dt:
07/21/1997
Title:
PROCESS FOR MANUFACTURING AN INTEGRATED CIRCUIT COMPRISING AN ARRAY OF MEMORY CELLS
80
Patent #:
Issue Dt:
09/07/1999
Application #:
08898099
Filing Dt:
07/22/1997
Title:
LAMINATED FILM/METAL STRUCTURE
81
Patent #:
Issue Dt:
08/15/2000
Application #:
08898155
Filing Dt:
07/22/1997
Title:
METHOD FOR IMPROVING THE INTERMEDIATE DIELECTRIC PROFILE, PARTICULARLY FOR NON-VOLATILE MEMORIES
82
Patent #:
Issue Dt:
11/09/1999
Application #:
08898177
Filing Dt:
07/22/1997
Title:
OUTPUT BUFFER HAVING INHERENTLY PRECISE DATA MASKING
83
Patent #:
Issue Dt:
06/05/2001
Application #:
08898527
Filing Dt:
07/22/1997
Title:
RESISTOR CONSTRUCTIONS
84
Patent #:
Issue Dt:
08/03/1999
Application #:
08898530
Filing Dt:
07/22/1997
Title:
INTEGRATED CIRCUITRY HAVING A PAIR OF ADJACENT CONDUCTIVE LINES AND METHOD OF FORMING
85
Patent #:
Issue Dt:
12/07/1999
Application #:
08898532
Filing Dt:
07/22/1997
Title:
METHODS OF MAKING A SRAM CELL EMPLOYING SUBSTANTIALLY VERTICALLY ELONGATED PULL-UP RESISTORS AND METHODS OF MAKING RESISTOR CONSTRUCTIONS
86
Patent #:
Issue Dt:
11/21/2000
Application #:
08898811
Filing Dt:
07/23/1997
Title:
HIGH VOLTAGE TOLERANCE OUTPUT STAGE
87
Patent #:
Issue Dt:
07/13/1999
Application #:
08898812
Filing Dt:
07/23/1997
Title:
BALL GRID ARRY (BGA) ENCAPSULATION MOLD
88
Patent #:
Issue Dt:
04/10/2001
Application #:
08899228
Filing Dt:
07/23/1997
Title:
OUTPUT STAGE FOR A MEMORY DEVICE AND FOR LOW VOLTAGE APPLICATIONS
89
Patent #:
Issue Dt:
09/28/1999
Application #:
08899524
Filing Dt:
07/24/1997
Title:
SENSE AMPLIFIER FOR COMPLEMENT OR NO-COMPLEMENTARY DATA SIGNALS
90
Patent #:
Issue Dt:
09/15/1998
Application #:
08899525
Filing Dt:
07/24/1997
Title:
METHOD AND APPARATUS FOR READING COMPRESSED TEST DATA FROM MEMORY DEVICES
91
Patent #:
Issue Dt:
01/11/2000
Application #:
08899729
Filing Dt:
07/24/1997
Title:
APPARATUS FOR ATTACHING ADHESIVE TAPE TO LEAD-ON-CHIP LEADFRAMES
92
Patent #:
Issue Dt:
02/06/2001
Application #:
08900165
Filing Dt:
07/28/1997
Title:
BIDIRECTIONAL CHARGE PUMP GENERATING EITHER A POSITIVE OR NEGATIVE VOLTAGE
93
Patent #:
Issue Dt:
04/04/2000
Application #:
08900424
Filing Dt:
07/25/1997
Title:
ASYMMETRICAL PULSIVE DELAY NETWORK
94
Patent #:
Issue Dt:
04/13/1999
Application #:
08901601
Filing Dt:
07/28/1997
Title:
METHOD AND APPARATUS FOR CONTINUOUS PROCESSING OF SEMICONDUCTOR WAFERS
95
Patent #:
Issue Dt:
03/07/2000
Application #:
08901921
Filing Dt:
07/28/1997
Title:
ROTATING SYSTEM AND METHOD FOR ELECTRODEPOSITING MATERIALS ON SEMICONDUCTOR WAFERS
96
Patent #:
Issue Dt:
11/09/1999
Application #:
08902004
Filing Dt:
07/29/1997
Title:
SRAM CELL EMPLOYING SUBSTANTIALLY VERTICALLY ELONGATED PULL-UP RESISTORS AND METHODS OF MAKING, AND RESISTOR CONSTRUCTIONS AND METHODS OF MAKING
97
Patent #:
Issue Dt:
02/29/2000
Application #:
08902098
Filing Dt:
07/29/1997
Title:
DEAPROM AND TRANSISTOR WITH GALLIUM NITRIDE OR GALLIIUM ALUMINIUM NITRIDE GATE
98
Patent #:
Issue Dt:
12/26/2006
Application #:
08902133
Filing Dt:
07/29/1997
Title:
MEMORY DEVICE
99
Patent #:
Issue Dt:
05/09/2000
Application #:
08902470
Filing Dt:
07/29/1997
Title:
METHOD AND APPARATUS PROVIDING REDUNDANCY FOR FABRICATING HIGHLY RELIABLE MEMORY MODULES
100
Patent #:
Issue Dt:
11/17/1998
Application #:
08903198
Filing Dt:
07/15/1997
Title:
INTEGRATED CIRCUITRY WITH INTERCONNECTION PILLAR
Assignor
1
Exec Dt:
06/29/2018
Assignee
1
8000 S. FEDERAL WAY
BOISE, IDAHO 83707
Correspondence name and address
WSGR, C/O QUI LU FLOOD, SENIOR PARALEGAL
ONE MARKET, SPEAR TOWER, SUITE 3300
SAN FRANCISCO, CA 94105

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