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NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:047243/0001   Pages: 959
Recorded: 08/23/2018
Attorney Dkt #:4816.238
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
1
Patent #:
Issue Dt:
10/29/2013
Application #:
12327648
Filing Dt:
12/03/2008
Publication #:
Pub Dt:
06/03/2010
Title:
REDUNDANT SIGNAL TRANSMISSION
2
Patent #:
Issue Dt:
11/02/2010
Application #:
12327667
Filing Dt:
12/03/2008
Publication #:
Pub Dt:
04/30/2009
Title:
MEMORY DEVICE WITH VARIABLE TRIM SETTING
3
Patent #:
Issue Dt:
01/06/2015
Application #:
12327879
Filing Dt:
12/04/2008
Publication #:
Pub Dt:
04/01/2010
Title:
METHOD AND APPARATUS USING LINKED LISTS FOR STREAMING OF DATA FOR SOLID-STATE BULK STORAGE DEVICE
4
Patent #:
Issue Dt:
01/30/2018
Application #:
12328381
Filing Dt:
12/04/2008
Publication #:
Pub Dt:
06/10/2010
Title:
METHOD AND APPARATUS FOR PROVIDING DATA ACCESS
5
Patent #:
Issue Dt:
09/25/2012
Application #:
12328435
Filing Dt:
12/04/2008
Publication #:
Pub Dt:
06/10/2010
Title:
METHODS OF FABRICATING SUBSTRATES
6
Patent #:
Issue Dt:
08/05/2014
Application #:
12328448
Filing Dt:
12/04/2008
Publication #:
Pub Dt:
06/10/2010
Title:
METHODS OF FABRICATING SUBSTRATES
7
Patent #:
Issue Dt:
08/21/2012
Application #:
12328464
Filing Dt:
12/04/2008
Publication #:
Pub Dt:
06/10/2010
Title:
METHODS OF FABRICATING SUBSTRATES
8
Patent #:
Issue Dt:
12/11/2012
Application #:
12329185
Filing Dt:
12/05/2008
Publication #:
Pub Dt:
06/10/2010
Title:
SEMICONDUCTOR DEVICE STRUCTURES INCLUDING TRANSISTORS WITH ENERGY BARRIERS ADJACENT TO TRANSISTOR CHANNELS AND ASSOCIATED METHODS
9
Patent #:
Issue Dt:
07/29/2014
Application #:
12329740
Filing Dt:
12/08/2008
Publication #:
Pub Dt:
06/10/2010
Title:
Increasing the Spatial Resolution of Dosimetry Sensors
10
Patent #:
Issue Dt:
02/09/2010
Application #:
12329779
Filing Dt:
12/08/2008
Publication #:
Pub Dt:
06/04/2009
Title:
METHOD AND APPARATUS FOR INITIALIZATION OF READ LATENCY TRACKING CIRCUIT IN HIGH-SPEED DRAM
11
Patent #:
Issue Dt:
08/10/2010
Application #:
12329932
Filing Dt:
12/08/2008
Publication #:
Pub Dt:
04/02/2009
Title:
NON-VOLATILE MEMORY WITH BOTH SINGLE AND MULTIPLE LEVEL CELLS
12
Patent #:
Issue Dt:
08/31/2010
Application #:
12330077
Filing Dt:
12/08/2008
Publication #:
Pub Dt:
06/10/2010
Title:
MEMORY CELL SHIFT ESTIMATION METHOD AND APPARATUS
13
Patent #:
Issue Dt:
10/27/2009
Application #:
12330285
Filing Dt:
12/08/2008
Publication #:
Pub Dt:
04/09/2009
Title:
EXTERNAL CLOCK TRACKING PIPELINED LATCH SCHEME
14
Patent #:
Issue Dt:
03/01/2011
Application #:
12331059
Filing Dt:
12/09/2008
Publication #:
Pub Dt:
04/09/2009
Title:
SEMICONDUCTOR CONSTRUCTIONS HAVING MULTIPLE PATTERNED MASKING LAYERS OVER NAND GATE STACKS
15
Patent #:
Issue Dt:
07/28/2015
Application #:
12331772
Filing Dt:
12/10/2008
Publication #:
Pub Dt:
06/10/2010
Title:
Non-Volatile Memory Device Capable of Initiating Transactions
16
Patent #:
Issue Dt:
01/08/2013
Application #:
12332413
Filing Dt:
12/11/2008
Publication #:
Pub Dt:
06/11/2009
Title:
INTEGRATED CIRCUIT HAVING MEMORY CELL ARRAY, AND METHOD OF MANUFACTURING SAME
17
Patent #:
Issue Dt:
07/09/2013
Application #:
12333012
Filing Dt:
12/11/2008
Publication #:
Pub Dt:
06/17/2010
Title:
JFET DEVICE STRUCTURES AND METHODS FOR FABRICATING THE SAME
18
Patent #:
Issue Dt:
01/05/2010
Application #:
12333035
Filing Dt:
12/11/2008
Publication #:
Pub Dt:
04/16/2009
Title:
METHOD AND SYSTEM FOR SELECTING COMPATIBLE PROCESSORS TO ADD TO A MULTIPROCESSOR COMPUTER
19
Patent #:
Issue Dt:
10/02/2012
Application #:
12333067
Filing Dt:
12/11/2008
Publication #:
Pub Dt:
06/17/2010
Title:
LOW POWER MEMORY DEVICE WITH JFET DEVICE STRUCTURES
20
Patent #:
Issue Dt:
11/27/2012
Application #:
12333100
Filing Dt:
12/11/2008
Publication #:
Pub Dt:
06/17/2010
Title:
MULTILEVEL ENCODING WITH ERROR CORRECTION
21
Patent #:
Issue Dt:
01/25/2011
Application #:
12333530
Filing Dt:
12/12/2008
Publication #:
Pub Dt:
06/17/2010
Title:
READING THRESHOLD SWITCHING MEMORY CELLS
22
Patent #:
Issue Dt:
04/26/2011
Application #:
12333560
Filing Dt:
12/12/2008
Publication #:
Pub Dt:
04/02/2009
Title:
METHOD OF MAKING A SEMICONDUCTOR DEVICE HAVING IMPROVED CONTACTS
23
Patent #:
Issue Dt:
01/15/2013
Application #:
12333822
Filing Dt:
12/12/2008
Publication #:
Pub Dt:
06/17/2010
Title:
PARALLEL ENCRYPTION/DECRYPTION
24
Patent #:
Issue Dt:
02/04/2014
Application #:
12336476
Filing Dt:
12/16/2008
Publication #:
Pub Dt:
06/17/2010
Title:
MEMORY WITH GUARD VALUE DEPENDENT ERROR CORRECTION
25
Patent #:
Issue Dt:
03/15/2011
Application #:
12337292
Filing Dt:
12/17/2008
Publication #:
Pub Dt:
04/16/2009
Title:
EPITAXIAL SILICON GROWTH
26
Patent #:
Issue Dt:
05/13/2014
Application #:
12337573
Filing Dt:
12/17/2008
Title:
METHOD AND APPARATUS FOR CONFIGURING WRITE PERFORMANCE FOR ELECTRICALLY WRITABLE MEMORY DEVICES
27
Patent #:
Issue Dt:
01/11/2011
Application #:
12337740
Filing Dt:
12/18/2008
Publication #:
Pub Dt:
07/02/2009
Title:
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE HAVING A FIN-SHAPED CHANNEL
28
Patent #:
Issue Dt:
10/02/2012
Application #:
12338404
Filing Dt:
12/18/2008
Publication #:
Pub Dt:
06/24/2010
Title:
METHOD AND STRUCTURE FOR INTEGRATING CAPACITOR-LESS MEMORY CELL WITH LOGIC
29
Patent #:
Issue Dt:
03/01/2011
Application #:
12338413
Filing Dt:
12/18/2008
Publication #:
Pub Dt:
05/21/2009
Title:
SCALABLE MULTI-FUNCTIONAL AND MULTI-LEVEL NANO-CRYSTAL NON-VOLATILE MEMORY DEVICE
30
Patent #:
Issue Dt:
08/10/2010
Application #:
12339610
Filing Dt:
12/19/2008
Publication #:
Pub Dt:
04/16/2009
Title:
DRAM CELLS WITH VERTICAL TRANSISTORS
31
Patent #:
Issue Dt:
07/05/2011
Application #:
12339935
Filing Dt:
12/19/2008
Publication #:
Pub Dt:
06/24/2010
Title:
WORDLINE TEMPERATURE COMPENSATION
32
Patent #:
Issue Dt:
01/17/2012
Application #:
12341002
Filing Dt:
12/22/2008
Publication #:
Pub Dt:
06/24/2010
Title:
SHALLOW TRENCH ISOLATION FOR A MEMORY
33
Patent #:
Issue Dt:
05/28/2013
Application #:
12341014
Filing Dt:
12/22/2008
Publication #:
Pub Dt:
06/24/2010
Title:
INTEGRATING DIVERSE TRANSISTORS ON THE SAME WAFER
34
Patent #:
Issue Dt:
12/07/2010
Application #:
12341027
Filing Dt:
12/22/2008
Publication #:
Pub Dt:
06/24/2010
Title:
FABRICATING BIPOLAR JUNCTION SELECT TRANSISTORS FOR SEMICONDUCTOR MEMORIES
35
Patent #:
Issue Dt:
07/13/2010
Application #:
12341043
Filing Dt:
12/22/2008
Publication #:
Pub Dt:
04/30/2009
Title:
METHOD FOR OPERATING AN ELECTRONIC DEVICE WITH REDUCED PIN CAPACITANCE
36
Patent #:
Issue Dt:
05/25/2010
Application #:
12342309
Filing Dt:
12/23/2008
Publication #:
Pub Dt:
05/07/2009
Title:
INTERNAL DATA COMPARISON FOR MEMORY TESTING
37
Patent #:
Issue Dt:
07/03/2012
Application #:
12342312
Filing Dt:
12/23/2008
Publication #:
Pub Dt:
06/24/2010
Title:
FORMING ISOLATION REGIONS FOR INTEGRATED CIRCUITS
38
Patent #:
Issue Dt:
03/29/2011
Application #:
12342342
Filing Dt:
12/23/2008
Publication #:
Pub Dt:
06/24/2010
Title:
CONFIGURABLE LATCHING FOR ASYNCHRONOUS MEMORIES
39
Patent #:
Issue Dt:
09/06/2011
Application #:
12343304
Filing Dt:
12/23/2008
Publication #:
Pub Dt:
06/04/2009
Title:
ANTI-ECLIPSING CIRCUIT FOR IMAGE SENSORS
40
Patent #:
Issue Dt:
05/26/2015
Application #:
12343398
Filing Dt:
12/23/2008
Publication #:
Pub Dt:
06/24/2010
Title:
MOLDING COMPOUND INCLUDING A CARBON NANO-TUBE DISPERSION
41
Patent #:
Issue Dt:
11/01/2011
Application #:
12343688
Filing Dt:
12/24/2008
Publication #:
Pub Dt:
07/09/2009
Title:
MULTICAST DATA PACKET SWITCHING METHOD
42
Patent #:
Issue Dt:
07/12/2011
Application #:
12344157
Filing Dt:
12/24/2008
Title:
REWRITABLE SINGLE-BIT-PER-CELL FLASH MEMORY
43
Patent #:
Issue Dt:
01/18/2011
Application #:
12344740
Filing Dt:
12/29/2008
Publication #:
Pub Dt:
06/11/2009
Title:
PIXEL WITH STRAINED SILICON LAYER FOR IMPROVING CARRIER MOBILITY AND BLUE RESPONSE IN IMAGERS
44
Patent #:
Issue Dt:
10/12/2010
Application #:
12345039
Filing Dt:
12/29/2008
Publication #:
Pub Dt:
05/07/2009
Title:
METHODS AND APPARATUS FOR SYNCHRONIZING WITH A CLOCK SIGNAL
45
Patent #:
Issue Dt:
03/23/2010
Application #:
12345245
Filing Dt:
12/29/2008
Publication #:
Pub Dt:
04/30/2009
Title:
DIELECTRIC LAYERS AND MEMORY CELLS INCLUDING METAL-DOPED ALUMINA
46
Patent #:
NONE
Issue Dt:
Application #:
12345306
Filing Dt:
12/29/2008
Publication #:
Pub Dt:
07/01/2010
Title:
METHOD AND APPARATUS TO PROFILE RAM MEMORY OBJECTS FOR DISPLACMENT WITH NONVOLATILE MEMORY
47
Patent #:
Issue Dt:
02/08/2011
Application #:
12345398
Filing Dt:
12/29/2008
Publication #:
Pub Dt:
07/01/2010
Title:
METHOD FOR LOW-STRESS MULTILEVEL READING OF PHASE CHANGE MEMORY CELLS AND MULTILEVEL PHASE CHANGE MEMORY
48
Patent #:
Issue Dt:
01/11/2011
Application #:
12345411
Filing Dt:
12/29/2008
Publication #:
Pub Dt:
07/01/2010
Title:
METHOD FOR LOW POWER ACCESSING A PHASE CHANGE MEMORY DEVICE
49
Patent #:
Issue Dt:
03/08/2011
Application #:
12345436
Filing Dt:
12/29/2008
Publication #:
Pub Dt:
07/01/2010
Title:
AN APPARATUS INCLUDING A FOLLOWER OUTPUT BUFFER HAVING AN OUTPUT IMPEDANCE THAT ADAPTS TO A TRANSMISSION LINE IMPEDANCE
50
Patent #:
Issue Dt:
07/26/2011
Application #:
12345462
Filing Dt:
12/29/2008
Title:
APPARATUS AND METHOD FOR REFRESHING OR TOGGLING A PHASE-CHANGE MEMORY CELL
51
Patent #:
Issue Dt:
09/20/2011
Application #:
12345511
Filing Dt:
12/29/2008
Publication #:
Pub Dt:
07/01/2010
Title:
ERASE COMPLETION RECOGNITION
52
Patent #:
Issue Dt:
09/28/2010
Application #:
12345568
Filing Dt:
12/29/2008
Title:
LITHOGRAPHIC PATTERNING FOR SUB-90NM WITH A MULTI-LAYERED CARBON-BASED HARDMASK
53
Patent #:
Issue Dt:
06/04/2013
Application #:
12346015
Filing Dt:
12/30/2008
Title:
SECONDARY MEMORY ELEMENT FOR NON-VOLATILE MEMORY
54
Patent #:
Issue Dt:
09/14/2010
Application #:
12346227
Filing Dt:
12/30/2008
Publication #:
Pub Dt:
04/23/2009
Title:
MEMORY MODULE, SYSTEM AND METHOD OF MAKING SAME
55
Patent #:
Issue Dt:
02/15/2011
Application #:
12346281
Filing Dt:
12/30/2008
Publication #:
Pub Dt:
04/30/2009
Title:
STRAINED SEMICONDUCTOR, DEVICES AND SYSTEMS AND METHODS OF FORMATION
56
Patent #:
Issue Dt:
10/27/2009
Application #:
12346353
Filing Dt:
12/30/2008
Publication #:
Pub Dt:
04/30/2009
Title:
NON-VOLATILE MULTILEVEL MEMORY CELL PROGRAMMING
57
Patent #:
Issue Dt:
12/11/2012
Application #:
12346363
Filing Dt:
12/30/2008
Title:
METHOD OF FABRICATING A CHARGE TRAP NAND FLASH MEMORY DEVICE
58
Patent #:
Issue Dt:
05/10/2011
Application #:
12346472
Filing Dt:
12/30/2008
Title:
DYNAMIC POLARIZATION FOR REDUCING STRESS INDUCED LEAKAGE CURRENT
59
Patent #:
Issue Dt:
04/19/2011
Application #:
12346542
Filing Dt:
12/30/2008
Publication #:
Pub Dt:
07/01/2010
Title:
VARIABLE MEMORY REFRESH DEVICES AND METHODS
60
Patent #:
Issue Dt:
07/12/2011
Application #:
12346564
Filing Dt:
12/30/2008
Publication #:
Pub Dt:
07/01/2010
Title:
GENERATING A FULL RAIL SIGNAL
61
Patent #:
Issue Dt:
06/21/2011
Application #:
12346566
Filing Dt:
12/30/2008
Publication #:
Pub Dt:
06/04/2009
Title:
FLEXIBLE COLUMN DIE INTERCONNECTS AND STRUCTURES INCLUDING SAME
62
Patent #:
Issue Dt:
03/20/2012
Application #:
12347403
Filing Dt:
12/31/2008
Publication #:
Pub Dt:
07/01/2010
Title:
SYSTEMS, METHODS, AND DEVICES FOR CONFIGURING A DEVICE
63
Patent #:
Issue Dt:
08/21/2012
Application #:
12347510
Filing Dt:
12/31/2008
Title:
ENHANCED THROUGHPUT FOR SERIAL FLASH MEMORY, INCLUDING STREAMING MODE OPERATIONS
64
Patent #:
Issue Dt:
02/19/2013
Application #:
12347623
Filing Dt:
12/31/2008
Title:
EXTENDED ADDRESS MODE FOR SERIAL FLASH MEMORY
65
Patent #:
Issue Dt:
08/07/2012
Application #:
12347721
Filing Dt:
12/31/2008
Publication #:
Pub Dt:
07/01/2010
Title:
METHOD OF HIGH ASPECT RATIO PLUG FILL
66
Patent #:
Issue Dt:
01/01/2013
Application #:
12347738
Filing Dt:
12/31/2008
Publication #:
Pub Dt:
07/01/2010
Title:
MULTI-DIE BUILDING BLOCK FOR STACKED-DIE PACKAGE
67
Patent #:
Issue Dt:
04/27/2010
Application #:
12347786
Filing Dt:
12/31/2008
Title:
METHOD FOR PATTERNING A PHOTO-RESIST IN AN IMMERSION LITHOGRAPHY PROCESS
68
Patent #:
Issue Dt:
04/04/2017
Application #:
12347935
Filing Dt:
12/31/2008
Publication #:
Pub Dt:
07/01/2010
Title:
RECOVERY FOR NON-VOLATILE MEMORY AFTER POWER LOSS
69
Patent #:
Issue Dt:
12/04/2012
Application #:
12347962
Filing Dt:
12/31/2008
Title:
METHOD AND APPARATUS FOR AN ALWAYS OPEN WRITE-ONLY REGISTER BASED MEMORY MAPPED OVERLAY INTERFACE FOR A NONVOLATILE MEMORY
70
Patent #:
Issue Dt:
06/26/2012
Application #:
12348737
Filing Dt:
01/05/2009
Publication #:
Pub Dt:
07/08/2010
Title:
SEMICONDUCTOR DEVICES INCLUDING DUAL GATE STRUCTURES
71
Patent #:
Issue Dt:
01/11/2011
Application #:
12349133
Filing Dt:
01/06/2009
Publication #:
Pub Dt:
06/18/2009
Title:
ENHANCED MULTI-BIT NON-VOLATILE MEMORY DEVICE WITH RESONANT TUNNEL BARRIER
72
Patent #:
Issue Dt:
12/08/2009
Application #:
12349185
Filing Dt:
01/06/2009
Publication #:
Pub Dt:
05/14/2009
Title:
ERASE OPERATION IN A FLASH DRIVE MEMORY
73
Patent #:
Issue Dt:
10/02/2012
Application #:
12350132
Filing Dt:
01/07/2009
Publication #:
Pub Dt:
07/08/2010
Title:
PATTERN-RECOGNITION PROCESSOR WITH MATCHING-DATA REPORTING MODULE
74
Patent #:
NONE
Issue Dt:
Application #:
12350136
Filing Dt:
01/07/2009
Publication #:
Pub Dt:
07/08/2010
Title:
Buses for Pattern-Recognition Processors
75
Patent #:
Issue Dt:
07/03/2012
Application #:
12350142
Filing Dt:
01/07/2009
Publication #:
Pub Dt:
07/08/2010
Title:
METHOD AND SYSTEMS FOR POWER CONSUMPTION MANAGEMENT OF A PATTERN-RECOGNITION PROCESSOR
76
Patent #:
Issue Dt:
04/02/2013
Application #:
12350686
Filing Dt:
01/08/2009
Publication #:
Pub Dt:
07/08/2010
Title:
MEMORY SYSTEM CONTROLLER TO MANAGE WEAR LEVELING ACROSS A PLURALITY OF STORAGE NODES
77
Patent #:
Issue Dt:
07/24/2012
Application #:
12350789
Filing Dt:
01/08/2009
Publication #:
Pub Dt:
07/08/2010
Title:
METHODS OF REMOVING PARTICLES FROM OVER SEMICONDUCTOR SUBSTRATES
78
Patent #:
Issue Dt:
04/08/2014
Application #:
12350831
Filing Dt:
01/08/2009
Publication #:
Pub Dt:
07/08/2010
Title:
OVER-LIMIT ELECTRICAL CONDITION PROTECTION CIRCUITS FOR INTEGRATED CIRCUITS
79
Patent #:
Issue Dt:
06/28/2011
Application #:
12351099
Filing Dt:
01/09/2009
Publication #:
Pub Dt:
07/15/2010
Title:
MEMORY CELLS, METHODS OF FORMING DIELECTRIC MATERIALS, AND METHODS OF FORMING MEMORY CELLS
80
Patent #:
Issue Dt:
12/13/2011
Application #:
12351206
Filing Dt:
01/09/2009
Publication #:
Pub Dt:
07/15/2010
Title:
MEMORY CONTROLLER HAVING FRONT END AND BACK END CHANNELS FOR MODIFYING COMMANDS
81
Patent #:
Issue Dt:
05/22/2012
Application #:
12351556
Filing Dt:
01/09/2009
Publication #:
Pub Dt:
07/15/2010
Title:
TRI-STATE DRIVER CIRCUITS HAVING AUTOMATIC HIGH-IMPEDANCE ENABLING
82
Patent #:
Issue Dt:
03/18/2014
Application #:
12352033
Filing Dt:
01/12/2009
Publication #:
Pub Dt:
05/14/2009
Title:
SYSTEMS AND METHODS FOR PLASMA PROCESSING OF MICROFEATURE WORKPIECES
83
Patent #:
Issue Dt:
04/05/2011
Application #:
12352147
Filing Dt:
01/12/2009
Publication #:
Pub Dt:
05/07/2009
Title:
METHODS AND APPARATUSES RELATING TO AUTOMATIC CELL THRESHOLD VOLTAGE MEASUREMENT
84
Patent #:
Issue Dt:
10/04/2011
Application #:
12352283
Filing Dt:
01/12/2009
Publication #:
Pub Dt:
05/21/2009
Title:
MICROELECTRONIC DEVICE PACKAGES, STACKED MICROELECTRONIC DEVICE PACKAGES, AND METHODS FOR MANUFACTURING MICROELECTRONIC DEVICES
85
Patent #:
Issue Dt:
09/23/2014
Application #:
12352311
Filing Dt:
01/12/2009
Publication #:
Pub Dt:
07/22/2010
Title:
DEVICES, SYSTEMS, AND METHODS FOR COMMUNICATING PATTERN MATCHING RESULTS OF A PARALLEL PATTERN SEARCH ENGINE
86
Patent #:
Issue Dt:
06/07/2011
Application #:
12352364
Filing Dt:
01/12/2009
Publication #:
Pub Dt:
07/15/2010
Title:
MEMORY CELL HAVING NONMAGNETIC FILAMENT CONTACT AND METHODS OF OPERATING AND FABRICATING THE SAME
87
Patent #:
Issue Dt:
10/04/2011
Application #:
12352381
Filing Dt:
01/12/2009
Publication #:
Pub Dt:
07/15/2010
Title:
SYSTEMS AND METHODS FOR MONITORING A MEMORY SYSTEM
88
Patent #:
Issue Dt:
06/04/2013
Application #:
12352402
Filing Dt:
01/12/2009
Publication #:
Pub Dt:
07/15/2010
Title:
MEMORY CELL HAVING DIELECTRIC MEMORY ELEMENT
89
Patent #:
Issue Dt:
09/30/2014
Application #:
12352499
Filing Dt:
01/12/2009
Publication #:
Pub Dt:
05/21/2009
Title:
ADAPTIVE COMMUNICATION INTERFACE
90
Patent #:
Issue Dt:
03/16/2010
Application #:
12352775
Filing Dt:
01/13/2009
Publication #:
Pub Dt:
06/11/2009
Title:
SYSTEMS AND METHODS FOR FORMING METAL OXIDE LAYERS
91
Patent #:
Issue Dt:
02/21/2012
Application #:
12353592
Filing Dt:
01/14/2009
Publication #:
Pub Dt:
06/18/2009
Title:
DRAM WITH NANOFIN TRANSISTORS
92
Patent #:
Issue Dt:
04/19/2011
Application #:
12353661
Filing Dt:
01/14/2009
Publication #:
Pub Dt:
07/15/2010
Title:
MEMORY BANK SIGNAL COUPLING BUFFER AND METHOD
93
Patent #:
Issue Dt:
02/04/2014
Application #:
12353773
Filing Dt:
01/14/2009
Publication #:
Pub Dt:
07/15/2010
Title:
COMPUTER MODULES WITH SMALL THICKNESSES AND ASSOCIATED METHODS OF MANUFACTURING
94
Patent #:
Issue Dt:
08/21/2012
Application #:
12353878
Filing Dt:
01/14/2009
Publication #:
Pub Dt:
07/15/2010
Title:
METHOD FOR DETECTING FLASH PROGRAM FAILURES
95
Patent #:
Issue Dt:
08/07/2012
Application #:
12354059
Filing Dt:
01/15/2009
Publication #:
Pub Dt:
05/14/2009
Title:
ASSEMBLIES AND MULTI-CHIP MODULES INCLUDING STACKED SEMICONDUCTOR DICE HAVING CENTRALLY LOCATED, WIRE BONDED BOND PADS
96
Patent #:
Issue Dt:
05/11/2010
Application #:
12354975
Filing Dt:
01/16/2009
Publication #:
Pub Dt:
05/14/2009
Title:
MEMORY VOLTAGE CYCLE ADJUSTMENT
97
Patent #:
Issue Dt:
09/28/2010
Application #:
12355121
Filing Dt:
01/16/2009
Publication #:
Pub Dt:
05/21/2009
Title:
METHOD AND SYSTEM FOR LOCAL MEMORY ADDRESSING IN SINGLE INSTRUCTION, MULTIPLE DATA COMPUTER SYSTEM
98
Patent #:
NONE
Issue Dt:
Application #:
12355412
Filing Dt:
01/16/2009
Publication #:
Pub Dt:
07/22/2010
Title:
PHOTOLITHOGRAPHY SYSTEMS WITH LOCAL EXPOSURE CORRECTION AND ASSOCIATED METHODS
99
Patent #:
Issue Dt:
03/08/2011
Application #:
12355466
Filing Dt:
01/16/2009
Title:
HIGH IMPEDANCE REFERENCE VOLTAGE DISTRIBUTION
100
Patent #:
Issue Dt:
10/12/2010
Application #:
12355523
Filing Dt:
01/16/2009
Publication #:
Pub Dt:
07/22/2010
Title:
LOCKED LOOPS, BIAS GENERATORS, CHARGE PUMPS AND METHODS FOR GENERATING CONTROL VOLTAGES
Assignor
1
Exec Dt:
06/29/2018
Assignee
1
8000 S. FEDERAL WAY
BOISE, IDAHO 83707
Correspondence name and address
WSGR, C/O QUI LU FLOOD, SENIOR PARALEGAL
ONE MARKET, SPEAR TOWER, SUITE 3300
SAN FRANCISCO, CA 94105

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