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Reel/Frame:047243/0001   Pages: 959
Recorded: 08/23/2018
Attorney Dkt #:4816.238
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
1
Patent #:
Issue Dt:
02/19/2013
Application #:
13308405
Filing Dt:
11/30/2011
Publication #:
Pub Dt:
03/22/2012
Title:
MEMORY WITH INTERLEAVED READ AND REDUNDANT COLUMNS
2
Patent #:
Issue Dt:
12/19/2017
Application #:
13308656
Filing Dt:
12/01/2011
Publication #:
Pub Dt:
06/06/2013
Title:
SOLID STATE TRANSDUCER DEVICES WITH SEPARATELY CONTROLLED REGIONS, AND ASSOCIATED SYSTEMS AND METHODS
3
Patent #:
Issue Dt:
07/16/2013
Application #:
13308976
Filing Dt:
12/01/2011
Publication #:
Pub Dt:
03/22/2012
Title:
REDUCING NOISE IN SEMICONDUCTOR DEVICES
4
Patent #:
Issue Dt:
03/12/2013
Application #:
13309442
Filing Dt:
12/01/2011
Publication #:
Pub Dt:
03/29/2012
Title:
Methods Of Forming Patterns
5
Patent #:
Issue Dt:
04/30/2013
Application #:
13309796
Filing Dt:
12/02/2011
Publication #:
Pub Dt:
03/29/2012
Title:
METHOD AND APPARATUS FOR MANAGING BEHAVIOR OF MEMORY DEVICES
6
Patent #:
Issue Dt:
01/21/2014
Application #:
13310145
Filing Dt:
12/02/2011
Publication #:
Pub Dt:
06/06/2013
Title:
SEMICONDUTOR ISOLATION STRUCTURE
7
Patent #:
Issue Dt:
09/30/2014
Application #:
13310245
Filing Dt:
12/02/2011
Publication #:
Pub Dt:
03/29/2012
Title:
METHOD OF FORMING LUTETIUM AND LANTHANUM DIELECTRIC STRUCTURES
8
Patent #:
Issue Dt:
01/15/2013
Application #:
13311107
Filing Dt:
12/05/2011
Publication #:
Pub Dt:
03/29/2012
Title:
SENSING OF MEMORY CELLS IN NAND FLASH
9
Patent #:
Issue Dt:
10/16/2012
Application #:
13311150
Filing Dt:
12/05/2011
Publication #:
Pub Dt:
03/29/2012
Title:
SYSTEMS CONFIGURED TO IDENTIFY AN OPERATING MODE
10
Patent #:
Issue Dt:
06/04/2013
Application #:
13311218
Filing Dt:
12/05/2011
Publication #:
Pub Dt:
03/29/2012
Title:
APPARATUS CONTAINING COBALT TITANIUM OXIDE
11
Patent #:
Issue Dt:
05/14/2013
Application #:
13311378
Filing Dt:
12/05/2011
Publication #:
Pub Dt:
03/29/2012
Title:
MEMORY INTERLEAVE FOR HETEROGENEOUS COMPUTING
12
Patent #:
Issue Dt:
10/23/2012
Application #:
13311808
Filing Dt:
12/06/2011
Publication #:
Pub Dt:
03/29/2012
Title:
METHOD AND APPARATUS FOR DETECTING COMMUNICATION ERRORS ON A BUS
13
Patent #:
Issue Dt:
09/16/2014
Application #:
13311821
Filing Dt:
12/06/2011
Publication #:
Pub Dt:
03/29/2012
Title:
METHODS, SYSTEMS, AND DEVICES FOR MANAGEMENT OF A MEMORY SYSTEM
14
Patent #:
Issue Dt:
05/07/2013
Application #:
13312074
Filing Dt:
12/06/2011
Title:
METHOD OF CONTROLLING A VERTICAL DUAL-GATE DYNAMIC RANDOM ACCESS MEMORY
15
Patent #:
Issue Dt:
02/04/2014
Application #:
13312383
Filing Dt:
12/06/2011
Publication #:
Pub Dt:
03/29/2012
Title:
ONE-DIMENSIONAL ARRAYS OF BLOCK COPOLYMER CYLINDERS AND APPLICATIONS THEREOF
16
Patent #:
Issue Dt:
02/05/2013
Application #:
13312801
Filing Dt:
12/06/2011
Publication #:
Pub Dt:
05/10/2012
Title:
SEMICONDUCTOR DEVICE COMPRISING TRANSISTOR STRUCTURES AND METHODS FOR FORMING SAME
17
Patent #:
Issue Dt:
11/20/2012
Application #:
13313341
Filing Dt:
12/07/2011
Publication #:
Pub Dt:
03/29/2012
Title:
DIRECT SECONDARY DEVICE INTERFACE BY A HOST
18
Patent #:
Issue Dt:
09/11/2012
Application #:
13313379
Filing Dt:
12/07/2011
Publication #:
Pub Dt:
03/29/2012
Title:
CHARGE LOSS COMPENSATION DURING PROGRAMMING OF A MEMORY DEVICE
19
Patent #:
Issue Dt:
12/24/2013
Application #:
13313566
Filing Dt:
12/07/2011
Publication #:
Pub Dt:
06/13/2013
Title:
METHOD OF MANUFACTURING VERTICAL TRANSISTORS
20
Patent #:
Issue Dt:
10/02/2012
Application #:
13314976
Filing Dt:
12/08/2011
Publication #:
Pub Dt:
04/05/2012
Title:
ISOLATION STRUCTURE FOR A MEMORY CELL USING AL2O3 DIELECTRIC
21
Patent #:
Issue Dt:
03/04/2014
Application #:
13315337
Filing Dt:
12/09/2011
Publication #:
Pub Dt:
04/05/2012
Title:
SHALLOW TRENCH ISOLATION FOR A MEMORY
22
Patent #:
Issue Dt:
10/20/2015
Application #:
13315385
Filing Dt:
12/09/2011
Publication #:
Pub Dt:
04/05/2012
Title:
CHARGE PUMP APPARATUS, A MEMORY INTEGRATED CIRCUIT AND METHODS OF POWER SUPPLY
23
Patent #:
Issue Dt:
06/26/2012
Application #:
13315390
Filing Dt:
12/09/2011
Publication #:
Pub Dt:
04/05/2012
Title:
NON-VOLATILE MEMORY DEVICE HAVING ASSIGNABLE NETWORK IDENTIFICATION
24
Patent #:
Issue Dt:
08/05/2014
Application #:
13316026
Filing Dt:
12/09/2011
Publication #:
Pub Dt:
06/13/2013
Title:
APPARATUSES AND METHODS FOR TRANSPOSING SELECT GATES
25
Patent #:
Issue Dt:
01/28/2014
Application #:
13316133
Filing Dt:
12/09/2011
Publication #:
Pub Dt:
06/13/2013
Title:
MEMORY CELLS HAVING A PLURALITY OF HEATERS
26
Patent #:
Issue Dt:
12/23/2014
Application #:
13316167
Filing Dt:
12/09/2011
Publication #:
Pub Dt:
06/13/2013
Title:
SLEW RATE MODULATION
27
Patent #:
Issue Dt:
02/05/2013
Application #:
13316285
Filing Dt:
12/09/2011
Publication #:
Pub Dt:
04/05/2012
Title:
INPUT-OUTPUT LINE SENSE AMPLIFIER HAVING ADJUSTABLE OUTPUT DRIVE CAPABILITY
28
Patent #:
Issue Dt:
04/30/2013
Application #:
13316300
Filing Dt:
12/09/2011
Publication #:
Pub Dt:
04/05/2012
Title:
METHOD AND SYSTEM FOR PROGRAMMING NON-VOLATILE MEMORY CELLS BASED ON PROGRAMMING OF PROXIMATE MEMORY CELLS
29
Patent #:
Issue Dt:
03/12/2013
Application #:
13323144
Filing Dt:
12/12/2011
Publication #:
Pub Dt:
04/05/2012
Title:
MEMORY FOR ACCESSING MULTIPLE SECTORS OF INFORMATION SUBSTANTIALLY CONCURRENTLY
30
Patent #:
Issue Dt:
09/17/2013
Application #:
13323525
Filing Dt:
12/12/2011
Publication #:
Pub Dt:
05/03/2012
Title:
DATA CELLS AND CONNECTIONS TO DATA CELLS
31
Patent #:
Issue Dt:
03/19/2013
Application #:
13323609
Filing Dt:
12/12/2011
Publication #:
Pub Dt:
04/12/2012
Title:
METHODS OF FORMING TITANIUM SILICON OXIDE
32
Patent #:
Issue Dt:
10/21/2014
Application #:
13323633
Filing Dt:
12/12/2011
Publication #:
Pub Dt:
04/05/2012
Title:
CHARGE TRAPPING DIELECTRIC STRUCTURES
33
Patent #:
Issue Dt:
05/21/2013
Application #:
13323708
Filing Dt:
12/12/2011
Publication #:
Pub Dt:
04/05/2012
Title:
COMMUNICATION METHODS, METHODS OF FORMING AN INTERCONNECT, SIGNAL INTERCONNECTS, INTEGRATED CIRCUIT STRUCTURES, CIRCUITS, AND DATA APPARATUSES
34
Patent #:
Issue Dt:
01/28/2014
Application #:
13323956
Filing Dt:
12/13/2011
Publication #:
Pub Dt:
06/13/2013
Title:
MEMORY CELLS HAVING A PLURALITY OF CONTROL GATES AND MEMORY CELLS HAVING A CONTROL GATE AND A SHIELD
35
Patent #:
Issue Dt:
06/04/2013
Application #:
13324214
Filing Dt:
12/13/2011
Publication #:
Pub Dt:
04/05/2012
Title:
N WELL IMPLANTS TO SEPARATE BLOCKS IN A FLASH MEMORY DEVICE
36
Patent #:
Issue Dt:
05/21/2013
Application #:
13324216
Filing Dt:
12/13/2011
Publication #:
Pub Dt:
04/05/2012
Title:
CROSSLINKABLE GRAFT POLYMER NON-PREFERENTIALLY WETTED BY POLYSTYRENE AND POLYETHYLENE OXIDE
37
Patent #:
Issue Dt:
06/10/2014
Application #:
13324520
Filing Dt:
12/13/2011
Publication #:
Pub Dt:
04/12/2012
Title:
METHODS OF FABRICATING FIN STRUCTURES
38
Patent #:
Issue Dt:
11/04/2014
Application #:
13324877
Filing Dt:
12/13/2011
Publication #:
Pub Dt:
06/13/2013
Title:
MEMORY APPARATUSES, COMPUTER SYSTEMS AND METHODS FOR ORDERING MEMORY RESPONSES
39
Patent #:
Issue Dt:
10/07/2014
Application #:
13326199
Filing Dt:
12/14/2011
Publication #:
Pub Dt:
06/20/2013
Title:
APPARATUSES AND METHODS FOR COMPARING A CURRENT REPRESENTATIVE OF A NUMBER OF FAILING MEMORY CELLS
40
Patent #:
Issue Dt:
05/13/2014
Application #:
13327057
Filing Dt:
12/15/2011
Publication #:
Pub Dt:
06/20/2013
Title:
WIRING CONFIGURATION OF A BUS SYSTEM AND POWER WIRES IN A MEMORY CHIP
41
Patent #:
Issue Dt:
06/11/2013
Application #:
13327157
Filing Dt:
12/15/2011
Publication #:
Pub Dt:
06/20/2013
Title:
SELF-ALIGNED WET ETCHING PROCESS
42
Patent #:
Issue Dt:
02/11/2014
Application #:
13327499
Filing Dt:
12/15/2011
Publication #:
Pub Dt:
06/20/2013
Title:
COUNTER OPERATION IN A STATE MACHINE LATTICE
43
Patent #:
Issue Dt:
11/26/2013
Application #:
13327510
Filing Dt:
12/15/2011
Publication #:
Pub Dt:
06/20/2013
Title:
BOOLEAN LOGIC IN A STATE MACHINE LATTICE
44
Patent #:
Issue Dt:
07/15/2014
Application #:
13327580
Filing Dt:
12/15/2011
Publication #:
Pub Dt:
06/20/2013
Title:
METHODS AND SYSTEMS FOR DETECTION IN A STATE MACHINE
45
Patent #:
Issue Dt:
09/13/2016
Application #:
13327591
Filing Dt:
12/15/2011
Publication #:
Pub Dt:
06/20/2013
Title:
METHODS AND SYSTEMS FOR DATA ANALYSIS IN A STATE MACHINE
46
Patent #:
Issue Dt:
03/25/2014
Application #:
13327623
Filing Dt:
12/15/2011
Publication #:
Pub Dt:
06/20/2013
Title:
METHODS AND SYSTEMS FOR ROUTING IN A STATE MACHINE
47
Patent #:
Issue Dt:
05/06/2014
Application #:
13327673
Filing Dt:
12/15/2011
Publication #:
Pub Dt:
06/20/2013
Title:
READ BIAS MANAGEMENT TO REDUCE READ ERRORS FOR PHASE CHANGE MEMORY
48
Patent #:
Issue Dt:
02/12/2013
Application #:
13329977
Filing Dt:
12/19/2011
Publication #:
Pub Dt:
04/19/2012
Title:
VERTICAL TRANSISTORS
49
Patent #:
Issue Dt:
01/29/2013
Application #:
13329982
Filing Dt:
12/19/2011
Publication #:
Pub Dt:
04/12/2012
Title:
METHODS OF OPERATING MEMORY DEVICES AND ELECTRONIC SYSTEMS HAVING MEMORY DEVICES
50
Patent #:
Issue Dt:
05/14/2013
Application #:
13330041
Filing Dt:
12/19/2011
Publication #:
Pub Dt:
04/12/2012
Title:
METHOD AND APPARATUS FOR IMAGE NOISE REDUCTION USING NOISE MODELS
51
Patent #:
Issue Dt:
03/05/2013
Application #:
13330077
Filing Dt:
12/19/2011
Publication #:
Pub Dt:
04/19/2012
Title:
METHOD AND APPARATUS FOR IMAGE NOISE REDUCTION USING NOISE MODELS
52
Patent #:
Issue Dt:
06/10/2014
Application #:
13330973
Filing Dt:
12/20/2011
Publication #:
Pub Dt:
04/12/2012
Title:
Methods of Forming Patterns in Semiconductor Constructions, Methods of Forming Container Capacitors, and Methods of Forming Reticles Configured for Imprint Lithography
53
Patent #:
Issue Dt:
06/11/2013
Application #:
13331185
Filing Dt:
12/20/2011
Publication #:
Pub Dt:
04/19/2012
Title:
MEMORY ERASE METHODS AND DEVICES
54
Patent #:
Issue Dt:
06/11/2013
Application #:
13331932
Filing Dt:
12/20/2011
Publication #:
Pub Dt:
04/19/2012
Title:
COMMAND LATENCY SYSTEMS AND METHODS
55
Patent #:
Issue Dt:
06/18/2013
Application #:
13332222
Filing Dt:
12/20/2011
Publication #:
Pub Dt:
04/19/2012
Title:
HAFNIUM TANTALUM OXYNITRIDE DIELECTRIC
56
Patent #:
Issue Dt:
06/02/2015
Application #:
13332553
Filing Dt:
12/21/2011
Publication #:
Pub Dt:
04/19/2012
Title:
METHODS, APPARATUS, AND SYSTEMS TO REPAIR MEMORY
57
Patent #:
Issue Dt:
02/03/2015
Application #:
13332816
Filing Dt:
12/21/2011
Publication #:
Pub Dt:
06/27/2013
Title:
Methods Of Forming Capacitors
58
Patent #:
Issue Dt:
07/02/2013
Application #:
13333245
Filing Dt:
12/21/2011
Publication #:
Pub Dt:
04/19/2012
Title:
METHOD OF FORMING AN IMAGING DEVICE
59
Patent #:
Issue Dt:
11/12/2013
Application #:
13333822
Filing Dt:
12/21/2011
Publication #:
Pub Dt:
06/27/2013
Title:
SYSTEMS, CIRCUITS, AND METHODS FOR CHARGE SHARING
60
Patent #:
Issue Dt:
08/27/2013
Application #:
13333850
Filing Dt:
12/21/2011
Publication #:
Pub Dt:
06/27/2013
Title:
METHODS, APPARATUSES, AND CIRCUITS FOR BIMODAL DISABLE CIRCUITS
61
Patent #:
Issue Dt:
07/21/2015
Application #:
13334339
Filing Dt:
12/22/2011
Publication #:
Pub Dt:
04/19/2012
Title:
TWO-PART PROGRAMMING METHODS
62
Patent #:
Issue Dt:
03/11/2014
Application #:
13335107
Filing Dt:
12/22/2011
Publication #:
Pub Dt:
05/31/2012
Title:
SEMICONDUCTOR STRUCTURES INCLUDING POLYMER MATERIAL PERMEATED WITH METAL OXIDE
63
Patent #:
Issue Dt:
03/24/2015
Application #:
13335291
Filing Dt:
12/22/2011
Publication #:
Pub Dt:
06/27/2013
Title:
Apparatus and Methods of Programming Memory Cells using Adjustable Charge State Level(s)
64
Patent #:
Issue Dt:
08/05/2014
Application #:
13335309
Filing Dt:
12/22/2011
Publication #:
Pub Dt:
06/27/2013
Title:
METHODS AND APPARATUSES FOR DETERMINING THRESHOLD VOLTAGE SHIFT
65
Patent #:
Issue Dt:
12/08/2015
Application #:
13335619
Filing Dt:
12/22/2011
Publication #:
Pub Dt:
04/19/2012
Title:
PASS-THROUGH 3D INTERCONNECT FOR MICROELECTRONIC DIES AND ASSOCIATED SYSTEMS AND METHODS
66
Patent #:
Issue Dt:
07/29/2014
Application #:
13335814
Filing Dt:
12/22/2011
Publication #:
Pub Dt:
06/27/2013
Title:
APPARATUSES AND METHODS INCLUDING MEMORY WITH TOP AND BOTTOM DATA LINES
67
Patent #:
Issue Dt:
08/06/2013
Application #:
13336516
Filing Dt:
12/23/2011
Publication #:
Pub Dt:
05/03/2012
Title:
METHOD OF MANUFACTURING DEVICES HAVING VERTICAL JUNCTION EDGE
68
Patent #:
Issue Dt:
02/25/2014
Application #:
13336805
Filing Dt:
12/23/2011
Publication #:
Pub Dt:
04/19/2012
Title:
TECHNIQUES FOR READING A MEMORY CELL WITH ELECTRICALLY FLOATING BODY TRANSISTOR
69
Patent #:
Issue Dt:
04/02/2013
Application #:
13337567
Filing Dt:
12/27/2011
Publication #:
Pub Dt:
04/19/2012
Title:
Registered Structure Formation via the Application of Directed Thermal Energy to Diblock Copolymer Films
70
Patent #:
Issue Dt:
03/25/2014
Application #:
13337810
Filing Dt:
12/27/2011
Publication #:
Pub Dt:
06/27/2013
Title:
VERTICAL TRANSISTOR STRUCTURE AND METHOD OF MANUFACTURING SAME
71
Patent #:
Issue Dt:
06/10/2014
Application #:
13337943
Filing Dt:
12/27/2011
Publication #:
Pub Dt:
04/19/2012
Title:
MICROELECTRONIC DEVICES AND METHODS FOR FILING VIAS IN MICROELECTRONIC DEVICES
72
Patent #:
Issue Dt:
05/28/2013
Application #:
13338484
Filing Dt:
12/28/2011
Publication #:
Pub Dt:
04/26/2012
Title:
METHODS OF FORMING SILICON OXIDES AND METHODS OF FORMING INTERLEVEL DIELECTRICS
73
Patent #:
Issue Dt:
07/30/2013
Application #:
13338527
Filing Dt:
12/28/2011
Publication #:
Pub Dt:
04/26/2012
Title:
Capacitors Including Conductive TiOxNx
74
Patent #:
Issue Dt:
09/10/2013
Application #:
13339692
Filing Dt:
12/29/2011
Publication #:
Pub Dt:
04/26/2012
Title:
Methods of Forming Capacitors
75
Patent #:
Issue Dt:
02/03/2015
Application #:
13339721
Filing Dt:
12/29/2011
Publication #:
Pub Dt:
07/04/2013
Title:
SHARING LOCAL CONTROL LINES ACROSS MULTIPLE PLANES IN A MEMORY DEVICE
76
Patent #:
Issue Dt:
09/15/2015
Application #:
13340375
Filing Dt:
12/29/2011
Publication #:
Pub Dt:
07/04/2013
Title:
Memory Structures and Arrays
77
Patent #:
Issue Dt:
04/16/2013
Application #:
13341418
Filing Dt:
12/30/2011
Publication #:
Pub Dt:
07/19/2012
Title:
SEAMLESS COARSE AND FINE DELAY STRUCTURE FOR HIGH PERFORMANCE DLL
78
Patent #:
Issue Dt:
02/26/2013
Application #:
13341512
Filing Dt:
12/30/2011
Publication #:
Pub Dt:
04/26/2012
Title:
CMOS IMAGER WITH INTEGRATED CIRCUITRY
79
Patent #:
Issue Dt:
03/11/2014
Application #:
13342826
Filing Dt:
01/03/2012
Publication #:
Pub Dt:
06/14/2012
Title:
BOOT BLOCK FEATURES IN SYNCHRONOUS SERIAL INTERFACE NAND
80
Patent #:
Issue Dt:
09/09/2014
Application #:
13342844
Filing Dt:
01/03/2012
Publication #:
Pub Dt:
04/26/2012
Title:
QUANTIZING CIRCUITS WITH VARIABLE PARAMETERS
81
Patent #:
Issue Dt:
07/02/2013
Application #:
13342876
Filing Dt:
01/03/2012
Publication #:
Pub Dt:
04/26/2012
Title:
METHODS AND APPARATUS FOR A STACKED-DIE INTERPOSER
82
Patent #:
Issue Dt:
12/17/2013
Application #:
13343023
Filing Dt:
01/04/2012
Publication #:
Pub Dt:
05/03/2012
Title:
NON-VOLATILE MULTILEVEL MEMORY CELLS
83
Patent #:
Issue Dt:
12/09/2014
Application #:
13343087
Filing Dt:
01/04/2012
Publication #:
Pub Dt:
07/04/2013
Title:
SOURCE/DRAIN ZONES WITH A DELECTRIC PLUG OVER AN ISOLATION REGION BETWEEN ACTIVE REGIONS AND METHODS
84
Patent #:
Issue Dt:
08/16/2016
Application #:
13344226
Filing Dt:
01/05/2012
Publication #:
Pub Dt:
07/11/2013
Title:
SOLID-STATE RADIATION TRANSDUCER DEVICES HAVING AT LEAST PARTIALLY TRANSPARENT BURIED-CONTACT ELEMENTS, AND ASSOCIATED SYSTEMS AND METHODS
85
Patent #:
Issue Dt:
11/06/2012
Application #:
13344329
Filing Dt:
01/05/2012
Publication #:
Pub Dt:
05/03/2012
Title:
METHOD OF FABRICATING DIFFERENT GATE OXIDES FOR DIFFERENT TRANSISTORS IN AN INTEGRATED CIRCUIT
86
Patent #:
Issue Dt:
12/04/2012
Application #:
13345379
Filing Dt:
01/06/2012
Publication #:
Pub Dt:
05/03/2012
Title:
METHOD AND APPARATUS FOR SENDING DATA FROM MULTIPLE SOURCES OVER A COMMUNICATIONS BUS
87
Patent #:
Issue Dt:
11/04/2014
Application #:
13345417
Filing Dt:
01/06/2012
Publication #:
Pub Dt:
04/26/2012
Title:
MULTI-RESISTIVE INTEGRATED CIRCUIT MEMORY
88
Patent #:
Issue Dt:
09/01/2015
Application #:
13345422
Filing Dt:
01/06/2012
Publication #:
Pub Dt:
07/11/2013
Title:
INTEGRATED CIRCUIT CONSTRUCTIONS HAVING THROUGH SUBSTRATE VIAS AND METHODS OF FORMING INTEGRATED CIRCUIT CONSTRUCTIONS HAVING THROUGH SUBSTRATE VIAS
89
Patent #:
Issue Dt:
08/12/2014
Application #:
13345446
Filing Dt:
01/06/2012
Publication #:
Pub Dt:
05/03/2012
Title:
ELECTRONIC DEVICE WITH ASYMMETRIC GATE STRAIN
90
Patent #:
Issue Dt:
07/22/2014
Application #:
13345530
Filing Dt:
01/06/2012
Publication #:
Pub Dt:
05/10/2012
Title:
LOW POWER, HASH-CONTENT ADDRESSABLE MEMORY ARCHITECTURE
91
Patent #:
Issue Dt:
10/16/2012
Application #:
13345896
Filing Dt:
01/09/2012
Publication #:
Pub Dt:
05/03/2012
Title:
PROGRAMMING ERROR CORRECTION CODE INTO A SOLID STATE MEMORY DEVICE WITH VARYING BITS PER CELL
92
Patent #:
Issue Dt:
03/19/2013
Application #:
13345984
Filing Dt:
01/09/2012
Publication #:
Pub Dt:
05/03/2012
Title:
ELECTRONIC APPARATUS CONTAINING LANTHANIDE YTTRIUM ALUMINUM OXIDE
93
Patent #:
Issue Dt:
06/24/2014
Application #:
13346076
Filing Dt:
01/09/2012
Title:
INTEGRATED CIRCUIT DICE WITH EDGE FINISHING
94
Patent #:
Issue Dt:
04/16/2013
Application #:
13346115
Filing Dt:
01/09/2012
Publication #:
Pub Dt:
05/03/2012
Title:
SYSTEMS AND METHODS FOR ERASING A MEMORY
95
Patent #:
Issue Dt:
10/16/2012
Application #:
13346290
Filing Dt:
01/09/2012
Publication #:
Pub Dt:
05/03/2012
Title:
MACRO AND COMMAND EXECUTION FROM MEMORY ARRAY
96
Patent #:
Issue Dt:
08/06/2013
Application #:
13346402
Filing Dt:
01/09/2012
Publication #:
Pub Dt:
05/03/2012
Title:
STACKED MICROELECTRONIC DEVICES AND METHODS FOR MANUFACTURING STACKED MICROELECTRONIC DEVICES
97
Patent #:
Issue Dt:
12/03/2013
Application #:
13346495
Filing Dt:
01/09/2012
Publication #:
Pub Dt:
07/11/2013
Title:
VERTICAL SOLID-STATE TRANSDUCERS AND SOLID-STATE TRANSDUCER ARRAYS HAVING BACKSIDE TERMINALS AND ASSOCIATED SYSTEMS AND METHODS
98
Patent #:
Issue Dt:
01/15/2013
Application #:
13346538
Filing Dt:
01/09/2012
Publication #:
Pub Dt:
05/03/2012
Title:
ERROR SCANNING IN FLASH MEMORY
99
Patent #:
Issue Dt:
11/13/2012
Application #:
13347054
Filing Dt:
01/10/2012
Publication #:
Pub Dt:
05/17/2012
Title:
MEMORY BLOCK MANAGEMENT
100
Patent #:
NONE
Issue Dt:
Application #:
13347192
Filing Dt:
01/10/2012
Publication #:
Pub Dt:
05/03/2012
Title:
HIGH ASPECT RATIO CONTACTS
Assignor
1
Exec Dt:
06/29/2018
Assignee
1
8000 S. FEDERAL WAY
BOISE, IDAHO 83707
Correspondence name and address
WSGR, C/O QUI LU FLOOD, SENIOR PARALEGAL
ONE MARKET, SPEAR TOWER, SUITE 3300
SAN FRANCISCO, CA 94105

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