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Reel/Frame:047243/0001   Pages: 959
Recorded: 08/23/2018
Attorney Dkt #:4816.238
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
1
Patent #:
Issue Dt:
04/21/2015
Application #:
13624272
Filing Dt:
09/21/2012
Publication #:
Pub Dt:
03/27/2014
Title:
ETCHING POLYSILICON
2
Patent #:
Issue Dt:
08/18/2015
Application #:
13624627
Filing Dt:
09/21/2012
Publication #:
Pub Dt:
03/27/2014
Title:
METHOD, SYSTEM AND DEVICE FOR RECESSED CONTACT IN MEMORY ARRAY
3
Patent #:
Issue Dt:
09/30/2014
Application #:
13625104
Filing Dt:
09/24/2012
Publication #:
Pub Dt:
03/27/2014
Title:
POWER CONSUMPTION CONTROL
4
Patent #:
Issue Dt:
04/08/2014
Application #:
13627915
Filing Dt:
09/26/2012
Publication #:
Pub Dt:
01/24/2013
Title:
MULTILEVEL ENCODING WITH ERROR CORRECTION
5
Patent #:
Issue Dt:
12/30/2014
Application #:
13631068
Filing Dt:
09/28/2012
Publication #:
Pub Dt:
04/03/2014
Title:
Patterned Bases, and Patterning Methods
6
Patent #:
Issue Dt:
11/12/2013
Application #:
13632797
Filing Dt:
10/01/2012
Publication #:
Pub Dt:
01/31/2013
Title:
STACKED MEMORY DEVICES, SYSTEMS, AND METHODS
7
Patent #:
Issue Dt:
11/05/2013
Application #:
13633158
Filing Dt:
10/02/2012
Publication #:
Pub Dt:
01/24/2013
Title:
PROGRAMMING ERROR CORRECTION CODE INTO A SOLID STATE MEMORY DEVICE WITH VARYING BITS PER CELL
8
Patent #:
Issue Dt:
10/14/2014
Application #:
13644510
Filing Dt:
10/04/2012
Publication #:
Pub Dt:
04/10/2014
Title:
APPARATUSES AND METHODS FOR SENSING FUSE STATES
9
Patent #:
Issue Dt:
07/21/2015
Application #:
13646131
Filing Dt:
10/05/2012
Publication #:
Pub Dt:
04/10/2014
Title:
METHODS OF FORMING AN ARRAY OF OPENINGS IN A SUBSTRATE, AND RELATED METHODS OF FORMING A SEMICONDUCTOR DEVICE STRUCTURE
10
Patent #:
Issue Dt:
07/14/2015
Application #:
13646307
Filing Dt:
10/05/2012
Publication #:
Pub Dt:
04/10/2014
Title:
DEVICES, SYSTEMS, AND METHODS RELATED TO REMOVING PARASITIC CONDUCTION IN SEMICONDUCTOR DEVICES
11
Patent #:
Issue Dt:
10/29/2013
Application #:
13647153
Filing Dt:
10/08/2012
Publication #:
Pub Dt:
02/07/2013
Title:
META PREDICTOR RESTORATION UPON DETECTING MISPREDICTION
12
Patent #:
Issue Dt:
03/07/2017
Application #:
13647179
Filing Dt:
10/08/2012
Publication #:
Pub Dt:
04/10/2014
Title:
REDUCING PROGRAMMING DISTURBANCE IN MEMORY DEVICES
13
Patent #:
Issue Dt:
08/04/2015
Application #:
13647527
Filing Dt:
10/09/2012
Publication #:
Pub Dt:
04/10/2014
Title:
DRIFT ACCELERATION IN RESISTANCE VARIABLE MEMORY
14
Patent #:
Issue Dt:
04/04/2017
Application #:
13649822
Filing Dt:
10/11/2012
Publication #:
Pub Dt:
04/17/2014
Title:
UPDATING RELIABILITY DATA WITH A VARIABLE NODE AND CHECK NODES
15
Patent #:
Issue Dt:
11/25/2014
Application #:
13649886
Filing Dt:
10/11/2012
Publication #:
Pub Dt:
04/17/2014
Title:
SENSING DATA STORED IN MEMORY
16
Patent #:
Issue Dt:
01/12/2016
Application #:
13651093
Filing Dt:
10/12/2012
Publication #:
Pub Dt:
04/17/2014
Title:
APPARATUSES, CIRCUITS, AND METHODS FOR BIASING SIGNAL LINES
17
Patent #:
Issue Dt:
11/17/2015
Application #:
13651149
Filing Dt:
10/12/2012
Publication #:
Pub Dt:
04/17/2014
Title:
MEMORY DEVICE ARCHITECTURE
18
Patent #:
Issue Dt:
11/18/2014
Application #:
13651234
Filing Dt:
10/12/2012
Publication #:
Pub Dt:
04/17/2014
Title:
INTERCONNECTION FOR MEMORY ELECTRODES
19
Patent #:
Issue Dt:
04/22/2014
Application #:
13651834
Filing Dt:
10/15/2012
Publication #:
Pub Dt:
02/14/2013
Title:
DATA TRANSFER MANAGEMENT
20
Patent #:
Issue Dt:
09/24/2013
Application #:
13651931
Filing Dt:
10/15/2012
Publication #:
Pub Dt:
02/14/2013
Title:
MACRO AND COMMAND EXECUTION FROM MEMORY ARRAY
21
Patent #:
Issue Dt:
10/14/2014
Application #:
13652033
Filing Dt:
10/15/2012
Publication #:
Pub Dt:
04/17/2014
Title:
DEVICES, SYSTEMS, AND METHODS RELATED TO FORMING THROUGH-SUBSTRATE VIAS WITH SACRIFICIAL PLUGS
22
Patent #:
Issue Dt:
12/10/2013
Application #:
13652108
Filing Dt:
10/15/2012
Publication #:
Pub Dt:
02/14/2013
Title:
MULTIPLE DEVICE APPARATUS, SYSTEMS, AND METHODS
23
Patent #:
Issue Dt:
01/14/2014
Application #:
13652286
Filing Dt:
10/15/2012
Title:
Memory Cells
24
Patent #:
Issue Dt:
02/24/2015
Application #:
13652305
Filing Dt:
10/15/2012
Publication #:
Pub Dt:
04/17/2014
Title:
METHODS OF FORMING GATED DEVICES
25
Patent #:
Issue Dt:
06/25/2013
Application #:
13652957
Filing Dt:
10/16/2012
Publication #:
Pub Dt:
03/28/2013
Title:
SPIN TORQUE TRANSFER MEMORY CELL STRUCTURES AND METHODS
26
Patent #:
Issue Dt:
01/21/2014
Application #:
13654258
Filing Dt:
10/17/2012
Title:
METHODS OF FORMING A MEMORY CELL HAVING PROGRAMMABLE MATERIAL THAT COMPRISES A MULTIVALENT METAL OXIDE PORTION AND AN OXYGEN CONTAINING DIELECTRIC PORTION
27
Patent #:
NONE
Issue Dt:
Application #:
13657381
Filing Dt:
10/22/2012
Publication #:
Pub Dt:
02/21/2013
Title:
DEVICES AND METHODS TO IMPROVE CARRIER MOBILITY
28
Patent #:
Issue Dt:
12/15/2015
Application #:
13657444
Filing Dt:
10/22/2012
Publication #:
Pub Dt:
04/24/2014
Title:
APPARATUSES AND METHODS AND FOR PROVIDING POWER RESPONSIVE TO A POWER LOSS
29
Patent #:
Issue Dt:
08/19/2014
Application #:
13657487
Filing Dt:
10/22/2012
Publication #:
Pub Dt:
02/21/2013
Title:
VERTICALLY STACKED FIN TRANSISTORS AND METHODS OF FABRICATING AND OPERATING THE SAME
30
Patent #:
Issue Dt:
01/05/2016
Application #:
13658519
Filing Dt:
10/23/2012
Publication #:
Pub Dt:
04/24/2014
Title:
Memory Programming Methods And Memory Systems
31
Patent #:
Issue Dt:
03/03/2015
Application #:
13658617
Filing Dt:
10/23/2012
Title:
MULTISTAGE DEVELOPMENT WORKFLOW FOR GENERATING A CUSTOM INSTRUCTION SET RECONFIGURABLE PROCESSOR
32
Patent #:
Issue Dt:
05/20/2014
Application #:
13658691
Filing Dt:
10/23/2012
Publication #:
Pub Dt:
04/24/2014
Title:
MEMORY CONSTRUCTIONS COMPRISING THIN FILMS OF PHASE CHANGE MATERIAL
33
Patent #:
Issue Dt:
10/14/2014
Application #:
13659790
Filing Dt:
10/24/2012
Publication #:
Pub Dt:
03/07/2013
Title:
Methods of Lithographically Patterning a Substrate
34
Patent #:
Issue Dt:
12/16/2014
Application #:
13660768
Filing Dt:
10/25/2012
Publication #:
Pub Dt:
05/01/2014
Title:
APPARATUSES AND METHODS FOR CAPTURING DATA IN A MEMORY
35
Patent #:
Issue Dt:
06/02/2015
Application #:
13660860
Filing Dt:
10/25/2012
Publication #:
Pub Dt:
05/01/2014
Title:
PATTERNING METHODS AND METHODS OF FORMING ELECTRICALLY CONDUCTIVE LINES
36
Patent #:
Issue Dt:
04/19/2016
Application #:
13661321
Filing Dt:
10/26/2012
Publication #:
Pub Dt:
05/01/2014
Title:
PARTIAL PAGE MEMORY OPERATIONS
37
Patent #:
Issue Dt:
07/28/2015
Application #:
13661498
Filing Dt:
10/26/2012
Publication #:
Pub Dt:
05/01/2014
Title:
MULTIPLE DATA LINE MEMORY AND METHODS
38
Patent #:
Issue Dt:
12/30/2014
Application #:
13663915
Filing Dt:
10/30/2012
Publication #:
Pub Dt:
05/01/2014
Title:
LOW MARGIN READ OPERATION WITH CRC COMPARISION
39
Patent #:
Issue Dt:
11/05/2013
Application #:
13667414
Filing Dt:
11/02/2012
Publication #:
Pub Dt:
03/07/2013
Title:
METHODS, DEVICES, AND SYSTEMS FOR DEALING WITH THRESHOLD VOLTAGE CHANGE IN MEMORY DEVICES
40
Patent #:
Issue Dt:
07/07/2015
Application #:
13667649
Filing Dt:
11/02/2012
Publication #:
Pub Dt:
05/08/2014
Title:
MEMORY ARRAYS WITH A MEMORY CELL ADJACENT TO A SMALLER SIZE OF A PILLAR HAVING A GREATER CHANNEL LENGTH THAN A MEMORY CELL ADJACENT TO A LARGER SIZE OF THE PILLAR AND METHODS
41
Patent #:
Issue Dt:
01/14/2014
Application #:
13670209
Filing Dt:
11/06/2012
Publication #:
Pub Dt:
03/14/2013
Title:
PILLARS FOR VERTICAL TRANSISTORS
42
Patent #:
Issue Dt:
04/24/2018
Application #:
13670222
Filing Dt:
11/06/2012
Publication #:
Pub Dt:
05/08/2014
Title:
APPARATUSES AND METHODS FOR DUTY CYCLE ADJUSTMENT
43
Patent #:
Issue Dt:
10/29/2013
Application #:
13672018
Filing Dt:
11/08/2012
Publication #:
Pub Dt:
03/21/2013
Title:
MEMORY DEVICE HAVING DATA PATHS FACILITATING ARRAY/CONTACT CONSOLIDATION AND/OR SWAPPING
44
Patent #:
Issue Dt:
02/21/2017
Application #:
13672433
Filing Dt:
11/08/2012
Publication #:
Pub Dt:
05/08/2014
Title:
ERROR CORRECTION METHODS AND APPARATUSES USING FIRST AND SECOND DECODERS
45
Patent #:
Issue Dt:
08/11/2015
Application #:
13672460
Filing Dt:
11/08/2012
Publication #:
Pub Dt:
05/08/2014
Title:
METHODS OF FORMING SEMICONDUCTOR STRUCTURES WITH SULFUR DIOXIDE ETCH CHEMISTRIES
46
Patent #:
Issue Dt:
12/22/2015
Application #:
13673130
Filing Dt:
11/09/2012
Publication #:
Pub Dt:
03/14/2013
Title:
STT-MRAM CELL STRUCTURE INCORPORATING PIEZOELECTRIC STRESS MATERIAL
47
Patent #:
Issue Dt:
07/01/2014
Application #:
13673141
Filing Dt:
11/09/2012
Publication #:
Pub Dt:
03/14/2013
Title:
MEMORY CELL HAVING NONMAGNETIC FILAMENT CONTACT AND METHODS OF OPERATING AND FABRICATING THE SAME
48
Patent #:
Issue Dt:
09/24/2013
Application #:
13674159
Filing Dt:
11/12/2012
Publication #:
Pub Dt:
03/14/2013
Title:
RECESSED ACCESS DEVICE FOR A MEMORY
49
Patent #:
Issue Dt:
05/10/2016
Application #:
13674254
Filing Dt:
11/12/2012
Publication #:
Pub Dt:
03/21/2013
Title:
METHOD OF FORMING CONTACTS FOR A MEMORY DEVICE
50
Patent #:
Issue Dt:
03/31/2015
Application #:
13674535
Filing Dt:
11/12/2012
Publication #:
Pub Dt:
03/21/2013
Title:
SYSTEMS AND METHODS FOR LOWERING INTERCONNECT CAPACITANCE
51
Patent #:
Issue Dt:
07/30/2013
Application #:
13674674
Filing Dt:
11/12/2012
Publication #:
Pub Dt:
03/21/2013
Title:
METHODS OF FORMING DOPED REGIONS IN SEMICONDUCTOR SUBSTRATES
52
Patent #:
Issue Dt:
05/30/2017
Application #:
13675458
Filing Dt:
11/13/2012
Publication #:
Pub Dt:
05/12/2016
Title:
SPIN TORQUE TRANSFER MEMORY CELL STRUCTURES AND METHODS
53
Patent #:
Issue Dt:
06/03/2014
Application #:
13675523
Filing Dt:
11/13/2012
Publication #:
Pub Dt:
07/18/2013
Title:
MICROELECTRONIC DEVICES AND METHODS FOR MANUFACTURING MICROELECTRONIC DEVICES
54
Patent #:
Issue Dt:
03/25/2014
Application #:
13675870
Filing Dt:
11/13/2012
Publication #:
Pub Dt:
03/21/2013
Title:
ERROR DETECTION/CORRECTION BASED MEMORY MANAGEMENT
55
Patent #:
Issue Dt:
11/03/2015
Application #:
13675933
Filing Dt:
11/13/2012
Publication #:
Pub Dt:
05/15/2014
Title:
SEMICONDUCTOR CONSTRUCTIONS
56
Patent #:
Issue Dt:
09/29/2015
Application #:
13676407
Filing Dt:
11/14/2012
Publication #:
Pub Dt:
03/21/2013
Title:
MEMORY ARRAY WITH A PAIR OF MEMORY-CELL STRINGS TO A SINGLE CONDUCTIVE PILLAR
57
Patent #:
Issue Dt:
11/19/2013
Application #:
13677771
Filing Dt:
11/15/2012
Publication #:
Pub Dt:
03/21/2013
Title:
COMBINED PARALLEL/SERIAL STATUS REGISTER READ
58
Patent #:
Issue Dt:
05/20/2014
Application #:
13678934
Filing Dt:
11/16/2012
Publication #:
Pub Dt:
03/28/2013
Title:
DATA RECOVERY IN A SOLID STATE STORAGE SYSTEM
59
Patent #:
Issue Dt:
02/24/2015
Application #:
13680908
Filing Dt:
11/19/2012
Publication #:
Pub Dt:
03/28/2013
Title:
MEMORY CONTROLLER SUPPORTING RATE-COMPATIBLE PUNCTURED CODES AND SUPPORTING BLOCK CODES
60
Patent #:
Issue Dt:
07/01/2014
Application #:
13682019
Filing Dt:
11/20/2012
Publication #:
Pub Dt:
03/28/2013
Title:
SURFACE DEPRESSIONS FOR DIE-TO-DIE INTERCONNECTS AND ASSOCIATED SYSTEMS AND METHODS
61
Patent #:
Issue Dt:
08/05/2014
Application #:
13682190
Filing Dt:
11/20/2012
Publication #:
Pub Dt:
05/22/2014
Title:
TRANSISTORS, MEMORY CELLS AND SEMICONDUCTOR CONSTRUCTIONS
62
Patent #:
Issue Dt:
12/17/2013
Application #:
13683313
Filing Dt:
11/21/2012
Publication #:
Pub Dt:
03/28/2013
Title:
CONTROL OF INPUTS TO A MEMORY DEVICE
63
Patent #:
Issue Dt:
04/18/2017
Application #:
13683418
Filing Dt:
11/21/2012
Publication #:
Pub Dt:
05/22/2014
Title:
METHODS FOR FORMING NARROW VERTICAL PILLARS AND INTEGRATED CIRCUIT DEVICES HAVING THE SAME
64
Patent #:
Issue Dt:
03/17/2015
Application #:
13683440
Filing Dt:
11/21/2012
Publication #:
Pub Dt:
05/22/2014
Title:
SHAPING CODES FOR MEMORY
65
Patent #:
Issue Dt:
07/23/2013
Application #:
13684919
Filing Dt:
11/26/2012
Publication #:
Pub Dt:
03/28/2013
Title:
NON-VOLATILE MEMORY WITH EXTENDED ERROR CORRECTION PROTECTION
66
Patent #:
Issue Dt:
12/31/2013
Application #:
13685402
Filing Dt:
11/26/2012
Publication #:
Pub Dt:
04/04/2013
Title:
METHODS OF FORMING DIODES
67
Patent #:
Issue Dt:
02/23/2016
Application #:
13686107
Filing Dt:
11/27/2012
Publication #:
Pub Dt:
04/04/2013
Title:
Selective Metal Deposition Over Dielectric Layers
68
Patent #:
Issue Dt:
11/26/2013
Application #:
13686438
Filing Dt:
11/27/2012
Publication #:
Pub Dt:
04/04/2013
Title:
MEMORY DEVICE INTERFACE METHODS, APPARATUS, AND SYSTEMS
69
Patent #:
Issue Dt:
10/07/2014
Application #:
13686487
Filing Dt:
11/27/2012
Publication #:
Pub Dt:
04/04/2013
Title:
LIFETIME MARKERS FOR MEMORY DEVICES
70
Patent #:
Issue Dt:
03/11/2014
Application #:
13686488
Filing Dt:
11/27/2012
Publication #:
Pub Dt:
04/04/2013
Title:
MEMORY WITH WEIGHTED MULTI-PAGE READ
71
Patent #:
Issue Dt:
04/22/2014
Application #:
13686649
Filing Dt:
11/27/2012
Publication #:
Pub Dt:
04/04/2013
Title:
MICROELECTRONIC DEVICES HAVING INTERMEDIATE CONTACTS FOR CONNECTION TO INTERPOSER SUBSTRATES, AND ASSOCIATED METHODS OF PACKAGING MICROELECTRONIC DEVICES WITH INTERMEDIATE CONTACTS
72
Patent #:
Issue Dt:
08/02/2016
Application #:
13687706
Filing Dt:
11/28/2012
Publication #:
Pub Dt:
05/29/2014
Title:
MATCHING SEMICONDUCTOR CIRCUITS
73
Patent #:
Issue Dt:
12/29/2015
Application #:
13687726
Filing Dt:
11/28/2012
Publication #:
Pub Dt:
04/11/2013
Title:
METHOD OF FABRICATING A CHARGE TRAP NAND FLASH MEMORY DEVICE
74
Patent #:
Issue Dt:
10/13/2015
Application #:
13689144
Filing Dt:
11/29/2012
Publication #:
Pub Dt:
05/29/2014
Title:
ADHESIVES INCLUDING A FILLER MATERIAL AND RELATED METHODS
75
Patent #:
Issue Dt:
02/09/2016
Application #:
13689386
Filing Dt:
11/29/2012
Publication #:
Pub Dt:
05/29/2014
Title:
METHODS AND APPARATUSES FOR COMPENSATING FOR SOURCE VOLTAGE
76
Patent #:
Issue Dt:
01/26/2016
Application #:
13689442
Filing Dt:
11/29/2012
Publication #:
Pub Dt:
05/29/2014
Title:
SEMICONDUCTOR DEVICES AND FABRICATION METHODS
77
Patent #:
Issue Dt:
10/28/2014
Application #:
13690266
Filing Dt:
11/30/2012
Publication #:
Pub Dt:
04/11/2013
Title:
METHOD FOR FORMING HIGH DENSITY PATTERNS
78
Patent #:
Issue Dt:
06/09/2015
Application #:
13690957
Filing Dt:
11/30/2012
Publication #:
Pub Dt:
06/05/2014
Title:
MEMORY CELLS HAVING FERROELECTRIC MATERIALS
79
Patent #:
Issue Dt:
11/17/2015
Application #:
13691266
Filing Dt:
11/30/2012
Publication #:
Pub Dt:
06/05/2014
Title:
DETERMINING SOFT DATA FROM A HARD READ
80
Patent #:
Issue Dt:
05/13/2014
Application #:
13691338
Filing Dt:
11/30/2012
Publication #:
Pub Dt:
04/11/2013
Title:
Systems and Methods for Internal Initialization of a Nonvolatile Memory
81
Patent #:
Issue Dt:
08/12/2014
Application #:
13692269
Filing Dt:
12/03/2012
Publication #:
Pub Dt:
04/18/2013
Title:
METHOD AND APPARATUS FOR SENDING DATA FROM MULTIPLE SOURCES OVER A COMMUNICATIONS BUS
82
Patent #:
Issue Dt:
07/08/2014
Application #:
13692407
Filing Dt:
12/03/2012
Publication #:
Pub Dt:
05/16/2013
Title:
ZR-SUBSTITUTED BATIO3 FILMS
83
Patent #:
Issue Dt:
07/22/2014
Application #:
13692666
Filing Dt:
12/03/2012
Publication #:
Pub Dt:
06/05/2014
Title:
APPARATUSES AND METHODS FOR DELAYING SIGNALS USING A DELAY LINE WITH HOMOGENOUS ARCHITECTURE AND INTEGRATED MEASURE INITIALIZATION CIRCUITRY
84
Patent #:
Issue Dt:
10/21/2014
Application #:
13692812
Filing Dt:
12/03/2012
Publication #:
Pub Dt:
04/18/2013
Title:
ERROR CORRECTION IN A STACKED MEMORY
85
Patent #:
Issue Dt:
04/04/2017
Application #:
13692907
Filing Dt:
12/03/2012
Publication #:
Pub Dt:
06/05/2014
Title:
APPARATUSES AND METHODS FOR PRE-FETCHING AND WRITE-BACK FOR A SEGMENTED CACHE MEMORY
86
Patent #:
Issue Dt:
10/13/2015
Application #:
13693865
Filing Dt:
12/04/2012
Publication #:
Pub Dt:
06/05/2014
Title:
METHODS AND APPARATUSES FOR REFRESHING MEMORY
87
Patent #:
Issue Dt:
09/13/2016
Application #:
13693899
Filing Dt:
12/04/2012
Publication #:
Pub Dt:
06/05/2014
Title:
METHODS AND APPARATUSES FOR MEMORY TESTING WITH DATA COMPRESSION
88
Patent #:
Issue Dt:
12/17/2013
Application #:
13705744
Filing Dt:
12/05/2012
Publication #:
Pub Dt:
04/18/2013
Title:
METHOD OF MAKING A MEMORY ARRAY WITH SURROUNDING GATE ACCESS TRANSISTORS AND CAPACITORS WITH GLOBAL STAGGERED LOCAL BIT LINES
89
Patent #:
Issue Dt:
02/09/2016
Application #:
13706851
Filing Dt:
12/06/2012
Publication #:
Pub Dt:
06/12/2014
Title:
SETTING A DEFAULT READ SIGNAL BASED ON ERROR CORRECTION
90
Patent #:
Issue Dt:
06/23/2015
Application #:
13707067
Filing Dt:
12/06/2012
Publication #:
Pub Dt:
06/12/2014
Title:
APPARATUSES AND METHODS TO CONTROL BODY POTENTIAL IN MEMORY OPERATIONS
91
Patent #:
Issue Dt:
02/24/2015
Application #:
13708526
Filing Dt:
12/07/2012
Publication #:
Pub Dt:
06/12/2014
Title:
VERTICAL SOLID-STATE TRANSDUCERS AND HIGH VOLTAGE SOLID-STATE TRANSDUCERS HAVING BURIED CONTACTS AND ASSOCIATED SYSTEMS AND METHODS
92
Patent #:
Issue Dt:
11/26/2013
Application #:
13708583
Filing Dt:
12/07/2012
Publication #:
Pub Dt:
04/18/2013
Title:
EXPLICIT SKEW INTERFACE FOR REDUCING CROSSTALK AND SIMULTANEOUS SWITCHING NOISE
93
Patent #:
Issue Dt:
07/15/2014
Application #:
13708789
Filing Dt:
12/07/2012
Publication #:
Pub Dt:
06/12/2014
Title:
Methods of Forming Vertically-Stacked Structures, and Methods of Forming Vertically-Stacked Memory Cells
94
Patent #:
Issue Dt:
08/26/2014
Application #:
13709792
Filing Dt:
12/10/2012
Publication #:
Pub Dt:
06/12/2014
Title:
APPARATUSES AND METHODS FOR UNIT IDENTIFICATION IN A MASTER/SLAVE MEMORY STACK
95
Patent #:
Issue Dt:
03/25/2014
Application #:
13710067
Filing Dt:
12/10/2012
Publication #:
Pub Dt:
05/30/2013
Title:
Error-Correcting Code and Process for Fast Read-Error Correction
96
Patent #:
Issue Dt:
05/06/2014
Application #:
13710559
Filing Dt:
12/11/2012
Publication #:
Pub Dt:
04/25/2013
Title:
ALIGNMENT OF INSTRUCTIONS AND REPLIES ACROSS MULTIPLE DEVICES IN A CASCADED SYSTEM, USING BUFFERS OF PROGRAMMABLE DEPTHS
97
Patent #:
Issue Dt:
04/22/2014
Application #:
13710729
Filing Dt:
12/11/2012
Publication #:
Pub Dt:
04/25/2013
Title:
METHODS OF FORMING PATTERNS
98
Patent #:
Issue Dt:
03/10/2015
Application #:
13710785
Filing Dt:
12/11/2012
Publication #:
Pub Dt:
04/25/2013
Title:
Electronic Devices, Memory Devices and Memory Arrays
99
Patent #:
Issue Dt:
12/10/2013
Application #:
13711432
Filing Dt:
12/11/2012
Publication #:
Pub Dt:
04/25/2013
Title:
METHODS AND SYSTEMS FOR REMOVING MATERIALS FROM MICROFEATURE WORKPIECES WITH ORGANIC AND/OR NON-AQUEOUS ELECTROLYTIC MEDIA
100
Patent #:
Issue Dt:
10/06/2015
Application #:
13712635
Filing Dt:
12/12/2012
Publication #:
Pub Dt:
06/12/2014
Title:
METHOD OF FORMING A PLANAR SURFACE FOR A SEMICONDUCTOR DEVICE STRUCTURE, AND RELATED METHODS OF FORMING A SEMICONDUCTOR DEVICE STRUCTURE
Assignor
1
Exec Dt:
06/29/2018
Assignee
1
8000 S. FEDERAL WAY
BOISE, IDAHO 83707
Correspondence name and address
WSGR, C/O QUI LU FLOOD, SENIOR PARALEGAL
ONE MARKET, SPEAR TOWER, SUITE 3300
SAN FRANCISCO, CA 94105

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