|
|
Patent #:
|
|
Issue Dt:
|
01/31/2017
|
Application #:
|
15003679
|
Filing Dt:
|
01/21/2016
|
Publication #:
|
|
Pub Dt:
|
06/02/2016
| | | | |
Title:
|
Transistors and Methods of Forming Transistors
|
|
|
Patent #:
|
|
Issue Dt:
|
02/13/2018
|
Application #:
|
15003715
|
Filing Dt:
|
01/21/2016
|
Publication #:
|
|
Pub Dt:
|
06/02/2016
| | | | |
Title:
|
MEMORY ARRAYS AND METHODS OF FORMING MEMORY CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/30/2017
|
Application #:
|
15004150
|
Filing Dt:
|
01/22/2016
|
Publication #:
|
|
Pub Dt:
|
05/19/2016
| | | | |
Title:
|
METHODS AND DEVICES FOR STORING USER DATA ALONG WITH ADDRESSES CORRESPONDING TO PHYSICAL PAGES STORING VALID DATA
|
|
|
Patent #:
|
|
Issue Dt:
|
09/19/2017
|
Application #:
|
15004282
|
Filing Dt:
|
01/22/2016
|
Publication #:
|
|
Pub Dt:
|
07/27/2017
| | | | |
Title:
|
APPARATUSES, MULTI-CHIP MODULES AND CAPACITIVE CHIPS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/20/2016
|
Application #:
|
15004744
|
Filing Dt:
|
01/22/2016
|
Publication #:
|
|
Pub Dt:
|
05/19/2016
| | | | |
Title:
|
Field Effect Transistor Constructions And Memory Arrays
|
|
|
Patent #:
|
|
Issue Dt:
|
07/30/2019
|
Application #:
|
15004777
|
Filing Dt:
|
01/22/2016
|
Publication #:
|
|
Pub Dt:
|
07/27/2017
| | | | |
Title:
|
APPARATUSES AND METHODS FOR ENCODING AND DECODING OF SIGNAL LINES FOR MULTI-LEVEL COMMUNICATION ARCHITECTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/11/2017
|
Application #:
|
15004781
|
Filing Dt:
|
01/22/2016
|
Publication #:
|
|
Pub Dt:
|
05/19/2016
| | | | |
Title:
|
REFERENCE VOLTAGE GENERATORS AND SENSING CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/12/2017
|
Application #:
|
15005250
|
Filing Dt:
|
01/25/2016
|
Publication #:
|
|
Pub Dt:
|
06/02/2016
| | | | |
Title:
|
Ferroelectric Field Effect Transistors, Pluralities Of Ferroelectric Field Effect Transistors Arrayed In Row Lines And Column Lines, And Methods Of Forming A Plurality Of Ferroelectric Field Effect Transistors
|
|
|
Patent #:
|
|
Issue Dt:
|
12/25/2018
|
Application #:
|
15005360
|
Filing Dt:
|
01/25/2016
|
Publication #:
|
|
Pub Dt:
|
06/02/2016
| | | | |
Title:
|
An Array Of Conductive Lines Individually Extending Transversally Across And Elevationally Over A Mid-Portion Of Individual Active Area Regions
|
|
|
Patent #:
|
|
Issue Dt:
|
08/09/2016
|
Application #:
|
15006236
|
Filing Dt:
|
01/26/2016
|
Publication #:
|
|
Pub Dt:
|
05/19/2016
| | | | |
Title:
|
MAPPING BETWEEN PROGRAM STATES AND DATA PATTERNS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/03/2017
|
Application #:
|
15006646
|
Filing Dt:
|
01/26/2016
|
Publication #:
|
|
Pub Dt:
|
07/27/2017
| | | | |
Title:
|
APPARATUS AND METHOD FOR STANDBY CURRENT CONTROL OF SIGNAL PATH
|
|
|
Patent #:
|
|
Issue Dt:
|
10/29/2019
|
Application #:
|
15007615
|
Filing Dt:
|
01/27/2016
|
Publication #:
|
|
Pub Dt:
|
05/19/2016
| | | | |
Title:
|
STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH IMPROVED THERMAL PERFORMANCE AND ASSOCIATED SYSTEMS AND METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/05/2019
|
Application #:
|
15011115
|
Filing Dt:
|
01/29/2016
|
Publication #:
|
|
Pub Dt:
|
05/26/2016
| | | | |
Title:
|
SEMICONDUCTOR DEVICE HAVING A REDUCED FOOTPRINT OF WIRES CONNECTING A DLL CIRCUIT WITH AN INPUT/OUTPUT BUFFER
|
|
|
Patent #:
|
|
Issue Dt:
|
03/14/2017
|
Application #:
|
15011816
|
Filing Dt:
|
02/01/2016
|
Publication #:
|
|
Pub Dt:
|
05/26/2016
| | | | |
Title:
|
THREE DIMENSIONAL MEMORY ARRAY ARCHITECTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/11/2019
|
Application #:
|
15011819
|
Filing Dt:
|
02/01/2016
|
Publication #:
|
|
Pub Dt:
|
05/26/2016
| | | | |
Title:
|
METHODS AND APPARATUSES WITH VERTICAL STRINGS OF MEMORY CELLS AND SUPPORT CIRCUITRY
|
|
|
Patent #:
|
|
Issue Dt:
|
12/26/2017
|
Application #:
|
15012478
|
Filing Dt:
|
02/01/2016
|
Publication #:
|
|
Pub Dt:
|
06/09/2016
| | | | |
Title:
|
METHODS FOR OPERATING A MEMORY ARRAY
|
|
|
Patent #:
|
|
Issue Dt:
|
07/31/2018
|
Application #:
|
15012519
|
Filing Dt:
|
02/01/2016
|
Publication #:
|
|
Pub Dt:
|
05/26/2016
| | | | |
Title:
|
APPARATUSES AND METHODS TO CHANGE INFORMATION VALUES
|
|
|
Patent #:
|
|
Issue Dt:
|
08/15/2017
|
Application #:
|
15012566
|
Filing Dt:
|
02/01/2016
|
Publication #:
|
|
Pub Dt:
|
08/03/2017
| | | | |
Title:
|
CELL-BASED REFERENCE VOLTAGE GENERATION
|
|
|
Patent #:
|
|
Issue Dt:
|
02/28/2017
|
Application #:
|
15013269
|
Filing Dt:
|
02/02/2016
|
Publication #:
|
|
Pub Dt:
|
08/04/2016
| | | | |
Title:
|
LOOP STRUCTURE FOR OPERATIONS IN MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
10/16/2018
|
Application #:
|
15013298
|
Filing Dt:
|
02/02/2016
|
Publication #:
|
|
Pub Dt:
|
05/26/2016
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURES INCLUDING DIELECTRIC MATERIALS HAVING DIFFERING REMOVAL RATES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/20/2017
|
Application #:
|
15013796
|
Filing Dt:
|
02/02/2016
|
Publication #:
|
|
Pub Dt:
|
06/09/2016
| | | | |
Title:
|
Semiconductor Device
|
|
|
Patent #:
|
|
Issue Dt:
|
06/12/2018
|
Application #:
|
15015424
|
Filing Dt:
|
02/04/2016
|
Publication #:
|
|
Pub Dt:
|
06/02/2016
| | | | |
Title:
|
MEMORY DEVICES AND THEIR OPERATION HAVING TRIM REGISTERS ASSOCIATED WITH ACCESS OPERATION COMMANDS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/05/2019
|
Application #:
|
15019175
|
Filing Dt:
|
02/09/2016
|
Publication #:
|
|
Pub Dt:
|
08/10/2017
| | | | |
Title:
|
MEMORY DEVICES WITH A TRANSISTOR THAT SELECTIVELY CONNECTS A DATA LINE TO ANOTHER DATA LINE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/12/2017
|
Application #:
|
15019397
|
Filing Dt:
|
02/09/2016
|
Publication #:
|
|
Pub Dt:
|
06/02/2016
| | | | |
Title:
|
PROGRAM OPERATIONS WITH EMBEDDED LEAK CHECKS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/14/2017
|
Application #:
|
15019687
|
Filing Dt:
|
02/09/2016
|
Publication #:
|
|
Pub Dt:
|
06/02/2016
| | | | |
Title:
|
METHODS AND APPARATUSES FOR COMPENSATING FOR SOURCE VOLTAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/08/2017
|
Application #:
|
15019748
|
Filing Dt:
|
02/09/2016
|
Publication #:
|
|
Pub Dt:
|
08/04/2016
| | | | |
Title:
|
VERTICAL SOLID-STATE TRANSDUCERS AND HIGH VOLTAGE SOLID-STATE TRANSDUCERS HAVING BURIED CONTACTS AND ASSOCIATED SYSTEMS AND METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2018
|
Application #:
|
15040084
|
Filing Dt:
|
02/10/2016
|
Publication #:
|
|
Pub Dt:
|
08/10/2017
| | | | |
Title:
|
APPARATUSES AND METHODS FOR PARTITIONED PARALLEL DATA MOVEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
09/11/2018
|
Application #:
|
15041207
|
Filing Dt:
|
02/11/2016
|
Publication #:
|
|
Pub Dt:
|
08/17/2017
| | | | |
Title:
|
DISTRIBUTED INPUT/OUTPUT VIRTUALIZATION
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2018
|
Application #:
|
15041277
|
Filing Dt:
|
02/11/2016
|
Publication #:
|
|
Pub Dt:
|
06/09/2016
| | | | |
Title:
|
APPARATUSES INCLUDING MEMORY ARRAYS WITH SOURCE CONTACTS ADJACENT EDGES OF SOURCES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/21/2017
|
Application #:
|
15042197
|
Filing Dt:
|
02/12/2016
|
Publication #:
|
|
Pub Dt:
|
06/09/2016
| | | | |
Title:
|
IMPROVED DEFLATE COMPRESSION ALGORITHM
|
|
|
Patent #:
|
|
Issue Dt:
|
05/16/2017
|
Application #:
|
15043086
|
Filing Dt:
|
02/12/2016
|
Title:
|
APPARATUSES AND METHODS FOR VOLTAGE LEVEL CONTROL
|
|
|
Patent #:
|
|
Issue Dt:
|
02/13/2018
|
Application #:
|
15043236
|
Filing Dt:
|
02/12/2016
|
Publication #:
|
|
Pub Dt:
|
08/17/2017
| | | | |
Title:
|
DATA GATHERING IN MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
07/18/2017
|
Application #:
|
15043921
|
Filing Dt:
|
02/15/2016
|
Publication #:
|
|
Pub Dt:
|
06/09/2016
| | | | |
Title:
|
METHODS AND APPARATUSES INCLUDING A SELECT TRANSISTOR HAVING A BODY REGION INCLUDING MONOCRYSTALLINE SEMICONDUCTOR MATERIAL AND/OR AT LEAST A PORTION OF ITS GATE LOCATED IN A SUBSTRATE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2018
|
Application #:
|
15044185
|
Filing Dt:
|
02/16/2016
|
Publication #:
|
|
Pub Dt:
|
08/17/2017
| | | | |
Title:
|
READ THRESHOLD VOLTAGE SELECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
09/19/2017
|
Application #:
|
15044713
|
Filing Dt:
|
02/16/2016
|
Publication #:
|
|
Pub Dt:
|
06/09/2016
| | | | |
Title:
|
METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES INCLUDING METAL OXIDE STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/30/2018
|
Application #:
|
15045061
|
Filing Dt:
|
02/16/2016
|
Publication #:
|
|
Pub Dt:
|
08/17/2017
| | | | |
Title:
|
SELECTORS ON INTERFACE DIE FOR MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/04/2017
|
Application #:
|
15045124
|
Filing Dt:
|
02/16/2016
|
Publication #:
|
|
Pub Dt:
|
06/09/2016
| | | | |
Title:
|
SEMICONDUCTOR DEVICE AND METHOD FOR ADJUSTING IMPEDANCE OF OUTPUT CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
12/25/2018
|
Application #:
|
15045490
|
Filing Dt:
|
02/17/2016
|
Publication #:
|
|
Pub Dt:
|
06/09/2016
| | | | |
Title:
|
SEMICONDUCTOR DEVICE HAVING A SECOND CONDUCTIVE LAYER PARTIALLY EMBEDDED IN A STACKED INSULATING STRUCTURE AND HAVING A FIRST CONDUCTIVE LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
01/03/2017
|
Application #:
|
15045550
|
Filing Dt:
|
02/17/2016
|
Publication #:
|
|
Pub Dt:
|
08/18/2016
| | | | |
Title:
|
METHODS AND SYSTEMS FOR ROUTING IN A STATE MACHINE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/15/2018
|
Application #:
|
15045750
|
Filing Dt:
|
02/17/2016
|
Publication #:
|
|
Pub Dt:
|
08/17/2017
| | | | |
Title:
|
APPARATUSES AND METHODS FOR DATA MOVEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
01/10/2017
|
Application #:
|
15045865
|
Filing Dt:
|
02/17/2016
|
Publication #:
|
|
Pub Dt:
|
06/09/2016
| | | | |
Title:
|
MAGNETIC MEMORY CELLS AND METHODS OF FABRICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
05/10/2022
|
Application #:
|
15046078
|
Filing Dt:
|
02/17/2016
|
Publication #:
|
|
Pub Dt:
|
08/17/2017
| | | | |
Title:
|
APPARATUSES AND METHODS FOR INTERNAL HEAT SPREADING FOR PACKAGED SEMICONDUCTOR DIE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/28/2017
|
Application #:
|
15046330
|
Filing Dt:
|
02/17/2016
|
Title:
|
MEMORY CELL ARCHITECTURE FOR MULTILEVEL CELL PROGRAMMING
|
|
|
Patent #:
|
|
Issue Dt:
|
03/05/2019
|
Application #:
|
15046666
|
Filing Dt:
|
02/18/2016
|
Publication #:
|
|
Pub Dt:
|
08/24/2017
| | | | |
Title:
|
ERROR RATE REDUCTION
|
|
|
Patent #:
|
|
Issue Dt:
|
08/22/2017
|
Application #:
|
15046949
|
Filing Dt:
|
02/18/2016
|
Publication #:
|
|
Pub Dt:
|
08/24/2017
| | | | |
Title:
|
APPARATUSES AND METHODS FOR PHOTONIC COMMUNICATION AND PHOTONIC ADDRESSING
|
|
|
Patent #:
|
|
Issue Dt:
|
11/27/2018
|
Application #:
|
15047000
|
Filing Dt:
|
02/18/2016
|
Publication #:
|
|
Pub Dt:
|
08/24/2017
| | | | |
Title:
|
APPARATUSES AND METHODS FOR MULTIPLE ADDRESS REGISTERS FOR A SOLID STATE DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/20/2018
|
Application #:
|
15048133
|
Filing Dt:
|
02/19/2016
|
Publication #:
|
|
Pub Dt:
|
08/24/2017
| | | | |
Title:
|
MODIFIED DECODE FOR CORNER TURN
|
|
|
Patent #:
|
|
Issue Dt:
|
03/23/2021
|
Application #:
|
15048179
|
Filing Dt:
|
02/19/2016
|
Publication #:
|
|
Pub Dt:
|
08/24/2017
| | | | |
Title:
|
DATA TRANSFER WITH A BIT VECTOR OPERATION DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/11/2017
|
Application #:
|
15048746
|
Filing Dt:
|
02/19/2016
|
Publication #:
|
|
Pub Dt:
|
06/16/2016
| | | | |
Title:
|
METHOD, SYSTEM, AND DEVICE FOR HEATING A PHASE CHANGE MEMORY CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2018
|
Application #:
|
15049097
|
Filing Dt:
|
02/21/2016
|
Publication #:
|
|
Pub Dt:
|
06/16/2016
| | | | |
Title:
|
Methods of Fabricating Integrated Structures
|
|
|
Patent #:
|
|
Issue Dt:
|
02/14/2017
|
Application #:
|
15049100
|
Filing Dt:
|
02/21/2016
|
Publication #:
|
|
Pub Dt:
|
06/16/2016
| | | | |
Title:
|
Memory Cells, Integrated Devices, and Methods of Forming Memory Cells
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
15049754
|
Filing Dt:
|
02/22/2016
|
Publication #:
|
|
Pub Dt:
|
06/16/2016
| | | | |
Title:
|
INDEPENDENT CONTROL OF STACKED ELECTRONIC MODULES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/28/2017
|
Application #:
|
15050231
|
Filing Dt:
|
02/22/2016
|
Publication #:
|
|
Pub Dt:
|
06/16/2016
| | | | |
Title:
|
MICROELECTRONIC DEVICE PACKAGES, STACKED MICROELECTRONIC DEVICE PACKAGES, AND METHODS FOR MANUFACTURING MICROELECTRONIC DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/29/2019
|
Application #:
|
15050238
|
Filing Dt:
|
02/22/2016
|
Publication #:
|
|
Pub Dt:
|
06/16/2016
| | | | |
Title:
|
APPARATUSES AND METHOD FOR OVER-VOLTAGE EVENT PROTECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
12/04/2018
|
Application #:
|
15050248
|
Filing Dt:
|
02/22/2016
|
Publication #:
|
|
Pub Dt:
|
06/16/2016
| | | | |
Title:
|
Memory Systems and Memory Programming Methods
|
|
|
Patent #:
|
|
Issue Dt:
|
07/09/2019
|
Application #:
|
15050328
|
Filing Dt:
|
02/22/2016
|
Publication #:
|
|
Pub Dt:
|
06/16/2016
| | | | |
Title:
|
Method of Forming Contacts for a Memory Device
|
|
|
Patent #:
|
|
Issue Dt:
|
08/22/2017
|
Application #:
|
15050858
|
Filing Dt:
|
02/23/2016
|
Publication #:
|
|
Pub Dt:
|
06/16/2016
| | | | |
Title:
|
SEMICONDUCTOR DEVICES AND METHODS FOR BACKSIDE PHOTO ALIGNMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
03/07/2017
|
Application #:
|
15051112
|
Filing Dt:
|
02/23/2016
|
Publication #:
|
|
Pub Dt:
|
06/16/2016
| | | | |
Title:
|
APPARATUSES AND METHODS FOR PERFORMING LOGICAL OPERATIONS USING SENSING CIRCUITRY
|
|
|
Patent #:
|
|
Issue Dt:
|
07/04/2017
|
Application #:
|
15052161
|
Filing Dt:
|
02/24/2016
|
Publication #:
|
|
Pub Dt:
|
06/16/2016
| | | | |
Title:
|
OPTICAL INTERCONNECT IN HIGH-SPEED MEMORY SYSTEMS
|
|
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Patent #:
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Issue Dt:
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03/07/2017
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Application #:
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15053291
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Filing Dt:
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02/25/2016
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Title:
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MEMORY DEVICES WITH STAIRS IN A STAIRCASE COUPLED TO TIERS OF MEMORY CELLS AND TO PASS TRANSISTORS DIRECTLY UNDER THE STAIRCASE
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Patent #:
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Issue Dt:
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02/21/2017
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Application #:
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15053562
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Filing Dt:
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02/25/2016
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Publication #:
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Pub Dt:
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06/23/2016
| | | | |
Title:
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SYSTEMS, AND DEVICES, AND METHODS FOR PROGRAMMING A RESISTIVE MEMORY CELL
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|
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Patent #:
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Issue Dt:
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06/11/2019
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Application #:
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15053719
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Filing Dt:
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02/25/2016
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Publication #:
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Pub Dt:
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08/31/2017
| | | | |
Title:
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REDUNDANT ARRAY OF INDEPENDENT NAND FOR A THREE-DIMENSIONAL MEMORY ARRAY
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|
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Patent #:
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Issue Dt:
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06/13/2017
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Application #:
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15054409
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Filing Dt:
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02/26/2016
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Publication #:
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Pub Dt:
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06/23/2016
| | | | |
Title:
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POWER MANAGEMENT
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|
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Patent #:
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|
Issue Dt:
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08/08/2017
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Application #:
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15054984
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Filing Dt:
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02/26/2016
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Publication #:
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Pub Dt:
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06/23/2016
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Title:
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METHODS AND APPARATUSES HAVING A VOLTAGE GENERATOR WITH AN ADJUSTABLE VOLTAGE DROP FOR REPRESENTING A VOLTAGE DROP OF A MEMORY CELL AND/OR A CURRENT MIRROR CIRCUIT AND REPLICA CIRCUIT
|
|
|
Patent #:
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Issue Dt:
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11/13/2018
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Application #:
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15055230
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Filing Dt:
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02/26/2016
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Publication #:
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Pub Dt:
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08/31/2017
| | | | |
Title:
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APPARATUSES AND METHODS FOR LEVEL SHIFTING
|
|
|
Patent #:
|
|
Issue Dt:
|
09/26/2017
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Application #:
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15056548
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Filing Dt:
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02/29/2016
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Publication #:
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Pub Dt:
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06/23/2016
| | | | |
Title:
|
CELL PILLAR STRUCTURES AND INTEGRATED FLOWS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/02/2018
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Application #:
|
15056845
|
Filing Dt:
|
02/29/2016
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Publication #:
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Pub Dt:
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06/23/2016
| | | | |
Title:
|
METHODS AND APPARATUS PROVIDING THERMAL ISOLATION OF PHOTONIC DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/04/2017
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Application #:
|
15057736
|
Filing Dt:
|
03/01/2016
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Title:
|
VERTICAL BIT VECTOR SHIFT IN MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
07/17/2018
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Application #:
|
15057909
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Filing Dt:
|
03/01/2016
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Publication #:
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Pub Dt:
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06/23/2016
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURES AND DEVICES AND METHODS OF FORMING SEMICONDUCTOR STRUCTURES AND MAGNETIC MEMORY CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2018
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Application #:
|
15057914
|
Filing Dt:
|
03/01/2016
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Publication #:
|
|
Pub Dt:
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09/07/2017
| | | | |
Title:
|
GROUND REFERENCE SCHEME FOR A MEMORY CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
05/02/2017
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Application #:
|
15058009
|
Filing Dt:
|
03/01/2016
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Publication #:
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|
Pub Dt:
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06/23/2016
| | | | |
Title:
|
SYSTEM AND METHOD OF COMMAND BASED AND CURRENT LIMIT CONTROLLED MEMORY DEVICE POWER UP
|
|
|
Patent #:
|
|
Issue Dt:
|
05/23/2017
|
Application #:
|
15058810
|
Filing Dt:
|
03/02/2016
|
Publication #:
|
|
Pub Dt:
|
09/08/2016
| | | | |
Title:
|
REPLACEMENT MATERIALS PROCESSES FOR FORMING CROSS POINT MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
08/06/2019
|
Application #:
|
15058921
|
Filing Dt:
|
03/02/2016
|
Publication #:
|
|
Pub Dt:
|
09/07/2017
| | | | |
Title:
|
SEMICONDUCTOR DEVICE STRUCTURES INCLUDING STAIRCASE STRUCTURES, AND RELATED METHODS AND ELECTRONIC SYSTEMS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/18/2017
|
Application #:
|
15059020
|
Filing Dt:
|
03/02/2016
|
Publication #:
|
|
Pub Dt:
|
06/30/2016
| | | | |
Title:
|
DEVICES, SYSTEMS AND METHODS FOR MANUFACTURING THROUGH-SUBSTRATE VIAS AND FRONT-SIDE STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
11/14/2017
|
Application #:
|
15059076
|
Filing Dt:
|
03/02/2016
|
Publication #:
|
|
Pub Dt:
|
06/23/2016
| | | | |
Title:
|
STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH THERMAL SPACERS AND ASSOCIATED SYSTEMS AND METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/24/2017
|
Application #:
|
15059367
|
Filing Dt:
|
03/03/2016
|
Publication #:
|
|
Pub Dt:
|
07/14/2016
| | | | |
Title:
|
MEMORY CELL COUPLING COMPENSATION
|
|
|
Patent #:
|
|
Issue Dt:
|
04/04/2017
|
Application #:
|
15059457
|
Filing Dt:
|
03/03/2016
|
Publication #:
|
|
Pub Dt:
|
06/30/2016
| | | | |
Title:
|
PROGRAMMING AND/OR ERASING A MEMORY DEVICE IN RESPONSE TO ITS PROGRAM AND/OR ERASE HISTORY
|
|
|
Patent #:
|
|
Issue Dt:
|
01/24/2017
|
Application #:
|
15059541
|
Filing Dt:
|
03/03/2016
|
Publication #:
|
|
Pub Dt:
|
06/30/2016
| | | | |
Title:
|
APPARATUSES AND METHODS FOR SENSING USING AN INTEGRATION COMPONENT
|
|
|
Patent #:
|
|
Issue Dt:
|
08/22/2017
|
Application #:
|
15060222
|
Filing Dt:
|
03/03/2016
|
Publication #:
|
|
Pub Dt:
|
09/15/2016
| | | | |
Title:
|
DATA SHIFT BY ELEMENTS OF A VECTOR IN MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
09/25/2018
|
Application #:
|
15061559
|
Filing Dt:
|
03/04/2016
|
Publication #:
|
|
Pub Dt:
|
06/30/2016
| | | | |
Title:
|
APPARATUSES AND METHODS FOR MEASURING AN ELECTRICAL CHARACTERISTIC OF A MODEL SIGNAL LINE AND PROVIDING MEASUREMENT INFORMATION
|
|
|
Patent #:
|
|
Issue Dt:
|
09/05/2017
|
Application #:
|
15062452
|
Filing Dt:
|
03/07/2016
|
Publication #:
|
|
Pub Dt:
|
09/07/2017
| | | | |
Title:
|
METHODS OF FORMING SEMICONDUCTOR DEVICES INCLUDING DETERMINING MISREGISTRATION BETWEEN SEMICONDUCTOR LEVELS AND RELATED APPARATUSES
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/2019
|
Application #:
|
15062675
|
Filing Dt:
|
03/07/2016
|
Publication #:
|
|
Pub Dt:
|
09/07/2017
| | | | |
Title:
|
LOW CAPACITANCE THROUGH SUBSTRATE VIA STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/27/2018
|
Application #:
|
15063117
|
Filing Dt:
|
03/07/2016
|
Publication #:
|
|
Pub Dt:
|
09/07/2017
| | | | |
Title:
|
APPARATUSES AND METHODS FOR SEMICONDUCTOR CIRCUIT LAYOUT
|
|
|
Patent #:
|
|
Issue Dt:
|
04/25/2017
|
Application #:
|
15063140
|
Filing Dt:
|
03/07/2016
|
Publication #:
|
|
Pub Dt:
|
06/30/2016
| | | | |
Title:
|
MEMORY DEVICE COMMAND RECEIVING AND DECODING METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/06/2017
|
Application #:
|
15063179
|
Filing Dt:
|
03/07/2016
|
Publication #:
|
|
Pub Dt:
|
06/30/2016
| | | | |
Title:
|
PHASE CHANGE MEMORY STACK WITH TREATED SIDEWALLS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/25/2017
|
Application #:
|
15063208
|
Filing Dt:
|
03/07/2016
|
Publication #:
|
|
Pub Dt:
|
06/30/2016
| | | | |
Title:
|
FAST PROGRAMMING MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/03/2017
|
Application #:
|
15063229
|
Filing Dt:
|
03/07/2016
|
Title:
|
STAGGERED DLL CLOCKING ON N-DETECT QED TO MINIMIZE CLOCK COMMAND DECODE AND DELAY PATH
|
|
|
Patent #:
|
|
Issue Dt:
|
11/14/2017
|
Application #:
|
15063230
|
Filing Dt:
|
03/07/2016
|
Publication #:
|
|
Pub Dt:
|
06/30/2016
| | | | |
Title:
|
METHODS AND SYSTEMS FOR DETECTION IN A STATE MACHINE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/20/2018
|
Application #:
|
15063986
|
Filing Dt:
|
03/08/2016
|
Publication #:
|
|
Pub Dt:
|
09/15/2016
| | | | |
Title:
|
DIVISION OPERATIONS ON VARIABLE LENGTH ELEMENTS IN MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
10/04/2016
|
Application #:
|
15064002
|
Filing Dt:
|
03/08/2016
|
Publication #:
|
|
Pub Dt:
|
06/30/2016
| | | | |
Title:
|
Memory Arrays and Methods of Forming Memory Arrays
|
|
|
Patent #:
|
|
Issue Dt:
|
06/26/2018
|
Application #:
|
15064512
|
Filing Dt:
|
03/08/2016
|
Publication #:
|
|
Pub Dt:
|
06/30/2016
| | | | |
Title:
|
ENCAPSULATION ENABLED PCIE VIRTUALISATION
|
|
|
Patent #:
|
|
Issue Dt:
|
06/06/2017
|
Application #:
|
15064988
|
Filing Dt:
|
03/09/2016
|
Publication #:
|
|
Pub Dt:
|
08/18/2016
| | | | |
Title:
|
MEMORY CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/04/2018
|
Application #:
|
15065483
|
Filing Dt:
|
03/09/2016
|
Publication #:
|
|
Pub Dt:
|
09/15/2016
| | | | |
Title:
|
VECTOR POPULATION COUNT DETERMINATION IN MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
09/11/2018
|
Application #:
|
15066488
|
Filing Dt:
|
03/10/2016
|
Publication #:
|
|
Pub Dt:
|
12/01/2016
| | | | |
Title:
|
APPARATUSES AND METHODS FOR COMPUTE ENABLED CACHE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/06/2019
|
Application #:
|
15066573
|
Filing Dt:
|
03/10/2016
|
Publication #:
|
|
Pub Dt:
|
09/14/2017
| | | | |
Title:
|
PARALLEL ACCESS TECHNIQUES WITHIN MEMORY SECTIONS THROUGH SECTION INDEPENDENCE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/2019
|
Application #:
|
15066674
|
Filing Dt:
|
03/10/2016
|
Publication #:
|
|
Pub Dt:
|
09/14/2017
| | | | |
Title:
|
APPARATUSES AND METHODS FOR CACHE INVALIDATE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/12/2018
|
Application #:
|
15066831
|
Filing Dt:
|
03/10/2016
|
Publication #:
|
|
Pub Dt:
|
09/14/2017
| | | | |
Title:
|
PROCESSING IN MEMORY (PIM) CAPABLE MEMORY DEVICE HAVING SENSING CIRCUITRY PERFORMING LOGIC OPERATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/24/2017
|
Application #:
|
15067838
|
Filing Dt:
|
03/11/2016
|
Title:
|
OFFSET COMPENSATION FOR FERROELECTRIC MEMORY CELL SENSING
|
|
|
Patent #:
|
|
Issue Dt:
|
09/25/2018
|
Application #:
|
15067954
|
Filing Dt:
|
03/11/2016
|
Publication #:
|
|
Pub Dt:
|
09/14/2017
| | | | |
Title:
|
MEMORY CELL SENSING WITH STORAGE COMPONENT ISOLATION
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2018
|
Application #:
|
15068185
|
Filing Dt:
|
03/11/2016
|
Publication #:
|
|
Pub Dt:
|
09/14/2017
| | | | |
Title:
|
CONDUCTIVE HARD MASK FOR MEMORY DEVICE FORMATION
|
|