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Reel/Frame:047243/0001   Pages: 959
Recorded: 08/23/2018
Attorney Dkt #:4816.238
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
1
Patent #:
Issue Dt:
09/18/2001
Application #:
09501034
Filing Dt:
02/09/2000
Title:
Method of manufacturing an interposer
2
Patent #:
Issue Dt:
09/24/2002
Application #:
09501131
Filing Dt:
02/09/2000
Title:
Nonvolatile multilevel memory and reading method therefor
3
Patent #:
Issue Dt:
05/28/2002
Application #:
09502070
Filing Dt:
02/10/2000
Title:
SEMICONDUCTOR DEVICE WITH IMPROVED INTERCONNECTIONS BETWEEN THE CHIP AND THE TERMINALS, AND PROCESS FOR ITS MANUFACTURE
4
Patent #:
Issue Dt:
08/06/2002
Application #:
09502788
Filing Dt:
02/11/2000
Title:
SETPOINT SILICON CONTROLLED RECTIFIER (SCR) ELECTROSTATIC DISCHARGE (ESD) CORE CLAMP
5
Patent #:
Issue Dt:
09/16/2003
Application #:
09502793
Filing Dt:
02/11/2000
Title:
COMPUTER NETWORK WITH SWAPPABLE COMPONENTS
6
Patent #:
Issue Dt:
03/20/2001
Application #:
09502822
Filing Dt:
02/11/2000
Title:
Dram array with gridded sense amplifier power source for enhanced column repair
7
Patent #:
Issue Dt:
08/06/2002
Application #:
09502827
Filing Dt:
02/11/2000
Title:
EFFICIENT CMOS DC-DC CONVERTERS BASED ON SWITCHED CAPACITOR POWER SUPPLIES WITH INDUCTIVE CURRENT LIMITERS
8
Patent #:
Issue Dt:
11/07/2000
Application #:
09502925
Filing Dt:
02/11/2000
Title:
Method for improving a stepper signal in a planarized surface over alignment topography
9
Patent #:
Issue Dt:
05/23/2006
Application #:
09502994
Filing Dt:
02/11/2000
Title:
3-D RENDERING TEXTURE CACHING SCHEME
10
Patent #:
Issue Dt:
12/10/2002
Application #:
09503105
Filing Dt:
02/11/2000
Title:
LOW TEMPERATURE NITRIDE USED AS CU BARRIER LAYER
11
Patent #:
Issue Dt:
07/02/2002
Application #:
09503278
Filing Dt:
02/14/2000
Publication #:
Pub Dt:
02/14/2002
Title:
Low dielectric constant shallow trench isolation
12
Patent #:
Issue Dt:
05/08/2001
Application #:
09503412
Filing Dt:
02/14/2000
Title:
Method of removing surface defects or other recesses during the formation of a semiconductor device
13
Patent #:
Issue Dt:
11/26/2002
Application #:
09503420
Filing Dt:
02/11/2000
Title:
METHOD AND APPARATUS FOR APPLICATION OF SPRAY ADHESIVE TO A LEADFRAME FOR CHIP BONDING
14
Patent #:
Issue Dt:
07/12/2005
Application #:
09503553
Filing Dt:
02/11/2000
Title:
METHOD FOR OPTIMIZING PRINTING OF AN ALTERNATING PHASE SHIFT MASK HAVING A PHASE SHIFT ERROR
15
Patent #:
Issue Dt:
04/03/2001
Application #:
09503836
Filing Dt:
02/15/2000
Title:
Integrated circuit charge coupling circuit
16
Patent #:
Issue Dt:
11/11/2003
Application #:
09503879
Filing Dt:
02/14/2000
Title:
METHOD AND APPARATUS FOR BRANCH TRACE MESSAGE SCHEME
17
Patent #:
Issue Dt:
04/10/2001
Application #:
09504191
Filing Dt:
02/15/2000
Title:
Chemical-mechanical polishing slurry
18
Patent #:
Issue Dt:
09/25/2001
Application #:
09504496
Filing Dt:
02/15/2000
Title:
Alternate method and structure for improved floating gate tunneling devices
19
Patent #:
Issue Dt:
03/23/2004
Application #:
09505018
Filing Dt:
02/16/2000
Title:
AN ADHESIVE LAYER FOR AN ELECTRONIC APPARATUS HAVING MULTIPLE SEMICONDUCTOR DEVICES
20
Patent #:
Issue Dt:
12/17/2002
Application #:
09505309
Filing Dt:
02/16/2000
Title:
GRADED LDD IMPLANT PROCESS FOR SUB-HALF-MICRON MOS DEVICES
21
Patent #:
Issue Dt:
08/14/2001
Application #:
09505332
Filing Dt:
02/16/2000
Title:
Semiconductor wirebond machine leadframe thermal map system
22
Patent #:
Issue Dt:
11/12/2002
Application #:
09505391
Filing Dt:
02/16/2000
Title:
HEAT SINK FOR MICROCHIP APPLICATION
23
Patent #:
Issue Dt:
09/17/2002
Application #:
09505599
Filing Dt:
02/16/2000
Title:
COMPUTER HOUSING WITH EXPANSION BAY COVER AND METHODS FOR OPERATING EXPANSION BAY COVERS
24
Patent #:
Issue Dt:
05/28/2002
Application #:
09505943
Filing Dt:
02/15/2000
Title:
INTEGRATED CIRCUIT HAVING CONDUCTIVE PATHS OF DIFFERENT HEIGHTS FORMED FROM THE SAME LAYER STRUCTURE AND METHOD FOR FORMING THE SAME
25
Patent #:
Issue Dt:
10/29/2002
Application #:
09506205
Filing Dt:
02/17/2000
Title:
PROCESS FOR FABRICATING FILMS OF UNIFORM PROPERTIES ON SEMICONDUCTOR DEVICES
26
Patent #:
Issue Dt:
11/01/2005
Application #:
09507213
Filing Dt:
02/18/2000
Title:
METHOD OF INVERSE QUANTIZED SIGNAL SAMPLES OF AN IMAGE DURING IMAGE DECOMPRESSION
27
Patent #:
Issue Dt:
06/08/2004
Application #:
09507399
Filing Dt:
02/18/2000
Title:
METHOD OF QUANTIZING SIGNAL SAMPLES OF AN IMAGE DURING SAME
28
Patent #:
Issue Dt:
04/02/2002
Application #:
09507777
Filing Dt:
02/18/2000
Title:
Process for manufacturing semicondutor integrated memory devices with cells matrix having virtual ground
29
Patent #:
Issue Dt:
05/10/2005
Application #:
09507964
Filing Dt:
02/22/2000
Title:
POLYNORBORNENE FOAM INSULATION FOR INTEGRATED CIRCUITS
30
Patent #:
Issue Dt:
10/15/2002
Application #:
09510095
Filing Dt:
02/22/2000
Publication #:
Pub Dt:
12/20/2001
Title:
METHOD OF FABRICATING A SEMICONDUCTOR-ON-INSULATOR MEMORY CELL WITH BURIED WORD AND BODY LINES
31
Patent #:
Issue Dt:
04/16/2002
Application #:
09510413
Filing Dt:
02/22/2000
Publication #:
Pub Dt:
11/22/2001
Title:
METHOD FOR MAKING SEMICONDUCTOR DEVICES HAVING GRADUAL SLOPE CONTACTS
32
Patent #:
Issue Dt:
06/18/2002
Application #:
09510817
Filing Dt:
02/23/2000
Title:
MULTI-CHIP DEVICE UTILIZING A FLIP CHIP AND WIRE BOND ASSEMBLY
33
Patent #:
Issue Dt:
03/09/2004
Application #:
09510828
Filing Dt:
02/23/2000
Title:
SPRING ELEMENT FOR USE IN AN APPARATUS FOR ATTACHING TO A SEMICONDUCTOR AND A METHOD OF ATTACHING
34
Patent #:
Issue Dt:
09/17/2002
Application #:
09510890
Filing Dt:
02/23/2000
Title:
METHODOLOGY OF REMOVING MISPLACED ENCAPSULANT FOR ATTACHMENT OF HEAT SINKS IN A CHIP ON BOARD PACKAGE
35
Patent #:
Issue Dt:
05/08/2001
Application #:
09510894
Filing Dt:
02/23/2000
Title:
CHIP ON BOARD WITH HEAT SINK ATTACHMENT
36
Patent #:
Issue Dt:
07/20/2004
Application #:
09511092
Filing Dt:
02/23/2000
Title:
METHOD AND SYSTEM FOR AUTHENTICATING A USER OF A COMPUTER SYSTEM
37
Patent #:
Issue Dt:
07/24/2001
Application #:
09511471
Filing Dt:
02/23/2000
Title:
Variable equilibrate voltage circuit for paired digit lines
38
Patent #:
Issue Dt:
07/31/2001
Application #:
09511520
Filing Dt:
02/23/2000
Title:
Variable equilibrate voltage circuit for paired digit lines
39
Patent #:
Issue Dt:
09/04/2001
Application #:
09511577
Filing Dt:
02/23/2000
Title:
High-voltage charge pump circuit
40
Patent #:
Issue Dt:
07/22/2003
Application #:
09511609
Filing Dt:
02/23/2000
Title:
CHIP ON BOARD AND HEAT SINK ATTACHMENT METHODS
41
Patent #:
Issue Dt:
09/30/2003
Application #:
09511692
Filing Dt:
02/23/2000
Title:
METHOD OF MAKING AN ELECTRICAL CONTACT DEVICE
42
Patent #:
Issue Dt:
10/09/2001
Application #:
09512900
Filing Dt:
02/25/2000
Title:
Process for manufacturing semiconductor integrated memory devices with cells matrix having virtual ground
43
Patent #:
Issue Dt:
08/31/2004
Application #:
09512978
Filing Dt:
02/24/2000
Publication #:
Pub Dt:
04/24/2003
Title:
METHODS OF FORMING CONTACTS, METHODS OF CONTACTING LINES, METHODS OF OPERATING INTEGRATED CIRCUITRY, AND INTEGRATED CIRCUITS
44
Patent #:
Issue Dt:
07/10/2001
Application #:
09512981
Filing Dt:
02/24/2000
Title:
SEMICONDUCTOR WAFER ALIGNMENT TOOLS
45
Patent #:
Issue Dt:
11/19/2002
Application #:
09513000
Filing Dt:
02/25/2000
Title:
METHOD FOR PROVIDING AN ALIGNMENT DIFFRACTION GRATING FOR PHOTOLITHOGRAPHIC ALIGNMENT DURING SEMICONDUCTOR FABRICATION
46
Patent #:
Issue Dt:
07/03/2001
Application #:
09513273
Filing Dt:
02/24/2000
Title:
System for evaluating and reporting semiconductor test processes
47
Patent #:
Issue Dt:
03/04/2003
Application #:
09513286
Filing Dt:
02/24/2000
Title:
METHOD FOR CORRECTION OF ERRORS IN A BINARY WORD STORED IN MULTILEVEL MEMORY CELLS, NOT REQUIRING ADDITIONAL CELLS
48
Patent #:
Issue Dt:
10/09/2001
Application #:
09513598
Filing Dt:
02/25/2000
Title:
Method for reading a multilevel nonvolatile memory and multilevel nonvolatile memory
49
Patent #:
Issue Dt:
12/04/2001
Application #:
09513641
Filing Dt:
02/25/2000
Title:
Full page increment/decrement burst for ddr sdram/sgram
50
Patent #:
Issue Dt:
05/14/2002
Application #:
09513761
Filing Dt:
02/25/2000
Title:
Dummy wordline for controlling the timing of the firing of sense amplifiers in a memory device in relation to the firing of wordlines in the memory device
51
Patent #:
Issue Dt:
08/28/2001
Application #:
09513762
Filing Dt:
02/25/2000
Title:
Latched sense amplifier with tri-state outputs
52
Patent #:
Issue Dt:
05/28/2002
Application #:
09513797
Filing Dt:
02/25/2000
Title:
INTEGRATED CIRCUIT PACKAGING FOR OPTICAL SENSOR DEVICES
53
Patent #:
Issue Dt:
03/06/2001
Application #:
09513936
Filing Dt:
02/28/2000
Title:
Sense amplifier for low voltage memory arrays
54
Patent #:
Issue Dt:
06/19/2001
Application #:
09513938
Filing Dt:
02/28/2000
Title:
Dynamic flash memory cells with ultrathin tunnel oxides
55
Patent #:
Issue Dt:
02/18/2003
Application #:
09513939
Filing Dt:
02/28/2000
Publication #:
Pub Dt:
12/20/2001
Title:
Method for manufacturing improved stencil/screen
56
Patent #:
Issue Dt:
05/08/2001
Application #:
09513940
Filing Dt:
02/28/2000
Title:
Power level detection circuit
57
Patent #:
Issue Dt:
09/25/2001
Application #:
09514493
Filing Dt:
02/29/2000
Title:
Circuits and methods using vertical complementary transistors
58
Patent #:
Issue Dt:
12/24/2002
Application #:
09514578
Filing Dt:
02/28/2000
Title:
PLANARIZING PADS, PLANARIZING MACHINES AND METHODS FOR MAKING AND USING PLANARIZING PADS IN MECHANICAL AND CHEMICAL-MECHANICAL PLANARAZATION OF MICROELECRTRONIC DEVICE SUBSTRATE ASSEMBLIES
59
Patent #:
Issue Dt:
05/07/2002
Application #:
09514627
Filing Dt:
02/28/2000
Title:
P-channel dynamic flash memory cells with ultrathin tunnel oxides
60
Patent #:
Issue Dt:
09/02/2003
Application #:
09515246
Filing Dt:
02/29/2000
Title:
METHOD AND SYSTEM FOR ADDRESSING GRAPHICS DATA FOR EFFICIENT DATA ACCESS
61
Patent #:
Issue Dt:
10/24/2000
Application #:
09515362
Filing Dt:
02/29/2000
Title:
Plasma processing tools, dual-source plasma etchers, dual-source plasma etching methods, and methods of forming planar coil dual-source plasma etchers
62
Patent #:
Issue Dt:
02/25/2003
Application #:
09515579
Filing Dt:
02/29/2000
Title:
METHOD OF PRESSURE CURING FOR REDUCING VOIDS IN A DIE ATTACH BONDLINE AND APPLICATIONS THEREOF
63
Patent #:
Issue Dt:
03/27/2001
Application #:
09515804
Filing Dt:
02/29/2000
Title:
Self-aligned contact formation for semiconductor devices
64
Patent #:
Issue Dt:
04/30/2002
Application #:
09516047
Filing Dt:
03/01/2000
Title:
Semiconductor device for attachment to a semiconductor substrate
65
Patent #:
Issue Dt:
05/14/2002
Application #:
09516433
Filing Dt:
03/01/2000
Title:
Active pixel sensor with fully-depleted buried photoreceptor
66
Patent #:
Issue Dt:
07/03/2001
Application #:
09516532
Filing Dt:
03/01/2000
Title:
Apparatus and method for programming voltage protection in a non-volatile memory system
67
Patent #:
Issue Dt:
07/24/2001
Application #:
09516550
Filing Dt:
03/01/2000
Title:
Apparatus and method for programming voltage protection in a non-volatile memory system
68
Patent #:
Issue Dt:
02/06/2001
Application #:
09516592
Filing Dt:
07/09/1999
Title:
SYNCHRONOUS SRAM HAVING PIPELINED ENABLE AND BURST ADDRESS GENERATION
69
Patent #:
Issue Dt:
11/05/2002
Application #:
09516633
Filing Dt:
03/01/2000
Title:
METHOD OF FORMING INTEGRATED CIRCUITRY, METHOD OF FORMING A CAPACITOR AND METHOD OF FORMING DRAM INTEGRATED CIRCUITRY
70
Patent #:
Issue Dt:
07/01/2003
Application #:
09516652
Filing Dt:
03/01/2000
Title:
PROCESS FOR FORMING MICROELECTRONIC PACKAGES AND INTERMEDIATE STRUCTURES FORMED THEREWITH
71
Patent #:
Issue Dt:
01/13/2004
Application #:
09516681
Filing Dt:
03/01/2000
Title:
MEMORY CELL WITH TIGHT COUPLING
72
Patent #:
Issue Dt:
09/04/2001
Application #:
09516819
Filing Dt:
03/01/2000
Title:
Integrated circuitry and dram integrated circuitry
73
Patent #:
Issue Dt:
05/22/2001
Application #:
09517028
Filing Dt:
03/02/2000
Title:
Row decoded biasing of sense amplifier for improved one's margin
74
Patent #:
Issue Dt:
11/20/2001
Application #:
09517038
Filing Dt:
03/02/2000
Title:
Data ordering for cache data transfer
75
Patent #:
Issue Dt:
05/12/2009
Application #:
09517127
Filing Dt:
03/02/2000
Title:
SEMICONDUCTOR PROCESSOR SYSTEMS, A SYSTEM CONFIGURED TO PROVIDE A SEMICONDUCTOR WORKPIECE PROCESS FLUID
76
Patent #:
Issue Dt:
08/27/2002
Application #:
09517318
Filing Dt:
03/02/2000
Title:
SYSTEM-ON-A-CHIP WITH MULTI-LAYERED METALLIZED THROUGH-HOLE INTERCONNECTION
77
Patent #:
Issue Dt:
08/14/2001
Application #:
09517473
Filing Dt:
03/02/2000
Title:
Reflectance method for evaluating the surface characteristics of opaque materials
78
Patent #:
Issue Dt:
01/09/2001
Application #:
09517684
Filing Dt:
03/02/2000
Title:
Methods of forming metallization layers and integrated circuits containing such
79
Patent #:
Issue Dt:
12/11/2001
Application #:
09517814
Filing Dt:
03/02/2000
Title:
Circuit and method for a high data transfer rate output driver
80
Patent #:
Issue Dt:
12/24/2002
Application #:
09518292
Filing Dt:
03/03/2000
Title:
METHOD FOR ETCHING DIELECTRIC FILMS
81
Patent #:
Issue Dt:
09/11/2001
Application #:
09518293
Filing Dt:
03/03/2000
Title:
Hermetic chip and method of manufacture
82
Patent #:
Issue Dt:
03/01/2005
Application #:
09518338
Filing Dt:
03/03/2000
Title:
HIGH DENSITY STORAGE SCHEME FOR SEMICONDUCTOR MEMORY
83
Patent #:
Issue Dt:
02/10/2004
Application #:
09518339
Filing Dt:
03/03/2000
Title:
APPARATUS AND METHOD FOR FACE-TO-FACE CONNECTION OF A DIE TO A SUBSTRATE WITH POLYMER ELECTRODES
84
Patent #:
Issue Dt:
07/16/2002
Application #:
09518508
Filing Dt:
03/03/2000
Title:
METHODS OF FORMING PORTIONS OF TRANSISTOR STRUCTURES, METHODS OF FORMING ARRAY AND PERIPHERAL CIRCUITRY, AND STRUCTURES COMPRISING TRANSISTOR GATES
85
Patent #:
Issue Dt:
01/01/2002
Application #:
09518512
Filing Dt:
03/03/2000
Title:
METHODS OF FORMING CAPACITOR AND BITLINE STRUCTURES
86
Patent #:
Issue Dt:
09/05/2006
Application #:
09518787
Filing Dt:
03/03/2000
Title:
SOFTWARE DISTRIBUTION METHOD AND APPARATUS
87
Patent #:
Issue Dt:
10/17/2000
Application #:
09519226
Filing Dt:
03/06/2000
Title:
Space management for managing high capacity nonvolatile memory
88
Patent #:
Issue Dt:
05/29/2001
Application #:
09520057
Filing Dt:
03/07/2000
Title:
Buffer with fast edge propagation
89
Patent #:
Issue Dt:
06/10/2003
Application #:
09520260
Filing Dt:
03/07/2000
Title:
PARTIAL SLOT COVER FOR ENCAPSULATION PROCESS
90
Patent #:
Issue Dt:
05/29/2001
Application #:
09520288
Filing Dt:
03/07/2000
Title:
Isolation region forming methods
91
Patent #:
Issue Dt:
03/25/2003
Application #:
09520377
Filing Dt:
03/06/2000
Title:
AUTOMATED METHOD OF ATTACHING FLIP CHIP DEVICES TO A SUBSTRATE
92
Patent #:
Issue Dt:
04/30/2002
Application #:
09520492
Filing Dt:
03/08/2000
Publication #:
Pub Dt:
01/31/2002
Title:
METHODS FOR PREPARING RUTHENIUM METAL FILMS
93
Patent #:
Issue Dt:
11/26/2002
Application #:
09520494
Filing Dt:
03/08/2000
Title:
FIELD PROGRAMMABLE LOGIC ARRAYS WITH VERTICAL TRANSISTORS
94
Patent #:
Issue Dt:
02/20/2001
Application #:
09520649
Filing Dt:
03/07/2000
Title:
Memory cell with vertical transistor and buried word and body lines
95
Patent #:
Issue Dt:
04/24/2001
Application #:
09520903
Filing Dt:
03/07/2000
Title:
Identification and verification of a sector within a block of mass storage flash memory
96
Patent #:
Issue Dt:
11/21/2000
Application #:
09520904
Filing Dt:
03/07/2000
Title:
Method and apparatus for decreasing block write operation times performed on nonvolatile memory
97
Patent #:
Issue Dt:
01/09/2001
Application #:
09521419
Filing Dt:
03/08/2000
Title:
Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices
98
Patent #:
Issue Dt:
05/08/2001
Application #:
09521420
Filing Dt:
03/08/2000
Title:
Direct logical block addressing flash memory mass storage architecture
99
Patent #:
Issue Dt:
05/01/2001
Application #:
09521756
Filing Dt:
03/09/2000
Title:
Method and apparatus for reducing bleed currents within a dram array having row-to-column shorts
100
Patent #:
Issue Dt:
11/14/2000
Application #:
09521867
Filing Dt:
03/08/2000
Title:
Floating gate non-volatile memory cell with low erasing voltage and having different potential barriers
Assignor
1
Exec Dt:
06/29/2018
Assignee
1
8000 S. FEDERAL WAY
BOISE, IDAHO 83707
Correspondence name and address
WSGR, C/O QUI LU FLOOD, SENIOR PARALEGAL
ONE MARKET, SPEAR TOWER, SUITE 3300
SAN FRANCISCO, CA 94105

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