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NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:047243/0001   Pages: 959
Recorded: 08/23/2018
Attorney Dkt #:4816.238
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
1
Patent #:
Issue Dt:
07/24/2007
Application #:
09648044
Filing Dt:
08/25/2000
Title:
METHOD AND DEVICE TO REDUCE GATE-INDUCED DRAIN LEAKAGE (GIDL) CURRENT IN THIN GATE OXIDES MOSFETS
2
Patent #:
Issue Dt:
12/26/2006
Application #:
09648271
Filing Dt:
08/25/2000
Title:
FLASH MEMORY ARCHITECTURE WITH SEPARATE STORAGE OF OVERHEAD AND USER DATA
3
Patent #:
Issue Dt:
06/10/2003
Application #:
09648316
Filing Dt:
08/25/2000
Title:
INTEGRATED CIRCUIT DEVICE HAVING REDUCED BOW AND METHOD FOR MAKING SAME
4
Patent #:
Issue Dt:
03/23/2004
Application #:
09648508
Filing Dt:
08/25/2000
Title:
WRITE AND ERASE PROTECTION IN A SYNCHRONOUS MEMORY
5
Patent #:
Issue Dt:
05/15/2001
Application #:
09648585
Filing Dt:
08/25/2000
Title:
METHOD OF FORMING MEMORY CIRCUITRY
6
Patent #:
Issue Dt:
06/08/2004
Application #:
09648696
Filing Dt:
08/25/2000
Title:
RESIDUE-FREE CONTACT OPENINGS AND METHODS FOR FABRICATING SAME
7
Patent #:
Issue Dt:
08/14/2001
Application #:
09648703
Filing Dt:
08/25/2000
Title:
Clock generation circuits and methods
8
Patent #:
Issue Dt:
03/19/2002
Application #:
09648705
Filing Dt:
08/25/2000
Title:
Differential sensing in a memory with reference current
9
Patent #:
Issue Dt:
10/30/2001
Application #:
09648722
Filing Dt:
08/25/2000
Title:
Adjustable pre-charge in a memory
10
Patent #:
Issue Dt:
01/14/2003
Application #:
09648723
Filing Dt:
08/25/2000
Title:
DIFFERENTIAL SENSING IN A MEMORY
11
Patent #:
Issue Dt:
04/01/2003
Application #:
09648880
Filing Dt:
08/25/2000
Title:
MEMORY DEVICE POWER DISTRIBUTION
12
Patent #:
Issue Dt:
07/05/2005
Application #:
09648919
Filing Dt:
08/25/2000
Title:
ELECTROSTATIC DISCHARGE PROTECTION DEVICE
13
Patent #:
Issue Dt:
09/03/2002
Application #:
09648923
Filing Dt:
08/25/2000
Title:
MEMORY DEVICE REDUNDANCY SELECTION HAVING TEST INPUTS
14
Patent #:
Issue Dt:
02/22/2005
Application #:
09649160
Filing Dt:
08/28/2000
Title:
METHOD AND APPARATUS FOR EPOXY LOC DIE ATTACHMENT
15
Patent #:
Issue Dt:
05/14/2002
Application #:
09649192
Filing Dt:
08/28/2000
Title:
Method and apparatus for reducing the lock time of DLL
16
Patent #:
Issue Dt:
07/29/2003
Application #:
09649225
Filing Dt:
08/28/2000
Title:
Methods of fabricating semiconductor substrate-based BGA interconnection
17
Patent #:
Issue Dt:
09/10/2002
Application #:
09649246
Filing Dt:
08/28/2000
Title:
GRADED LDD IMPLANT PROCESS FOR SUB-HALF-MICRON MOS DEVICES
18
Patent #:
Issue Dt:
07/16/2002
Application #:
09649344
Filing Dt:
08/28/2000
Title:
Memory circuit having improved sense-amplifier block and method for forming same
19
Patent #:
Issue Dt:
01/04/2005
Application #:
09649428
Filing Dt:
08/28/2000
Title:
PACKAGED MICROELECTRONIC DEVICES WITH INTERCONNECTING UNITS AND METHODS FOR MANUFACTURING AND USING THE INTERCONNECTING UNITS
20
Patent #:
Issue Dt:
10/16/2001
Application #:
09649448
Filing Dt:
08/25/2000
Title:
Current limiting negative switch circuit
21
Patent #:
Issue Dt:
06/18/2002
Application #:
09649555
Filing Dt:
08/28/2000
Title:
HIGH SPEED LOW POWER INPUT BUFFER
22
Patent #:
Issue Dt:
09/24/2002
Application #:
09649556
Filing Dt:
08/28/2000
Title:
METAL COMPLEXES WITH CHELATING O-AND/OR N-DONOR LIGANDS
23
Patent #:
Issue Dt:
09/17/2002
Application #:
09649691
Filing Dt:
08/28/2000
Title:
SCHEME FOR DELAY LOCKED LOOP RESET PROTECTION
24
Patent #:
Issue Dt:
04/15/2003
Application #:
09649765
Filing Dt:
08/28/2000
Title:
MICROELECTRONIC DEVICE ASSEMBLIES HAVING A SHIELDED INPUT AND METHODS FOR MANUFACTURING AND OPERATING SUCH MICROELECTRONIC DEVICE ASSEMBLIES
25
Patent #:
Issue Dt:
04/30/2002
Application #:
09649828
Filing Dt:
08/29/2000
Title:
Double pass transistor logic with vertical gate transistors
26
Patent #:
Issue Dt:
05/24/2005
Application #:
09649897
Filing Dt:
08/28/2000
Title:
GAS DELIVERY DEVICE FOR IMPROVED DEPOSITION OF DIELECTRIC MATERIAL
27
Patent #:
Issue Dt:
08/13/2002
Application #:
09649907
Filing Dt:
08/30/2000
Title:
OVERLAY TARGET DESIGN METHOD WITH PTICH DETERMINATION TO MINIMIZE IMPACT OF LENS ABERRATIONS
28
Patent #:
Issue Dt:
03/02/2004
Application #:
09649964
Filing Dt:
08/29/2000
Title:
FILM FRAME SUBSTRATE FIXTURE
29
Patent #:
Issue Dt:
03/09/2004
Application #:
09649966
Filing Dt:
08/29/2000
Title:
FILM FRAME SUBSTRATE FIXTURE
30
Patent #:
Issue Dt:
07/16/2002
Application #:
09649970
Filing Dt:
08/28/2000
Title:
METHOD AND APPARATUS FOR PHASE-SPLITTING A CLOCK SIGNAL
31
Patent #:
Issue Dt:
06/24/2003
Application #:
09650071
Filing Dt:
08/29/2000
Title:
METHOD OF FORMING A METAL TO POLYSILICON CONTACT IN OXYGEN ENVIRONMENT
32
Patent #:
Issue Dt:
06/12/2001
Application #:
09650080
Filing Dt:
08/29/2000
Title:
Film frame substrate fixture
33
Patent #:
Issue Dt:
03/25/2003
Application #:
09650081
Filing Dt:
08/29/2000
Title:
SILICON ON INSULATOR DRAM PROCESS UTILIZING BOTH FULLY AND PARTIALLY DEPLETED DEVICES
34
Patent #:
Issue Dt:
11/26/2002
Application #:
09650125
Filing Dt:
08/29/2000
Title:
U-SHAPE TAPE FOR BOC FBGA PACKAGE TO IMPROVE MOLDABILITY
35
Patent #:
Issue Dt:
09/03/2002
Application #:
09650215
Filing Dt:
08/29/2000
Title:
A METHOD OF PREPARING A CAPACITOR ON INTEGRATED CIRCUIT DEVICE CONTAINING ISOLATED DIELECTRIC MATERIAL
36
Patent #:
Issue Dt:
06/10/2003
Application #:
09650231
Filing Dt:
08/29/2000
Title:
METHODS FOR PREPARING RUTHENIUM AND OSMIUM COMPOUNDS
37
Patent #:
Issue Dt:
10/16/2001
Application #:
09650475
Filing Dt:
08/29/2000
Title:
Method and apparatus for adjusting control signal timing in a memory device
38
Patent #:
Issue Dt:
03/05/2002
Application #:
09650534
Filing Dt:
08/30/2000
Title:
Device and method for protecting an integrated circuit during an ESD event
39
Patent #:
Issue Dt:
09/10/2002
Application #:
09650552
Filing Dt:
08/30/2000
Title:
DELAY LINE TAP SETTING OVERRIDE FOR DELAY LOCKED LOOP (DLL) TESTABILITY
40
Patent #:
Issue Dt:
03/12/2002
Application #:
09650567
Filing Dt:
08/30/2000
Title:
Full page increment/decrement burst for DDR SDRAM/SGRAM
41
Patent #:
Issue Dt:
12/24/2002
Application #:
09650600
Filing Dt:
08/30/2000
Title:
MEMORY ADDRESS DECODE ARRAY WITH VERTICAL TRANSISTORS
42
Patent #:
Issue Dt:
03/19/2002
Application #:
09650720
Filing Dt:
08/30/2000
Title:
Method and apparatus for digital delay locked loop circuits
43
Patent #:
Issue Dt:
12/04/2001
Application #:
09650721
Filing Dt:
08/30/2000
Title:
Multi stage refresh control of a memory device
44
Patent #:
Issue Dt:
07/09/2002
Application #:
09650778
Filing Dt:
08/29/2000
Title:
MATERIAL REMOVAL METHOD USING GERMANIUM
45
Patent #:
Issue Dt:
02/11/2003
Application #:
09650779
Filing Dt:
08/29/2000
Title:
METHOD FOR APPLYING UNIFORM PRESSURIZED FILM ACROSS WAFER
46
Patent #:
Issue Dt:
04/08/2003
Application #:
09650784
Filing Dt:
08/30/2000
Title:
AMMONIA GAS PASSIVATION ON NITRIDE ENCAPSULATED DEVICES
47
Patent #:
Issue Dt:
07/09/2002
Application #:
09650796
Filing Dt:
08/30/2000
Title:
METHOD AND APPARATUS FOR MARKING AND IDENTIFYING A DEFECTIVE DIE SITE
48
Patent #:
Issue Dt:
08/27/2002
Application #:
09650840
Filing Dt:
08/30/2000
Title:
UPHILL SCREEN PRINTING IN THE MANUFACTURING OF MICROELECTRONIC COMPONENTS
49
Patent #:
Issue Dt:
08/07/2001
Application #:
09650879
Filing Dt:
08/30/2000
Title:
Apparatus and method for programming voltage protection in a non-volatile memory system
50
Patent #:
Issue Dt:
10/14/2003
Application #:
09651040
Filing Dt:
08/30/2000
Title:
METHOD AND APPARATUS FOR ELECTROLYTIC PLATING OF SUREFACE METALS
51
Patent #:
Issue Dt:
01/15/2002
Application #:
09651063
Filing Dt:
08/30/2000
Title:
Apparatus and method for programming voltage protection in a non-volatile memory system
52
Patent #:
Issue Dt:
04/17/2007
Application #:
09651159
Filing Dt:
08/30/2000
Title:
OVERFLOW DETECTION AND CLAMPING WITH PARALLEL OPERAND PROCESSING FOR FIXED-POINT MULTIPLIERS
53
Patent #:
Issue Dt:
01/07/2003
Application #:
09651199
Filing Dt:
08/30/2000
Title:
MEMORY CELL HAVING A VERTICAL TRANSISTOR WITH BURIED SOURCE/DRAIN AND DUAL GATES
54
Patent #:
Issue Dt:
09/03/2002
Application #:
09651325
Filing Dt:
08/30/2000
Title:
WAFER PROCESSING APPARATUS
55
Patent #:
Issue Dt:
07/30/2002
Application #:
09651330
Filing Dt:
08/29/2000
Title:
HEAT SINK CHIP PACKAGE
56
Patent #:
Issue Dt:
07/10/2001
Application #:
09651332
Filing Dt:
08/31/2000
Title:
Semiconductor programmable test arrangement such as an antifuse ID circuit having common programming switches
57
Patent #:
Issue Dt:
10/08/2002
Application #:
09651380
Filing Dt:
08/29/2000
Title:
THIN DIELECTRIC FILMS FOR DRAM STORAGE CAPACITORS
58
Patent #:
Issue Dt:
05/27/2003
Application #:
09651391
Filing Dt:
08/29/2000
Title:
FUSE READ SEQUENCE FOR AUTO REFRESH POWER REDUCTION
59
Patent #:
Issue Dt:
05/11/2004
Application #:
09651422
Filing Dt:
08/30/2000
Title:
METHODS OF FORMING INSULATIVE MATERIAL AGAINST CONDUCTIVE STRUCTURES
60
Patent #:
Issue Dt:
06/10/2003
Application #:
09651448
Filing Dt:
08/30/2000
Title:
MICROELECTRONIC ASSEMBLY WITH PRE-DISPOSED FILL MATERIAL AND ASSOCIATED METHOD OF MANUFACTURE
61
Patent #:
Issue Dt:
09/25/2001
Application #:
09651460
Filing Dt:
08/30/2000
Title:
Semiconductor device including combed bond pad opening, assemblies and methods
62
Patent #:
Issue Dt:
11/06/2001
Application #:
09651461
Filing Dt:
08/30/2000
Title:
Method of attaching a leadframe to singulated semiconductor dice
63
Patent #:
Issue Dt:
10/08/2002
Application #:
09651462
Filing Dt:
08/30/2000
Title:
UTILIZATION OF DISAPPEARING SILICON HARD MASK FOR FABRICATION OF SEMICONDUCTOR STRUCTURES
64
Patent #:
Issue Dt:
07/30/2002
Application #:
09651472
Filing Dt:
08/30/2000
Title:
ENHANCED FUSE CONFIGURATIONS FOR LOW-VOLTAGE FLASH MEMORIES
65
Patent #:
Issue Dt:
09/17/2002
Application #:
09651475
Filing Dt:
08/30/2000
Title:
NOVEL HIGH-K DIELECTRIC MATERIALS AND PROCESSES FOR MANUFACTURING THEM
66
Patent #:
Issue Dt:
09/30/2003
Application #:
09651478
Filing Dt:
08/30/2000
Title:
ENHANCED PROTECTION FOR INPUT BUFFERS OF LOW-VOLTAGE FLASH MEMORIES
67
Patent #:
Issue Dt:
08/28/2001
Application #:
09651489
Filing Dt:
08/30/2000
Title:
Apparatus and method for facilitating circuit board processing
68
Patent #:
Issue Dt:
06/07/2005
Application #:
09651620
Filing Dt:
08/30/2000
Title:
METHOD FOR THE FORMATION OF RUSIXOY-CONTAINING BARRIER LAYERS FOR HIGH-K DIELECTRICS
69
Patent #:
Issue Dt:
01/28/2003
Application #:
09651631
Filing Dt:
08/30/2000
Title:
INTEGRATED CIRCUIT COMPARATOR OR AMPLIFIER
70
Patent #:
Issue Dt:
02/10/2004
Application #:
09651699
Filing Dt:
08/30/2000
Title:
DEVICES CONTAINING PLATINUM-RHODIUM LAYERS AND METHODS
71
Patent #:
Issue Dt:
07/11/2006
Application #:
09651779
Filing Dt:
08/30/2000
Title:
METHODS AND APPARATUS FOR REMOVING CONDUCTIVE MATERIAL FROM A MICROELECTRONIC SUBSTRATE
72
Patent #:
Issue Dt:
07/05/2005
Application #:
09651790
Filing Dt:
08/30/2000
Title:
RESIDUE FREE OVERLAY TARGET
73
Patent #:
Issue Dt:
12/23/2003
Application #:
09651815
Filing Dt:
08/30/2000
Title:
METHODS FOR FORMING VOID REGIONS, DIELECTRIC REGIONS AND CAPACITOR CONSTRUCTIONS
74
Patent #:
Issue Dt:
05/28/2002
Application #:
09651816
Filing Dt:
08/30/2000
Title:
SEMICONDUCTOR PROCESSING METHODS OF FORMING A PLURALITY OF CAPACITORS ON A SUBSTRATE, BIT LINE CONTACTS AND METHOD OF FORMING BIT LINE CONTACTS
75
Patent #:
Issue Dt:
12/07/2004
Application #:
09651858
Filing Dt:
08/30/2000
Title:
METHOD AND SYSTEM FOR STORING DEVICE TEST INFORMATION ON A SEMICONDUCTOR DEVICE USING ON-DEVICE LOGIC FOR DETERMINATION OF TEST RESULTS
76
Patent #:
Issue Dt:
09/17/2002
Application #:
09651861
Filing Dt:
08/30/2000
Title:
METHODS OF FABRICATING BURIED DIGIT LINES AND SEMICONDUCTOR DEVICES INCLUDING SAME
77
Patent #:
Issue Dt:
08/31/2004
Application #:
09651871
Filing Dt:
08/31/2000
Title:
GAS PULSING FOR ETCH PROFILE CONTROL
78
Patent #:
Issue Dt:
09/17/2002
Application #:
09651997
Filing Dt:
08/31/2000
Title:
METHOD AND APPARATUS FOR MAGNETIC SHIELDING OF AN INTEGRATED CIRCUIT
79
Patent #:
Issue Dt:
06/28/2005
Application #:
09652003
Filing Dt:
08/31/2000
Title:
METHOD AND APPARATUS FOR CONNECTING A MASSIVELY PARALLEL PROCESSOR ARRAY TO A MEMORY ARRAY IN A BIT SERIAL MANNER
80
Patent #:
Issue Dt:
01/21/2003
Application #:
09652059
Filing Dt:
08/31/2000
Title:
METHOD OF ENHANCING THE CONDUCTIVITY OF A CONDUCTIVE SURFACE
81
Patent #:
Issue Dt:
12/02/2003
Application #:
09652060
Filing Dt:
08/31/2000
Title:
METHOD OF FORMING A SEMICONDUCTOR CHIP CARRIER
82
Patent #:
Issue Dt:
03/18/2003
Application #:
09652070
Filing Dt:
08/31/2000
Title:
METHOD OF SELECTIVELY FORMING LOCAL INTERCONNECTS USING DESIGN RULES
83
Patent #:
Issue Dt:
05/24/2005
Application #:
09652071
Filing Dt:
08/31/2000
Title:
APPARATUS FOR DETECTING MIXED INTERLACED AND PROGRESSIVE ORIGINAL SOURCES IN A VIDEO SEQUENCE
84
Patent #:
Issue Dt:
03/25/2003
Application #:
09652076
Filing Dt:
08/31/2000
Title:
OVERMOLDING ENCAPSULATION PROCESS
85
Patent #:
Issue Dt:
04/09/2002
Application #:
09652188
Filing Dt:
08/31/2000
Title:
Use of selective ozone TEOS oxide to create variable thickness layers and spacers
86
Patent #:
Issue Dt:
02/11/2003
Application #:
09652208
Filing Dt:
08/31/2000
Title:
ELECTROLESS DEPOSITION OF DOPED NOBLE METALS AND NOBLE METAL ALLOYS
87
Patent #:
Issue Dt:
09/07/2004
Application #:
09652216
Filing Dt:
08/30/2000
Title:
METHOD AND APPARATUS FOR REDUCING SUBSTRATE BIAS VOLTAGE DROP
88
Patent #:
Issue Dt:
08/14/2001
Application #:
09652217
Filing Dt:
08/30/2000
Title:
Latched row or column select enable driver
89
Patent #:
Issue Dt:
03/16/2004
Application #:
09652218
Filing Dt:
08/30/2000
Title:
WAFER ALIGNMENT SYSTEM
90
Patent #:
Issue Dt:
05/13/2003
Application #:
09652225
Filing Dt:
08/29/2000
Title:
METHOD AND APPARATUS FOR ATTACHING A WORKPIECE TO A WORKPIECE SUPPORT
91
Patent #:
Issue Dt:
08/14/2001
Application #:
09652274
Filing Dt:
08/31/2000
Title:
Method and apparatus providing redundancy for fabricating highly reliable memory modules
92
Patent #:
Issue Dt:
12/17/2002
Application #:
09652320
Filing Dt:
08/31/2000
Title:
METHOD OF FORMING LIGHTLY DOPED DRAIN MOS TRANSISTOR INCLUDING FORMING SPACERS ON GATE ELECTRODE PATTERN BEFORE EXPOSING GATE INSULATOR
93
Patent #:
Issue Dt:
08/17/2004
Application #:
09652364
Filing Dt:
08/31/2000
Title:
PHASE DETECTOR FOR ALL-DIGITAL PHASE LOCKED AND DELAY LOCKED LOOPS
94
Patent #:
Issue Dt:
10/07/2003
Application #:
09652429
Filing Dt:
08/31/2000
Title:
GATE DIELECTRIC ANTIFUSE CIRCUITS AND METHODS FOR OPERATING SAME
95
Patent #:
Issue Dt:
09/18/2007
Application #:
09652495
Filing Dt:
08/31/2000
Title:
CARRIER FOR WAFER-SCALE PACKAGE AND WAFER-SCALE PACKAGE INCLUDING THE CARRIER
96
Patent #:
Issue Dt:
04/15/2003
Application #:
09652530
Filing Dt:
08/31/2000
Title:
METHODS OF ENHANCING SELECTIVITY OF ETCHING SILICON DIOXIDE RELATIVE TO ONE OR MORE ORGANIC SUBSTANCES
97
Patent #:
Issue Dt:
07/09/2002
Application #:
09652531
Filing Dt:
08/31/2000
Title:
METHODS OF POLISHING MICROELECTRONIC SUBSTRATES, AND METHODS OF POLISHING WAFERS
98
Patent #:
Issue Dt:
07/16/2002
Application #:
09652532
Filing Dt:
08/31/2000
Title:
CAPACITOR FABRICATION METHODS AND CAPACITOR CONSTRUCTIONS
99
Patent #:
Issue Dt:
08/22/2006
Application #:
09652533
Filing Dt:
08/31/2000
Title:
DEPOSITION METHODS AND APPARATUSES PROVIDING SURFACE ACTIVATION
100
Patent #:
Issue Dt:
12/14/2004
Application #:
09652550
Filing Dt:
08/31/2000
Title:
METHODS OF FORMING AN ISOLATION TRENCH IN A SEMICONDUCTOR, METHODS OF FORMING AN ISOLATION TRENCH IN A SURFACE OF A SILICON WAFER, METHODS OF FORMING AN ISOLATION TRENCH-ISOLATED TRANSISTOR, TRENCH-ISOLATED TRANSISTOR, TRENCH ISOLATION STRUCTURES FORMED IN A SEMICO
Assignor
1
Exec Dt:
06/29/2018
Assignee
1
8000 S. FEDERAL WAY
BOISE, IDAHO 83707
Correspondence name and address
WSGR, C/O QUI LU FLOOD, SENIOR PARALEGAL
ONE MARKET, SPEAR TOWER, SUITE 3300
SAN FRANCISCO, CA 94105

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