|
|
Patent #:
|
|
Issue Dt:
|
02/04/2003
|
Application #:
|
09652557
|
Filing Dt:
|
08/31/2000
|
Title:
|
JUNCTION-ISOLATED DEPLETION MODE FERROELECTRIC MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
10/09/2001
|
Application #:
|
09652578
|
Filing Dt:
|
08/31/2000
|
Title:
|
Die architecture accommodating high-speed semiconductor devices
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2002
|
Application #:
|
09652584
|
Filing Dt:
|
08/31/2000
|
Title:
|
DIE ARCHITECTURE ACCOMMODATING HIGH-SPEED SEMICONDUCTOR DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/09/2001
|
Application #:
|
09652586
|
Filing Dt:
|
08/31/2000
|
Title:
|
Die architecture accommodating high-speed semiconductor devices
|
|
|
Patent #:
|
|
Issue Dt:
|
11/06/2001
|
Application #:
|
09652587
|
Filing Dt:
|
08/31/2000
|
Title:
|
Die architecture accommodating high-speed semiconductor devices
|
|
|
Patent #:
|
|
Issue Dt:
|
10/24/2006
|
Application #:
|
09652619
|
Filing Dt:
|
08/31/2000
|
Title:
|
METHOD FOR FORMING A METALLIZATION LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2002
|
Application #:
|
09652622
|
Filing Dt:
|
08/31/2000
|
Title:
|
Double-edged clocked storage device and method
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|
|
Patent #:
|
|
Issue Dt:
|
11/25/2003
|
Application #:
|
09652639
|
Filing Dt:
|
08/31/2000
|
Title:
|
METHODS AND APPARATUSES FOR MAKING AND USING PLANARIZING PADS FOR MECHANICAL AND CHEMICAL-MECHANICAL PLANARIZATION OF MICROELECTRONIC SUBSTRATES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/2003
|
Application #:
|
09652723
|
Filing Dt:
|
08/31/2000
|
Title:
|
METHOD OF PROVIDING AN OXIDE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/30/2002
|
Application #:
|
09652746
|
Filing Dt:
|
08/31/2000
|
Title:
|
METHOD OF MAKING A FIELD EMISSION DEVICE WITH BUFFER LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
09/17/2002
|
Application #:
|
09652774
|
Filing Dt:
|
08/31/2000
|
Title:
|
SINGLE-LEVEL MASKING WITH PARTIAL USE OF ATTENUATED PHASE-SHIFT TECHNOLOGY
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2001
|
Application #:
|
09652775
|
Filing Dt:
|
08/31/2000
|
Title:
|
Memory with combined synchronous burst and bus efficient functionality
|
|
|
Patent #:
|
|
Issue Dt:
|
05/27/2003
|
Application #:
|
09652835
|
Filing Dt:
|
08/31/2000
|
Title:
|
METHOD TO ELIMINATE STRIATIONS AND SURFACE ROUGHNESS CAUSED BY DRY ETCH
|
|
|
Patent #:
|
|
Issue Dt:
|
11/20/2001
|
Application #:
|
09652839
|
Filing Dt:
|
08/31/2000
|
Title:
|
Die architecture accommodating high-speed semiconductor devices
|
|
|
Patent #:
|
|
Issue Dt:
|
01/07/2003
|
Application #:
|
09652864
|
Filing Dt:
|
08/31/2000
|
Title:
|
SOI CMOS DEVICE WITH REDUCED DIBL
|
|
|
Patent #:
|
|
Issue Dt:
|
06/03/2003
|
Application #:
|
09652877
|
Filing Dt:
|
08/31/2000
|
Title:
|
DEPLETION MODE FERROELECTRIC MEMORY DEVICE AND METHOD OF WRITING TO AND READING FROM THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
07/18/2006
|
Application #:
|
09652878
|
Filing Dt:
|
08/31/2000
|
Title:
|
SUBPAD SUPPORT WITH A RELEASABLE SUBPAD SECURING ELEMENTAND POLISHING APPARATUS INCLUDING THE SUBPAD SUPPORT
|
|
|
Patent #:
|
|
Issue Dt:
|
10/08/2002
|
Application #:
|
09652880
|
Filing Dt:
|
08/31/2000
|
Title:
|
MULTI-CHIP MODULE EMPLOYING A CARRIER SUBSTRATE WITH MICROMACHINED ALIGNMENT STRUCTURES AND METHOD OF FORMING
|
|
|
Patent #:
|
|
Issue Dt:
|
02/25/2003
|
Application #:
|
09652907
|
Filing Dt:
|
08/31/2000
|
Title:
|
DIELECTICE FILMS AND CAPACITOR STRUCTURES INCLUDING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
12/10/2002
|
Application #:
|
09652970
|
Filing Dt:
|
08/31/2000
|
Title:
|
HIGH-PRESSURE ANNEAL PROCESS FOR INTEGRATED CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/13/2004
|
Application #:
|
09652991
|
Filing Dt:
|
08/31/2000
|
Title:
|
COMPOSITIONS FOR DISSOLUTION OF LOW-K DIELECTRIC FILMS, AND METHODS OF USE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/04/2001
|
Application #:
|
09652996
|
Filing Dt:
|
08/31/2000
|
Title:
|
Die architecture accommodating high-speed semiconductor devices
|
|
|
Patent #:
|
|
Issue Dt:
|
07/01/2003
|
Application #:
|
09653074
|
Filing Dt:
|
08/31/2000
|
Title:
|
ARRAY ARCHITECTURE FOR DEPLETION MODE FERROELECTRIC MEMORY
DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/10/2003
|
Application #:
|
09653096
|
Filing Dt:
|
08/31/2000
|
Title:
|
DIELECTRIC LAYER FOR A SEMICONDUCTOR DEVICE HAVING LESS CURRENT LEAKAGE AND INCREASED CAPACITANCE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2003
|
Application #:
|
09653127
|
Filing Dt:
|
08/31/2000
|
Title:
|
BALL GRID ARRAY PACKAGES WITH THERMALLY CONDUCTIVE CONTAINERS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/09/2003
|
Application #:
|
09653138
|
Filing Dt:
|
08/31/2000
|
Title:
|
METAL LINE AND METHOD OF SUPPRESSING VOID FORMATION THEREIN
|
|
|
Patent #:
|
|
Issue Dt:
|
05/15/2007
|
Application #:
|
09653149
|
Filing Dt:
|
08/31/2000
|
Title:
|
CAPACITOR FABRICATION METHODS INCLUDING FORMING A CONDUCTIVE LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
03/11/2003
|
Application #:
|
09653151
|
Filing Dt:
|
08/31/2000
|
Title:
|
METHODS OF FORMING CONDUCTIVE INTERCONNECTS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/11/2003
|
Application #:
|
09653153
|
Filing Dt:
|
08/31/2000
|
Title:
|
METHOD, STRUCTURE AND PROCESS FLOW TO REDUCE LINE-LINE CAPACITANCE WITH LOW-K MATERIAL
|
|
|
Patent #:
|
|
Issue Dt:
|
06/25/2002
|
Application #:
|
09653249
|
Filing Dt:
|
08/31/2000
|
Title:
|
SINGLE ENDED DATA BUS EQUILIBRATION SCHEME
|
|
|
Patent #:
|
|
Issue Dt:
|
10/10/2006
|
Application #:
|
09653272
|
Filing Dt:
|
08/31/2000
|
Title:
|
METHOD FOR USING DATA REGARDING MANUFACTURING PROCEDURES INTEGRATED CIRCUITS (IC'S) HAVE UNDERGONE, SUCH AS REPAIRS, TO SELECT PROCEDURES THE IC'S WILL UNDERGO, SUCH AS ADDITIONAL REPAIRS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/18/2003
|
Application #:
|
09653298
|
Filing Dt:
|
08/31/2000
|
Title:
|
METHOD OF FORMING AN ULTRA THIN DIELECTRIC FILM
|
|
|
Patent #:
|
|
Issue Dt:
|
01/01/2002
|
Application #:
|
09653356
|
Filing Dt:
|
08/31/2000
|
Title:
|
Method to electrically program antifuses
|
|
|
Patent #:
|
|
Issue Dt:
|
06/29/2004
|
Application #:
|
09653366
|
Filing Dt:
|
09/01/2000
|
Title:
|
METHOD FOR FABRICATING A SEMICONDUCTOR COMPONENT WITH EXTERNAL CONTACT POLYMER SUPPORT LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
04/22/2003
|
Application #:
|
09653392
|
Filing Dt:
|
08/31/2000
|
Title:
|
SLURRY FOR USE IN POLISHING SEMICONDUCTOR DEVICE CONDUCTIVE STRUCTURES THAT INCLUDE COPPER AND TUNGSTEN AND POLISHING METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/30/2002
|
Application #:
|
09653423
|
Filing Dt:
|
08/31/2000
|
Title:
|
METHOD OF CO-DEPOSITION TO FORM ULTRA-SHALLOW JUNCTIONS IN MOS DEVICES USING ELECTROLESS OR ELECTRODELPOSITION
|
|
|
Patent #:
|
|
Issue Dt:
|
10/28/2003
|
Application #:
|
09653473
|
Filing Dt:
|
08/31/2000
|
Title:
|
USE OF A REFERENCE FIDUCIAL ON A SEMICONDUCTOR PACKAGE TO MONITOR AND CONTROL A SINGULATION METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
07/15/2003
|
Application #:
|
09653495
|
Filing Dt:
|
08/31/2000
|
Title:
|
INTEGRATED VOLATILE AND NON-VOLATILE MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
11/04/2003
|
Application #:
|
09653513
|
Filing Dt:
|
08/31/2000
|
Title:
|
DEVICES CONTAINING ZIRCONIUM-PLATINUM-CONTAINING MATERIALS AND METHODS FOR PREPARING SUCH MATERIALS AND DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/17/2002
|
Application #:
|
09653522
|
Filing Dt:
|
08/31/2000
|
Title:
|
SELF-ALIGNED PECVD ETCH MASK
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2002
|
Application #:
|
09653523
|
Filing Dt:
|
08/31/2000
|
Title:
|
ULTRA THIN TCS (SIC14) CELL NITRIDE FOR DRAM CAPACITOR WITH DCS (SIH2C12) INTERFACE SEEDING LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
12/17/2002
|
Application #:
|
09653539
|
Filing Dt:
|
08/31/2000
|
Title:
|
DISTRIBUTED CELL PLATE AND/OR DIGIT EQUILIBRATE VOLTAGE GENERATOR
|
|
|
Patent #:
|
|
Issue Dt:
|
04/06/2004
|
Application #:
|
09653541
|
Filing Dt:
|
08/31/2000
|
Title:
|
MAGNETIC SHIELDING FOR INTEGRATED CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/01/2003
|
Application #:
|
09653553
|
Filing Dt:
|
08/31/2000
|
Title:
|
ATOMIC LAYER DOPING APPARATUS AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/2002
|
Application #:
|
09653554
|
Filing Dt:
|
08/31/2000
|
Title:
|
METHOD FOR SELECTIVE ETCHING OF OXIDES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/23/2003
|
Application #:
|
09653558
|
Filing Dt:
|
08/31/2000
|
Title:
|
SHIELDED PC BOARD FOR MAGNETICALLY SENSITIVE INTEGRATED CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/09/2003
|
Application #:
|
09653560
|
Filing Dt:
|
08/31/2000
|
Title:
|
SUBTRACTIVE METALLIZATION STRUCTURE AND METHOD OF MAKING
|
|
|
Patent #:
|
|
Issue Dt:
|
10/24/2006
|
Application #:
|
09653561
|
Filing Dt:
|
08/31/2000
|
Title:
|
METHOD AND MATERIAL FOR REMOVING ETCH RESIDUE FROM HIGH ASPECT RATIO CONTACT SURFACES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/24/2002
|
Application #:
|
09653596
|
Filing Dt:
|
08/31/2000
|
Title:
|
SPUTTERED INSULATING LAYER FOR WORDLINE STACKS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/30/2002
|
Application #:
|
09653638
|
Filing Dt:
|
08/31/2000
|
Title:
|
SELECTIVE POLYSILICON STUD GROWTH
|
|
|
Patent #:
|
|
Issue Dt:
|
09/07/2004
|
Application #:
|
09653640
|
Filing Dt:
|
08/31/2000
|
Title:
|
INTEGRATED CIRCUIT HAVING A BARRIER STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/13/2002
|
Application #:
|
09654098
|
Filing Dt:
|
08/31/2000
|
Title:
|
CIRCUIT CONFIGURATION FOR ENHANCING PERFORMANCE CHARACTERISTICS OF FABRICATED DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/08/2003
|
Application #:
|
09654099
|
Filing Dt:
|
08/31/2000
|
Title:
|
VOLTAGE REGULATOR AND DATA PATH FOR A MEMORY DEVICE
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|
|
Patent #:
|
|
Issue Dt:
|
10/14/2003
|
Application #:
|
09654107
|
Filing Dt:
|
08/31/2000
|
Title:
|
PRECISION FIDUCIAL
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2002
|
Application #:
|
09654226
|
Filing Dt:
|
08/30/2000
|
Title:
|
METHOD AND SYSTEM FOR CONTROLLING THE DUTY CYCLE OF A CLOCK SIGNAL
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2002
|
Application #:
|
09655000
|
Filing Dt:
|
08/31/2000
|
Title:
|
DRAM FABRICATED ON A SILICON-ON-INSULATOR (SOI) SUBSTRATE HAVING BI-LEVEL DIGIT LINES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/03/2003
|
Application #:
|
09655002
|
Filing Dt:
|
08/31/2000
|
Title:
|
APPARATUS AND METHODS OF AUTOMATED WAFER-GRINDING USING GRINDING SURFACE POSITION MONITORING
|
|
|
Patent #:
|
|
Issue Dt:
|
05/18/2004
|
Application #:
|
09655004
|
Filing Dt:
|
08/31/2000
|
Title:
|
METHOD AND SYSTEM FOR SUBSTANTIALLY REGISTERLESS PROCESSING
|
|
|
Patent #:
|
|
Issue Dt:
|
12/17/2002
|
Application #:
|
09655034
|
Filing Dt:
|
09/05/2000
|
Title:
|
LOW PROFILE SEMICONDUCTOR PACKAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/02/2002
|
Application #:
|
09655167
|
Filing Dt:
|
09/05/2000
|
Title:
|
Method and apparatus for anticipatory selection of external or internal addresses in a synchronous memory device
|
|
|
Patent #:
|
|
Issue Dt:
|
11/05/2002
|
Application #:
|
09655934
|
Filing Dt:
|
09/06/2000
|
Title:
|
SEMICONDUCTOR MEMORY DEVICE WITH SIMULTANEOUSLY FORMED ELECTRODE AND INTERCONNECTION LAYERS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/16/2002
|
Application #:
|
09658327
|
Filing Dt:
|
09/08/2000
|
Title:
|
CIRCUIT AND METHOD TO PREVENT INADVERTENT TEST MODE ENTRY
|
|
|
Patent #:
|
|
Issue Dt:
|
09/11/2001
|
Application #:
|
09658334
|
Filing Dt:
|
09/08/2000
|
Title:
|
Circuit to prevent inadvertent test mode entry
|
|
|
Patent #:
|
|
Issue Dt:
|
09/17/2002
|
Application #:
|
09659247
|
Filing Dt:
|
09/11/2000
|
Title:
|
APPARATUS FOR TESTING REDUNDANT ELEMENTS IN A PACKAGED SEMICONDUCTOR MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/12/2002
|
Application #:
|
09659334
|
Filing Dt:
|
09/12/2000
|
Title:
|
Active termination in a multidrop memory system
|
|
|
Patent #:
|
|
Issue Dt:
|
06/05/2001
|
Application #:
|
09659471
|
Filing Dt:
|
09/11/2000
|
Title:
|
Apparatus for on-board programming of serial eeproms
|
|
|
Patent #:
|
|
Issue Dt:
|
01/07/2003
|
Application #:
|
09660303
|
Filing Dt:
|
09/12/2000
|
Title:
|
METHOD FOR PAGE MODE WRITING IN AN ELECTRICALLY ERASABLE/PROGRAMMABLE NON-VOLATILE MEMORY AND CORRESPONDING ARCHITECTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/03/2004
|
Application #:
|
09660838
|
Filing Dt:
|
09/13/2000
|
Title:
|
FLASH MEMORY SYSTEM AND METHOD IMPLEMENTING LBA TO PBA CORRELATION WITHIN FLASH MEMORY ARRAY
|
|
|
Patent #:
|
|
Issue Dt:
|
01/03/2006
|
Application #:
|
09661540
|
Filing Dt:
|
09/14/2000
|
Title:
|
BIOS LOCK CD-ROM ENDCODE/DECODE DRIVER
|
|
|
Patent #:
|
|
Issue Dt:
|
08/27/2002
|
Application #:
|
09662407
|
Filing Dt:
|
09/14/2000
|
Title:
|
STEPPED PHOTORESIST PROFILE AND OPENING FORMED USING THE PROFILE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/02/2002
|
Application #:
|
09663035
|
Filing Dt:
|
09/15/2000
|
Title:
|
Method and apparatus for synchronous data transfers in a memory device with selectable data or address paths
|
|
|
Patent #:
|
|
Issue Dt:
|
07/03/2001
|
Application #:
|
09665339
|
Filing Dt:
|
09/19/2000
|
Title:
|
Method and apparatus for setting the common mode level of a differential output
|
|
|
Patent #:
|
|
Issue Dt:
|
05/18/2004
|
Application #:
|
09665430
|
Filing Dt:
|
09/19/2000
|
Title:
|
THERMALLY CONDUCTIVE ADHESIVE TAPE FOR SEMICONDUCTOR DEVICES AND METHOD FOR USING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
02/28/2006
|
Application #:
|
09665826
|
Filing Dt:
|
09/20/2000
|
Title:
|
METHOD AND APPARATUS TO IMPROVE THE PROTECTION OF INFORMATION PRESENTED BY A COMPUTER
|
|
|
Patent #:
|
|
Issue Dt:
|
06/08/2004
|
Application #:
|
09665922
|
Filing Dt:
|
09/20/2000
|
Title:
|
METHOD AND APPARATUS FOR A LOW LATENCY SOURCE-SYNCHRONOUS ADDRESS RECEIVER FOR A HOST SYSTEM BUS IN A MEMORY CONTROLLER
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/2003
|
Application #:
|
09668922
|
Filing Dt:
|
09/25/2000
|
Title:
|
SHIELDING ARRANGEMENT TO PROTECT A CIRCUIT FROM STRAY MAGNETIC FIELDS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/01/2001
|
Application #:
|
09669093
|
Filing Dt:
|
09/25/2000
|
Title:
|
Semiconductor processing methods, and methods of forming
capacitor constructions
|
|
|
Patent #:
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Issue Dt:
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06/17/2003
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Application #:
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09669228
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Filing Dt:
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09/25/2000
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Title:
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MODULAR DRIVE CAGE ASSEMBLY
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Patent #:
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Issue Dt:
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07/22/2003
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Application #:
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09669281
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Filing Dt:
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09/26/2000
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Title:
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PROGRAMMABLE MEMORY ADDRESS DECODE ARRAY WITH VERTICAL TRANSISTORS
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Patent #:
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Issue Dt:
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08/20/2002
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Application #:
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09670248
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Filing Dt:
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09/26/2000
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Title:
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NONVOLATILE MEMORY AND HIGH SPEED MEMORY TEST METHOD
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Patent #:
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Issue Dt:
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08/28/2001
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Application #:
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09670471
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Filing Dt:
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09/26/2000
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Title:
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Memory test method and nonvolatile memory with low error masking probability
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Patent #:
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Issue Dt:
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05/22/2001
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Application #:
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09670982
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Filing Dt:
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09/26/2000
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Title:
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RF powered plasma enhanced chemical vapor deposition reactor and methods of effecting plasma enhanced chemical vapor deposition
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Patent #:
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Issue Dt:
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08/05/2003
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Application #:
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09672690
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Filing Dt:
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09/29/2000
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Title:
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A METHOD FOR MAKING A PACKAGED SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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09/11/2001
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Application #:
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09674395
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Filing Dt:
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10/30/2000
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Title:
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Monolithically integrated selector for electrically programmable memory cell devices
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Patent #:
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Issue Dt:
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08/13/2002
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Application #:
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09675072
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Filing Dt:
|
09/28/2000
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Title:
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INTERCONNECT AND SYSTEM FOR TESTING BUMPED SEMICONDUCTOR COMPONENTS WITH ON-BOARD MULTIPLEX CIRCUITRY FOR EXPANDING TESTER RESOURCES
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Patent #:
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Issue Dt:
|
02/25/2003
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Application #:
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09675117
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Filing Dt:
|
09/28/2000
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Title:
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SEMICONDUCTOR DEVICE HAVING INCREASED BREAKDOWN VOLTAGE AND METHOD OF FABRICATING SAME
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Patent #:
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Issue Dt:
|
01/23/2007
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Application #:
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09675286
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Filing Dt:
|
09/29/2000
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Title:
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RUNTIME PREDICTION FRAMEWORK FOR CPU INTENSIVE APPLICATIONS
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Patent #:
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Issue Dt:
|
03/25/2003
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Application #:
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09675635
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Filing Dt:
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09/29/2000
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Title:
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RUTHENIUM AND RUTHENIUM DIOXIDE REMOVAL METHOD AND MATERIAL
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Patent #:
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Issue Dt:
|
02/11/2003
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Application #:
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09675901
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Filing Dt:
|
09/28/2000
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Title:
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A METHOD FOR FORMING A FIELD EFFECT TRANSISTOR HAVING INCREASED BREAKDOWN VOLTAGE
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Patent #:
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Issue Dt:
|
03/04/2008
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Application #:
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09676175
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Filing Dt:
|
09/29/2000
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Title:
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EXECUTING A TRANSLATED BLOCK OF INSTRUCTIONS AND BRANCHING TO CORRECTION CODE WHEN EXPECTED TOP OF STACK DOES NOT MATCH ACTUAL TOP OF STACK TO ADJUST STACK AT EXECUTION TIME TO CONTINUE EXECUTING WITHOUT RESTARTING TRANSLATING
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Patent #:
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Issue Dt:
|
05/07/2002
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Application #:
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09676313
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Filing Dt:
|
09/29/2000
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Title:
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Clock splitter circuit to generate synchronized clock and inverted clock
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Patent #:
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Issue Dt:
|
05/08/2007
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Application #:
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09676556
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Filing Dt:
|
09/30/2000
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Title:
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EFFICIENT IMPLEMENTATION OF N-POINT DCT, N-POINT IDCT, SA-DCT AND SA-IDCT ALGORITHMS
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Patent #:
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Issue Dt:
|
11/12/2002
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Application #:
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09677267
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Filing Dt:
|
09/26/2000
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Title:
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METHOD FOR FORMING AN ETCH MASK DURING THE MANUFACTURE OF A SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
|
06/12/2001
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Application #:
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09677364
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Filing Dt:
|
10/02/2000
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Title:
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Column decode circuits and apparatus
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Patent #:
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Issue Dt:
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02/27/2007
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Application #:
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09677478
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Filing Dt:
|
10/02/2000
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Title:
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PLASMA ETCHING METHODS
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|
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Patent #:
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Issue Dt:
|
01/07/2003
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Application #:
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09678468
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Filing Dt:
|
10/02/2000
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Title:
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FIELD EFFECT TRANSISTORS, FIELD EMISSION APPARATUSES, AND A THIN FILM TRANSISTOR
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Patent #:
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|
Issue Dt:
|
03/19/2002
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Application #:
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09678941
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Filing Dt:
|
10/03/2000
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Title:
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Method and apparatus for reducing induced switching transients
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Patent #:
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|
Issue Dt:
|
02/18/2003
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Application #:
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09679095
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Filing Dt:
|
10/04/2000
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Title:
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CONTROLLING PACKAGING ENCAPSULANT LEAKAGE
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Patent #:
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Issue Dt:
|
08/21/2001
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Application #:
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09679393
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Filing Dt:
|
10/03/2000
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Title:
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Methods of forming SOI insulator layers, methods of forming transistor devices, and semiconductor devices and assemblies
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Patent #:
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Issue Dt:
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01/14/2003
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Application #:
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09679940
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Filing Dt:
|
10/04/2000
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Title:
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METHOD OF MAKING CHIP SCALE PACKAGE WITH HEAT SPREADER
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