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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:047243/0001   Pages: 959
Recorded: 08/23/2018
Attorney Dkt #:4816.238
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
1
Patent #:
Issue Dt:
02/04/2003
Application #:
09652557
Filing Dt:
08/31/2000
Title:
JUNCTION-ISOLATED DEPLETION MODE FERROELECTRIC MEMORY
2
Patent #:
Issue Dt:
10/09/2001
Application #:
09652578
Filing Dt:
08/31/2000
Title:
Die architecture accommodating high-speed semiconductor devices
3
Patent #:
Issue Dt:
08/20/2002
Application #:
09652584
Filing Dt:
08/31/2000
Title:
DIE ARCHITECTURE ACCOMMODATING HIGH-SPEED SEMICONDUCTOR DEVICES
4
Patent #:
Issue Dt:
10/09/2001
Application #:
09652586
Filing Dt:
08/31/2000
Title:
Die architecture accommodating high-speed semiconductor devices
5
Patent #:
Issue Dt:
11/06/2001
Application #:
09652587
Filing Dt:
08/31/2000
Title:
Die architecture accommodating high-speed semiconductor devices
6
Patent #:
Issue Dt:
10/24/2006
Application #:
09652619
Filing Dt:
08/31/2000
Title:
METHOD FOR FORMING A METALLIZATION LAYER
7
Patent #:
Issue Dt:
08/20/2002
Application #:
09652622
Filing Dt:
08/31/2000
Title:
Double-edged clocked storage device and method
8
Patent #:
Issue Dt:
11/25/2003
Application #:
09652639
Filing Dt:
08/31/2000
Title:
METHODS AND APPARATUSES FOR MAKING AND USING PLANARIZING PADS FOR MECHANICAL AND CHEMICAL-MECHANICAL PLANARIZATION OF MICROELECTRONIC SUBSTRATES
9
Patent #:
Issue Dt:
07/08/2003
Application #:
09652723
Filing Dt:
08/31/2000
Title:
METHOD OF PROVIDING AN OXIDE
10
Patent #:
Issue Dt:
07/30/2002
Application #:
09652746
Filing Dt:
08/31/2000
Title:
METHOD OF MAKING A FIELD EMISSION DEVICE WITH BUFFER LAYER
11
Patent #:
Issue Dt:
09/17/2002
Application #:
09652774
Filing Dt:
08/31/2000
Title:
SINGLE-LEVEL MASKING WITH PARTIAL USE OF ATTENUATED PHASE-SHIFT TECHNOLOGY
12
Patent #:
Issue Dt:
08/07/2001
Application #:
09652775
Filing Dt:
08/31/2000
Title:
Memory with combined synchronous burst and bus efficient functionality
13
Patent #:
Issue Dt:
05/27/2003
Application #:
09652835
Filing Dt:
08/31/2000
Title:
METHOD TO ELIMINATE STRIATIONS AND SURFACE ROUGHNESS CAUSED BY DRY ETCH
14
Patent #:
Issue Dt:
11/20/2001
Application #:
09652839
Filing Dt:
08/31/2000
Title:
Die architecture accommodating high-speed semiconductor devices
15
Patent #:
Issue Dt:
01/07/2003
Application #:
09652864
Filing Dt:
08/31/2000
Title:
SOI CMOS DEVICE WITH REDUCED DIBL
16
Patent #:
Issue Dt:
06/03/2003
Application #:
09652877
Filing Dt:
08/31/2000
Title:
DEPLETION MODE FERROELECTRIC MEMORY DEVICE AND METHOD OF WRITING TO AND READING FROM THE SAME
17
Patent #:
Issue Dt:
07/18/2006
Application #:
09652878
Filing Dt:
08/31/2000
Title:
SUBPAD SUPPORT WITH A RELEASABLE SUBPAD SECURING ELEMENTAND POLISHING APPARATUS INCLUDING THE SUBPAD SUPPORT
18
Patent #:
Issue Dt:
10/08/2002
Application #:
09652880
Filing Dt:
08/31/2000
Title:
MULTI-CHIP MODULE EMPLOYING A CARRIER SUBSTRATE WITH MICROMACHINED ALIGNMENT STRUCTURES AND METHOD OF FORMING
19
Patent #:
Issue Dt:
02/25/2003
Application #:
09652907
Filing Dt:
08/31/2000
Title:
DIELECTICE FILMS AND CAPACITOR STRUCTURES INCLUDING SAME
20
Patent #:
Issue Dt:
12/10/2002
Application #:
09652970
Filing Dt:
08/31/2000
Title:
HIGH-PRESSURE ANNEAL PROCESS FOR INTEGRATED CIRCUITS
21
Patent #:
Issue Dt:
07/13/2004
Application #:
09652991
Filing Dt:
08/31/2000
Title:
COMPOSITIONS FOR DISSOLUTION OF LOW-K DIELECTRIC FILMS, AND METHODS OF USE
22
Patent #:
Issue Dt:
12/04/2001
Application #:
09652996
Filing Dt:
08/31/2000
Title:
Die architecture accommodating high-speed semiconductor devices
23
Patent #:
Issue Dt:
07/01/2003
Application #:
09653074
Filing Dt:
08/31/2000
Title:
ARRAY ARCHITECTURE FOR DEPLETION MODE FERROELECTRIC MEMORY DEVICES
24
Patent #:
Issue Dt:
06/10/2003
Application #:
09653096
Filing Dt:
08/31/2000
Title:
DIELECTRIC LAYER FOR A SEMICONDUCTOR DEVICE HAVING LESS CURRENT LEAKAGE AND INCREASED CAPACITANCE
25
Patent #:
Issue Dt:
05/06/2003
Application #:
09653127
Filing Dt:
08/31/2000
Title:
BALL GRID ARRAY PACKAGES WITH THERMALLY CONDUCTIVE CONTAINERS
26
Patent #:
Issue Dt:
09/09/2003
Application #:
09653138
Filing Dt:
08/31/2000
Title:
METAL LINE AND METHOD OF SUPPRESSING VOID FORMATION THEREIN
27
Patent #:
Issue Dt:
05/15/2007
Application #:
09653149
Filing Dt:
08/31/2000
Title:
CAPACITOR FABRICATION METHODS INCLUDING FORMING A CONDUCTIVE LAYER
28
Patent #:
Issue Dt:
03/11/2003
Application #:
09653151
Filing Dt:
08/31/2000
Title:
METHODS OF FORMING CONDUCTIVE INTERCONNECTS
29
Patent #:
Issue Dt:
03/11/2003
Application #:
09653153
Filing Dt:
08/31/2000
Title:
METHOD, STRUCTURE AND PROCESS FLOW TO REDUCE LINE-LINE CAPACITANCE WITH LOW-K MATERIAL
30
Patent #:
Issue Dt:
06/25/2002
Application #:
09653249
Filing Dt:
08/31/2000
Title:
SINGLE ENDED DATA BUS EQUILIBRATION SCHEME
31
Patent #:
Issue Dt:
10/10/2006
Application #:
09653272
Filing Dt:
08/31/2000
Title:
METHOD FOR USING DATA REGARDING MANUFACTURING PROCEDURES INTEGRATED CIRCUITS (IC'S) HAVE UNDERGONE, SUCH AS REPAIRS, TO SELECT PROCEDURES THE IC'S WILL UNDERGO, SUCH AS ADDITIONAL REPAIRS
32
Patent #:
Issue Dt:
02/18/2003
Application #:
09653298
Filing Dt:
08/31/2000
Title:
METHOD OF FORMING AN ULTRA THIN DIELECTRIC FILM
33
Patent #:
Issue Dt:
01/01/2002
Application #:
09653356
Filing Dt:
08/31/2000
Title:
Method to electrically program antifuses
34
Patent #:
Issue Dt:
06/29/2004
Application #:
09653366
Filing Dt:
09/01/2000
Title:
METHOD FOR FABRICATING A SEMICONDUCTOR COMPONENT WITH EXTERNAL CONTACT POLYMER SUPPORT LAYER
35
Patent #:
Issue Dt:
04/22/2003
Application #:
09653392
Filing Dt:
08/31/2000
Title:
SLURRY FOR USE IN POLISHING SEMICONDUCTOR DEVICE CONDUCTIVE STRUCTURES THAT INCLUDE COPPER AND TUNGSTEN AND POLISHING METHODS
36
Patent #:
Issue Dt:
07/30/2002
Application #:
09653423
Filing Dt:
08/31/2000
Title:
METHOD OF CO-DEPOSITION TO FORM ULTRA-SHALLOW JUNCTIONS IN MOS DEVICES USING ELECTROLESS OR ELECTRODELPOSITION
37
Patent #:
Issue Dt:
10/28/2003
Application #:
09653473
Filing Dt:
08/31/2000
Title:
USE OF A REFERENCE FIDUCIAL ON A SEMICONDUCTOR PACKAGE TO MONITOR AND CONTROL A SINGULATION METHOD
38
Patent #:
Issue Dt:
07/15/2003
Application #:
09653495
Filing Dt:
08/31/2000
Title:
INTEGRATED VOLATILE AND NON-VOLATILE MEMORY
39
Patent #:
Issue Dt:
11/04/2003
Application #:
09653513
Filing Dt:
08/31/2000
Title:
DEVICES CONTAINING ZIRCONIUM-PLATINUM-CONTAINING MATERIALS AND METHODS FOR PREPARING SUCH MATERIALS AND DEVICES
40
Patent #:
Issue Dt:
09/17/2002
Application #:
09653522
Filing Dt:
08/31/2000
Title:
SELF-ALIGNED PECVD ETCH MASK
41
Patent #:
Issue Dt:
10/15/2002
Application #:
09653523
Filing Dt:
08/31/2000
Title:
ULTRA THIN TCS (SIC14) CELL NITRIDE FOR DRAM CAPACITOR WITH DCS (SIH2C12) INTERFACE SEEDING LAYER
42
Patent #:
Issue Dt:
12/17/2002
Application #:
09653539
Filing Dt:
08/31/2000
Title:
DISTRIBUTED CELL PLATE AND/OR DIGIT EQUILIBRATE VOLTAGE GENERATOR
43
Patent #:
Issue Dt:
04/06/2004
Application #:
09653541
Filing Dt:
08/31/2000
Title:
MAGNETIC SHIELDING FOR INTEGRATED CIRCUITS
44
Patent #:
Issue Dt:
04/01/2003
Application #:
09653553
Filing Dt:
08/31/2000
Title:
ATOMIC LAYER DOPING APPARATUS AND METHOD
45
Patent #:
Issue Dt:
04/16/2002
Application #:
09653554
Filing Dt:
08/31/2000
Title:
METHOD FOR SELECTIVE ETCHING OF OXIDES
46
Patent #:
Issue Dt:
09/23/2003
Application #:
09653558
Filing Dt:
08/31/2000
Title:
SHIELDED PC BOARD FOR MAGNETICALLY SENSITIVE INTEGRATED CIRCUITS
47
Patent #:
Issue Dt:
09/09/2003
Application #:
09653560
Filing Dt:
08/31/2000
Title:
SUBTRACTIVE METALLIZATION STRUCTURE AND METHOD OF MAKING
48
Patent #:
Issue Dt:
10/24/2006
Application #:
09653561
Filing Dt:
08/31/2000
Title:
METHOD AND MATERIAL FOR REMOVING ETCH RESIDUE FROM HIGH ASPECT RATIO CONTACT SURFACES
49
Patent #:
Issue Dt:
09/24/2002
Application #:
09653596
Filing Dt:
08/31/2000
Title:
SPUTTERED INSULATING LAYER FOR WORDLINE STACKS
50
Patent #:
Issue Dt:
04/30/2002
Application #:
09653638
Filing Dt:
08/31/2000
Title:
SELECTIVE POLYSILICON STUD GROWTH
51
Patent #:
Issue Dt:
09/07/2004
Application #:
09653640
Filing Dt:
08/31/2000
Title:
INTEGRATED CIRCUIT HAVING A BARRIER STRUCTURE
52
Patent #:
Issue Dt:
08/13/2002
Application #:
09654098
Filing Dt:
08/31/2000
Title:
CIRCUIT CONFIGURATION FOR ENHANCING PERFORMANCE CHARACTERISTICS OF FABRICATED DEVICES
53
Patent #:
Issue Dt:
04/08/2003
Application #:
09654099
Filing Dt:
08/31/2000
Title:
VOLTAGE REGULATOR AND DATA PATH FOR A MEMORY DEVICE
54
Patent #:
Issue Dt:
10/14/2003
Application #:
09654107
Filing Dt:
08/31/2000
Title:
PRECISION FIDUCIAL
55
Patent #:
Issue Dt:
07/23/2002
Application #:
09654226
Filing Dt:
08/30/2000
Title:
METHOD AND SYSTEM FOR CONTROLLING THE DUTY CYCLE OF A CLOCK SIGNAL
56
Patent #:
Issue Dt:
10/15/2002
Application #:
09655000
Filing Dt:
08/31/2000
Title:
DRAM FABRICATED ON A SILICON-ON-INSULATOR (SOI) SUBSTRATE HAVING BI-LEVEL DIGIT LINES
57
Patent #:
Issue Dt:
06/03/2003
Application #:
09655002
Filing Dt:
08/31/2000
Title:
APPARATUS AND METHODS OF AUTOMATED WAFER-GRINDING USING GRINDING SURFACE POSITION MONITORING
58
Patent #:
Issue Dt:
05/18/2004
Application #:
09655004
Filing Dt:
08/31/2000
Title:
METHOD AND SYSTEM FOR SUBSTANTIALLY REGISTERLESS PROCESSING
59
Patent #:
Issue Dt:
12/17/2002
Application #:
09655034
Filing Dt:
09/05/2000
Title:
LOW PROFILE SEMICONDUCTOR PACKAGE
60
Patent #:
Issue Dt:
04/02/2002
Application #:
09655167
Filing Dt:
09/05/2000
Title:
Method and apparatus for anticipatory selection of external or internal addresses in a synchronous memory device
61
Patent #:
Issue Dt:
11/05/2002
Application #:
09655934
Filing Dt:
09/06/2000
Title:
SEMICONDUCTOR MEMORY DEVICE WITH SIMULTANEOUSLY FORMED ELECTRODE AND INTERCONNECTION LAYERS
62
Patent #:
Issue Dt:
07/16/2002
Application #:
09658327
Filing Dt:
09/08/2000
Title:
CIRCUIT AND METHOD TO PREVENT INADVERTENT TEST MODE ENTRY
63
Patent #:
Issue Dt:
09/11/2001
Application #:
09658334
Filing Dt:
09/08/2000
Title:
Circuit to prevent inadvertent test mode entry
64
Patent #:
Issue Dt:
09/17/2002
Application #:
09659247
Filing Dt:
09/11/2000
Title:
APPARATUS FOR TESTING REDUNDANT ELEMENTS IN A PACKAGED SEMICONDUCTOR MEMORY DEVICE
65
Patent #:
Issue Dt:
03/12/2002
Application #:
09659334
Filing Dt:
09/12/2000
Title:
Active termination in a multidrop memory system
66
Patent #:
Issue Dt:
06/05/2001
Application #:
09659471
Filing Dt:
09/11/2000
Title:
Apparatus for on-board programming of serial eeproms
67
Patent #:
Issue Dt:
01/07/2003
Application #:
09660303
Filing Dt:
09/12/2000
Title:
METHOD FOR PAGE MODE WRITING IN AN ELECTRICALLY ERASABLE/PROGRAMMABLE NON-VOLATILE MEMORY AND CORRESPONDING ARCHITECTURE
68
Patent #:
Issue Dt:
08/03/2004
Application #:
09660838
Filing Dt:
09/13/2000
Title:
FLASH MEMORY SYSTEM AND METHOD IMPLEMENTING LBA TO PBA CORRELATION WITHIN FLASH MEMORY ARRAY
69
Patent #:
Issue Dt:
01/03/2006
Application #:
09661540
Filing Dt:
09/14/2000
Title:
BIOS LOCK CD-ROM ENDCODE/DECODE DRIVER
70
Patent #:
Issue Dt:
08/27/2002
Application #:
09662407
Filing Dt:
09/14/2000
Title:
STEPPED PHOTORESIST PROFILE AND OPENING FORMED USING THE PROFILE
71
Patent #:
Issue Dt:
07/02/2002
Application #:
09663035
Filing Dt:
09/15/2000
Title:
Method and apparatus for synchronous data transfers in a memory device with selectable data or address paths
72
Patent #:
Issue Dt:
07/03/2001
Application #:
09665339
Filing Dt:
09/19/2000
Title:
Method and apparatus for setting the common mode level of a differential output
73
Patent #:
Issue Dt:
05/18/2004
Application #:
09665430
Filing Dt:
09/19/2000
Title:
THERMALLY CONDUCTIVE ADHESIVE TAPE FOR SEMICONDUCTOR DEVICES AND METHOD FOR USING THE SAME
74
Patent #:
Issue Dt:
02/28/2006
Application #:
09665826
Filing Dt:
09/20/2000
Title:
METHOD AND APPARATUS TO IMPROVE THE PROTECTION OF INFORMATION PRESENTED BY A COMPUTER
75
Patent #:
Issue Dt:
06/08/2004
Application #:
09665922
Filing Dt:
09/20/2000
Title:
METHOD AND APPARATUS FOR A LOW LATENCY SOURCE-SYNCHRONOUS ADDRESS RECEIVER FOR A HOST SYSTEM BUS IN A MEMORY CONTROLLER
76
Patent #:
Issue Dt:
02/04/2003
Application #:
09668922
Filing Dt:
09/25/2000
Title:
SHIELDING ARRANGEMENT TO PROTECT A CIRCUIT FROM STRAY MAGNETIC FIELDS
77
Patent #:
Issue Dt:
05/01/2001
Application #:
09669093
Filing Dt:
09/25/2000
Title:
Semiconductor processing methods, and methods of forming capacitor constructions
78
Patent #:
Issue Dt:
06/17/2003
Application #:
09669228
Filing Dt:
09/25/2000
Title:
MODULAR DRIVE CAGE ASSEMBLY
79
Patent #:
Issue Dt:
07/22/2003
Application #:
09669281
Filing Dt:
09/26/2000
Title:
PROGRAMMABLE MEMORY ADDRESS DECODE ARRAY WITH VERTICAL TRANSISTORS
80
Patent #:
Issue Dt:
08/20/2002
Application #:
09670248
Filing Dt:
09/26/2000
Title:
NONVOLATILE MEMORY AND HIGH SPEED MEMORY TEST METHOD
81
Patent #:
Issue Dt:
08/28/2001
Application #:
09670471
Filing Dt:
09/26/2000
Title:
Memory test method and nonvolatile memory with low error masking probability
82
Patent #:
Issue Dt:
05/22/2001
Application #:
09670982
Filing Dt:
09/26/2000
Title:
RF powered plasma enhanced chemical vapor deposition reactor and methods of effecting plasma enhanced chemical vapor deposition
83
Patent #:
Issue Dt:
08/05/2003
Application #:
09672690
Filing Dt:
09/29/2000
Title:
A METHOD FOR MAKING A PACKAGED SEMICONDUCTOR DEVICE
84
Patent #:
Issue Dt:
09/11/2001
Application #:
09674395
Filing Dt:
10/30/2000
Title:
Monolithically integrated selector for electrically programmable memory cell devices
85
Patent #:
Issue Dt:
08/13/2002
Application #:
09675072
Filing Dt:
09/28/2000
Title:
INTERCONNECT AND SYSTEM FOR TESTING BUMPED SEMICONDUCTOR COMPONENTS WITH ON-BOARD MULTIPLEX CIRCUITRY FOR EXPANDING TESTER RESOURCES
86
Patent #:
Issue Dt:
02/25/2003
Application #:
09675117
Filing Dt:
09/28/2000
Title:
SEMICONDUCTOR DEVICE HAVING INCREASED BREAKDOWN VOLTAGE AND METHOD OF FABRICATING SAME
87
Patent #:
Issue Dt:
01/23/2007
Application #:
09675286
Filing Dt:
09/29/2000
Title:
RUNTIME PREDICTION FRAMEWORK FOR CPU INTENSIVE APPLICATIONS
88
Patent #:
Issue Dt:
03/25/2003
Application #:
09675635
Filing Dt:
09/29/2000
Title:
RUTHENIUM AND RUTHENIUM DIOXIDE REMOVAL METHOD AND MATERIAL
89
Patent #:
Issue Dt:
02/11/2003
Application #:
09675901
Filing Dt:
09/28/2000
Title:
A METHOD FOR FORMING A FIELD EFFECT TRANSISTOR HAVING INCREASED BREAKDOWN VOLTAGE
90
Patent #:
Issue Dt:
03/04/2008
Application #:
09676175
Filing Dt:
09/29/2000
Title:
EXECUTING A TRANSLATED BLOCK OF INSTRUCTIONS AND BRANCHING TO CORRECTION CODE WHEN EXPECTED TOP OF STACK DOES NOT MATCH ACTUAL TOP OF STACK TO ADJUST STACK AT EXECUTION TIME TO CONTINUE EXECUTING WITHOUT RESTARTING TRANSLATING
91
Patent #:
Issue Dt:
05/07/2002
Application #:
09676313
Filing Dt:
09/29/2000
Title:
Clock splitter circuit to generate synchronized clock and inverted clock
92
Patent #:
Issue Dt:
05/08/2007
Application #:
09676556
Filing Dt:
09/30/2000
Title:
EFFICIENT IMPLEMENTATION OF N-POINT DCT, N-POINT IDCT, SA-DCT AND SA-IDCT ALGORITHMS
93
Patent #:
Issue Dt:
11/12/2002
Application #:
09677267
Filing Dt:
09/26/2000
Title:
METHOD FOR FORMING AN ETCH MASK DURING THE MANUFACTURE OF A SEMICONDUCTOR DEVICE
94
Patent #:
Issue Dt:
06/12/2001
Application #:
09677364
Filing Dt:
10/02/2000
Title:
Column decode circuits and apparatus
95
Patent #:
Issue Dt:
02/27/2007
Application #:
09677478
Filing Dt:
10/02/2000
Title:
PLASMA ETCHING METHODS
96
Patent #:
Issue Dt:
01/07/2003
Application #:
09678468
Filing Dt:
10/02/2000
Title:
FIELD EFFECT TRANSISTORS, FIELD EMISSION APPARATUSES, AND A THIN FILM TRANSISTOR
97
Patent #:
Issue Dt:
03/19/2002
Application #:
09678941
Filing Dt:
10/03/2000
Title:
Method and apparatus for reducing induced switching transients
98
Patent #:
Issue Dt:
02/18/2003
Application #:
09679095
Filing Dt:
10/04/2000
Title:
CONTROLLING PACKAGING ENCAPSULANT LEAKAGE
99
Patent #:
Issue Dt:
08/21/2001
Application #:
09679393
Filing Dt:
10/03/2000
Title:
Methods of forming SOI insulator layers, methods of forming transistor devices, and semiconductor devices and assemblies
100
Patent #:
Issue Dt:
01/14/2003
Application #:
09679940
Filing Dt:
10/04/2000
Title:
METHOD OF MAKING CHIP SCALE PACKAGE WITH HEAT SPREADER
Assignor
1
Exec Dt:
06/29/2018
Assignee
1
8000 S. FEDERAL WAY
BOISE, IDAHO 83707
Correspondence name and address
WSGR, C/O QUI LU FLOOD, SENIOR PARALEGAL
ONE MARKET, SPEAR TOWER, SUITE 3300
SAN FRANCISCO, CA 94105

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