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Reel/Frame:047243/0001   Pages: 959
Recorded: 08/23/2018
Attorney Dkt #:4816.238
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
1
Patent #:
Issue Dt:
01/02/2007
Application #:
10614215
Filing Dt:
07/08/2003
Publication #:
Pub Dt:
08/05/2004
Title:
TECHNIQUE FOR SYNCHRONIZING FAULTS IN A PROCESSOR HAVING A REPLAY SYSTEM
2
Patent #:
Issue Dt:
08/02/2005
Application #:
10614418
Filing Dt:
07/03/2003
Publication #:
Pub Dt:
02/24/2005
Title:
HAZE-FREE BST FILMS
3
Patent #:
Issue Dt:
02/08/2005
Application #:
10614489
Filing Dt:
07/03/2003
Publication #:
Pub Dt:
04/01/2004
Title:
HAZE-FREE BST FILMS
4
Patent #:
Issue Dt:
08/23/2005
Application #:
10614538
Filing Dt:
07/03/2003
Publication #:
Pub Dt:
07/01/2004
Title:
SEMICONDUCTOR STRUCTURE WITH SUBSTANTIALLY ETCHED OXYNITRIDE DEFECTS PROTRUDING THEREFROM
5
Patent #:
Issue Dt:
12/28/2004
Application #:
10614693
Filing Dt:
07/07/2003
Publication #:
Pub Dt:
07/15/2004
Title:
VOLTAGE BOOST DEVICE AND MEMORY SYSTEM
6
Patent #:
Issue Dt:
10/10/2006
Application #:
10614917
Filing Dt:
07/07/2003
Publication #:
Pub Dt:
01/08/2004
Title:
NON-LOT BASED METHOD FOR ASSEMBLING INTEGRATED CIRCUIT DEVICES
7
Patent #:
Issue Dt:
10/24/2006
Application #:
10615051
Filing Dt:
07/07/2003
Publication #:
Pub Dt:
01/13/2005
Title:
METHODS OF FORMING A PHOSPHORUS DOPED SILICON DIOXIDE-COMPRISING LAYER
8
Patent #:
Issue Dt:
07/26/2005
Application #:
10615287
Filing Dt:
07/07/2003
Publication #:
Pub Dt:
01/13/2005
Title:
METHODS OF FORMING MEMORY CIRCUITRY
9
Patent #:
Issue Dt:
09/06/2005
Application #:
10615524
Filing Dt:
07/03/2003
Publication #:
Pub Dt:
02/26/2004
Title:
HAZE-FREE BST FILMS
10
Patent #:
Issue Dt:
02/17/2009
Application #:
10615891
Filing Dt:
07/08/2003
Publication #:
Pub Dt:
05/20/2004
Title:
STRUCTURES AND METHODS FOR IMPROVED CAPACITOR CELLS IN INTEGRATED CIRCUITS
11
Patent #:
Issue Dt:
07/26/2005
Application #:
10616078
Filing Dt:
07/07/2003
Publication #:
Pub Dt:
02/12/2004
Title:
NON-CONDUCTIVE AND SELF-LEVELING LEADFRAME CLAMP INSERT FOR WIREBONDING INTEGRATED CIRCUITS
12
Patent #:
Issue Dt:
08/16/2005
Application #:
10616414
Filing Dt:
07/08/2003
Publication #:
Pub Dt:
04/01/2004
Title:
LINE SELECTOR FOR A MATRIX OF MEMORY ELEMENTS
13
Patent #:
Issue Dt:
07/10/2007
Application #:
10616958
Filing Dt:
07/11/2003
Publication #:
Pub Dt:
01/13/2005
Title:
DATA ENCODING FOR FAST CAM AND TCAM ACCESS TIMES
14
Patent #:
Issue Dt:
07/26/2005
Application #:
10617246
Filing Dt:
07/09/2003
Publication #:
Pub Dt:
01/13/2005
Title:
DATA STROBE SYNCHRONIZATION CIRCUIT AND METHOD FOR DOUBLE DATA RATE, MULTI-BIT WRITES
15
Patent #:
Issue Dt:
02/08/2005
Application #:
10617719
Filing Dt:
07/14/2003
Publication #:
Pub Dt:
03/04/2004
Title:
MRAM SENSE LAYER AREA CONTROL
16
Patent #:
Issue Dt:
05/03/2005
Application #:
10617936
Filing Dt:
07/10/2003
Publication #:
Pub Dt:
06/03/2004
Title:
SEMICONDUCTOR COMPONENT HAVING CONDUCTORS WITH WIRE BONDABLE METALIZATION LAYERS
17
Patent #:
Issue Dt:
10/10/2006
Application #:
10619052
Filing Dt:
07/10/2003
Publication #:
Pub Dt:
01/13/2005
Title:
METHOD AND STRUCTURE FOR A SELF-ALIGNED SILICIDED WORD LINE AND POLYSILICON PLUG DURING THE FORMATION OF A SEMICONDUCTOR DEVICE
18
Patent #:
Issue Dt:
05/09/2006
Application #:
10619650
Filing Dt:
07/14/2003
Publication #:
Pub Dt:
01/20/2005
Title:
SEMICONDUCTOR INTERCONNECT HAVING COMPLIANT CONDUCTIVE CONTACTS
19
Patent #:
Issue Dt:
04/19/2005
Application #:
10620003
Filing Dt:
07/14/2003
Publication #:
Pub Dt:
02/26/2004
Title:
METHODS OF FABRICATING SILICIDE PATTERN STRUCTURES
20
Patent #:
Issue Dt:
08/09/2005
Application #:
10620054
Filing Dt:
07/14/2003
Publication #:
Pub Dt:
02/26/2004
Title:
Semiconductor fuses and semiconductor devices containing the same
21
Patent #:
Issue Dt:
02/12/2008
Application #:
10620468
Filing Dt:
07/15/2003
Publication #:
Pub Dt:
01/22/2004
Title:
CONDUCTIVE CONNECTION FORMING METHODS, OXIDATION REDUCING METHODS, AND INTEGRATED CIRCUITS FORMED THEREBY
22
Patent #:
Issue Dt:
04/03/2007
Application #:
10620469
Filing Dt:
07/15/2003
Publication #:
Pub Dt:
01/20/2005
Title:
MEMORY DRIVER ARCHITECTURE AND ASSOCIATED METHODS
23
Patent #:
Issue Dt:
12/19/2006
Application #:
10620612
Filing Dt:
07/17/2003
Publication #:
Pub Dt:
01/29/2004
Title:
INTEGRATED SEMICONDUCTOR MEMORY CHIP WITH PRESENCE DETECT DATA CAPABILITY
24
Patent #:
Issue Dt:
06/26/2007
Application #:
10620714
Filing Dt:
07/15/2003
Publication #:
Pub Dt:
02/26/2004
Title:
STACKED MICROELECTRONIC DIES
25
Patent #:
Issue Dt:
10/17/2006
Application #:
10621194
Filing Dt:
07/15/2003
Publication #:
Pub Dt:
01/22/2004
Title:
MICROELECTRONIC DEVICES AND METHODS FOR MOUNTING MICROELECTRONIC PACKAGES TO CIRCUIT BOARDS
26
Patent #:
Issue Dt:
02/21/2006
Application #:
10622295
Filing Dt:
07/17/2003
Publication #:
Pub Dt:
01/29/2004
Title:
METHODS OF FORMING SEMICONDUCTOR CONSTRUCTIONS
27
Patent #:
Issue Dt:
05/30/2006
Application #:
10622497
Filing Dt:
07/21/2003
Publication #:
Pub Dt:
01/27/2005
Title:
STABLE ELECTROLESS FINE PITCH INTERCONNECT PLATING
28
Patent #:
Issue Dt:
11/23/2004
Application #:
10622907
Filing Dt:
07/17/2003
Publication #:
Pub Dt:
03/11/2004
Title:
METHOD FOR CONTACT PAD ISOLATION
29
Patent #:
Issue Dt:
06/12/2007
Application #:
10623474
Filing Dt:
07/18/2003
Publication #:
Pub Dt:
04/29/2004
Title:
AUTOMATIC DECODING METHOD FOR MAPPING AND SELECTING A NON-VOLATILE MEMORY DEVICE HAVING A LPC SERIAL COMMUNICATION INTERFACE IN THE AVAILABLE ADDRESSING AREA ON MOTHERBOARDS
30
Patent #:
Issue Dt:
10/21/2008
Application #:
10623788
Filing Dt:
07/21/2003
Publication #:
Pub Dt:
01/27/2005
Title:
STRAINED SEMICONDUCTOR BY FULL WAFER BONDING
31
Patent #:
Issue Dt:
08/16/2005
Application #:
10623794
Filing Dt:
07/21/2003
Publication #:
Pub Dt:
01/27/2005
Title:
GETTERING USING VOIDS FORMED BY SURFACE TRANSFORMATION
32
Patent #:
Issue Dt:
07/17/2007
Application #:
10624332
Filing Dt:
07/22/2003
Publication #:
Pub Dt:
07/01/2004
Title:
CHIP ON BOARD AND HEAT SINK ATTACHMENT METHODS
33
Patent #:
Issue Dt:
10/21/2008
Application #:
10624340
Filing Dt:
07/21/2003
Publication #:
Pub Dt:
01/27/2005
Title:
CAPACITOR CONSTRUCTIONS AND METHODS OF FORMING
34
Patent #:
Issue Dt:
08/08/2006
Application #:
10624627
Filing Dt:
07/21/2003
Publication #:
Pub Dt:
05/20/2004
Title:
METHODS OF FORMING SEMICONDUCTOR CONSTRUCTIONS
35
Patent #:
Issue Dt:
08/15/2006
Application #:
10624628
Filing Dt:
07/21/2003
Publication #:
Pub Dt:
05/20/2004
Title:
METHODS OF FORMING SEMICONDUCTOR CONSTRUCTIONS
36
Patent #:
Issue Dt:
10/23/2007
Application #:
10624716
Filing Dt:
07/21/2003
Publication #:
Pub Dt:
04/15/2004
Title:
METHODS OF FORMING SEMICONDUCTOR CONSTRUCTIONS
37
Patent #:
Issue Dt:
05/31/2005
Application #:
10624833
Filing Dt:
07/22/2003
Publication #:
Pub Dt:
07/01/2004
Title:
METHOD FOR FABRICATING A CHIP SCALE PACKAGE USING WAFER LEVEL PROCESSING
38
Patent #:
Issue Dt:
06/21/2005
Application #:
10625068
Filing Dt:
07/22/2003
Title:
METHODS OF MAKING SEMICONDUCTOR-ON-INSULATOR THIN FILM TRANSISTOR CONSTRUCTIONS
39
Patent #:
Issue Dt:
01/23/2007
Application #:
10625166
Filing Dt:
07/22/2003
Publication #:
Pub Dt:
01/27/2005
Title:
WET ETCHING METHOD OF REMOVING SILICON FROM A SUBSTRATE
40
Patent #:
Issue Dt:
03/08/2005
Application #:
10625693
Filing Dt:
07/24/2003
Publication #:
Pub Dt:
01/27/2005
Title:
CONVERTING DIGITAL SIGNALS
41
Patent #:
Issue Dt:
07/19/2005
Application #:
10625952
Filing Dt:
07/23/2003
Publication #:
Pub Dt:
04/14/2005
Title:
AN IMPROVED METHOD, STRUCTURE AND PROCESS FLOW TO REDUCE LINE-LINE CAPACITANCE WITH LOW-K MATERIAL
42
Patent #:
Issue Dt:
09/02/2008
Application #:
10626620
Filing Dt:
07/25/2003
Publication #:
Pub Dt:
05/12/2005
Title:
METHOD TO REMOVE AN OXIDE SEAM ALONG GATE STACK EDGE, WHEN NITRIDE SPACE FORMATION BEGINS WITH AN OXIDE LINER SURROUNDING GATE STACK
43
Patent #:
Issue Dt:
10/11/2005
Application #:
10626729
Filing Dt:
07/25/2003
Publication #:
Pub Dt:
01/27/2005
Title:
NOISE REDUCTION IN A CAM MEMORY CELL
44
Patent #:
Issue Dt:
07/05/2005
Application #:
10627536
Filing Dt:
07/25/2003
Publication #:
Pub Dt:
01/29/2004
Title:
HIGH SPEED LOW POWER INPUT BUFFER
45
Patent #:
Issue Dt:
05/17/2005
Application #:
10628243
Filing Dt:
07/29/2003
Publication #:
Pub Dt:
02/26/2004
Title:
SPATIAL REGIONS OF A SECOND MATERIAL IN A FIRST MATERIAL
46
Patent #:
Issue Dt:
09/12/2006
Application #:
10628994
Filing Dt:
07/28/2003
Publication #:
Pub Dt:
02/03/2005
Title:
DOUBLE SIDED CONTAINER CAPACITOR FOR A SEMICONDUCTOR DEVICE AND METHOD FOR FORMING SAME
47
Patent #:
Issue Dt:
10/30/2007
Application #:
10628997
Filing Dt:
07/28/2003
Publication #:
Pub Dt:
02/03/2005
Title:
NETWORK STATISTICS
48
Patent #:
Issue Dt:
07/04/2006
Application #:
10629156
Filing Dt:
07/28/2003
Publication #:
Pub Dt:
09/30/2004
Title:
SYSTEM AND METHOD FOR ENCODING PROCESSING ELEMENT COMMANDS IN AN ACTIVE MEMORY DEVICE
49
Patent #:
Issue Dt:
08/10/2004
Application #:
10629199
Filing Dt:
07/29/2003
Publication #:
Pub Dt:
02/05/2004
Title:
METHOD OF PASSIVATING AN OXIDE SURFACE SUBJECTED TO A CONDUCTIVE MATERIAL ANNEAL
50
Patent #:
Issue Dt:
12/12/2006
Application #:
10629378
Filing Dt:
07/28/2003
Publication #:
Pub Dt:
09/30/2004
Title:
DATA REORDERING PROCESSOR AND METHOD FOR USE IN AN ACTIVE MEMORY DEVICE
51
Patent #:
Issue Dt:
11/07/2006
Application #:
10629382
Filing Dt:
07/28/2003
Publication #:
Pub Dt:
09/30/2004
Title:
ACTIVE MEMORY PROCESSING ARRAY TOPOGRAPHY AND METHOD
52
Patent #:
Issue Dt:
02/20/2007
Application #:
10629428
Filing Dt:
07/28/2003
Publication #:
Pub Dt:
09/30/2004
Title:
ACTIVE MEMORY COMMAND ENGINE AND METHOD
53
Patent #:
Issue Dt:
06/21/2005
Application #:
10629641
Filing Dt:
07/29/2003
Publication #:
Pub Dt:
02/05/2004
Title:
MULTI-LAYER, ATTENUATED PHASE-SHIFTING MASK
54
Patent #:
Issue Dt:
01/25/2005
Application #:
10629666
Filing Dt:
07/29/2003
Publication #:
Pub Dt:
02/05/2004
Title:
METHOD FOR BALL GRID ARRAY CHIP PACKAGES HAVING IMPROVED TESTING AND STACKING CHARACTERISTICS
55
Patent #:
Issue Dt:
02/15/2005
Application #:
10629830
Filing Dt:
07/30/2003
Publication #:
Pub Dt:
02/03/2005
Title:
MATCH LINE SENSING AMPLIFIER FOR CONTENT ADDRESSABLE MEMORY
56
Patent #:
Issue Dt:
05/10/2005
Application #:
10630051
Filing Dt:
07/30/2003
Publication #:
Pub Dt:
04/15/2004
Title:
METHODS AND APPARATUS FOR FORMING SOLDER BALLS
57
Patent #:
Issue Dt:
10/03/2006
Application #:
10630268
Filing Dt:
07/30/2003
Publication #:
Pub Dt:
02/05/2004
Title:
TECHNIQUE FOR ELIMINATION OF PITTING ON SILICON SUBSTRATE DURING GATE STACK ETCH USING MATERIAL IN A NON-ANNEALED STATE
58
Patent #:
Issue Dt:
09/15/2009
Application #:
10630635
Filing Dt:
07/29/2003
Publication #:
Pub Dt:
03/18/2004
Title:
SYSTEM AND METHOD FOR DYNAMIC BUFFER ALLOCATION
59
Patent #:
Issue Dt:
12/14/2004
Application #:
10630757
Filing Dt:
07/31/2003
Title:
PRIORITY ENCODING
60
Patent #:
Issue Dt:
10/19/2004
Application #:
10630761
Filing Dt:
07/31/2003
Publication #:
Pub Dt:
04/15/2004
Title:
REGULATOR CIRCUIT FOR INDEPENDENT ADJUSTMENT OF PUMPS IN MULTIPLE MODES OF OPERATION
61
Patent #:
Issue Dt:
12/19/2006
Application #:
10630812
Filing Dt:
07/31/2003
Publication #:
Pub Dt:
02/03/2005
Title:
OBTAINING SEARCH RESULTS FOR CONTENT ADDRESSABLE MEMORY
62
Patent #:
Issue Dt:
07/26/2005
Application #:
10631342
Filing Dt:
07/30/2003
Publication #:
Pub Dt:
04/15/2004
Title:
SEMICONDUCTOR PACKAGE ASSEMBLY AND METHOD FOR ELECTRICALLY ISOLATING MODULES
63
Patent #:
Issue Dt:
01/16/2007
Application #:
10631463
Filing Dt:
07/30/2003
Publication #:
Pub Dt:
07/08/2004
Title:
METHOD FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT STRUCTURES
64
Patent #:
Issue Dt:
02/08/2005
Application #:
10631918
Filing Dt:
07/31/2003
Publication #:
Pub Dt:
04/15/2004
Title:
ROM EMBEDDED DRAM WITH DIELECTRIC REMOVAL/SHORT
65
Patent #:
Issue Dt:
02/13/2007
Application #:
10631921
Filing Dt:
07/31/2003
Title:
TRANSISTOR GATE AND LOCAL INTERCONNECT
66
Patent #:
Issue Dt:
08/24/2004
Application #:
10632579
Filing Dt:
07/31/2003
Publication #:
Pub Dt:
02/05/2004
Title:
METHODS OF FORMING MAGNETORESISTIVE MEMORY DEVICES
67
Patent #:
Issue Dt:
12/01/2009
Application #:
10632628
Filing Dt:
08/01/2003
Publication #:
Pub Dt:
02/03/2005
Title:
MULTIFREQUENCY PLASMA REACTOR
68
Patent #:
Issue Dt:
07/18/2006
Application #:
10633165
Filing Dt:
08/01/2003
Publication #:
Pub Dt:
02/05/2004
Title:
SELF-ALIGNED POLY-METAL STRUCTURES
69
Patent #:
Issue Dt:
02/08/2005
Application #:
10633189
Filing Dt:
08/01/2003
Publication #:
Pub Dt:
02/05/2004
Title:
METHOD AND SYSTEM HAVING SWITCHING NETWORK FOR TESTING SEMICONDUCTOR COMPONENTS ON A SUBSTRATE
70
Patent #:
Issue Dt:
06/22/2004
Application #:
10633247
Filing Dt:
08/01/2003
Publication #:
Pub Dt:
02/12/2004
Title:
DUAL BANDGAP VOLTAGE REFERENCE SYSTEM AND METHOD FOR REDUCING CURRENT CONSUMPTION DURING A STANDBY MODE OF OPERATION AND FOR PROVIDING REFERENCE STABILITY DURING AN ACTIVE MODE OF OPERATION
71
Patent #:
Issue Dt:
06/07/2005
Application #:
10633434
Filing Dt:
08/01/2003
Publication #:
Pub Dt:
02/03/2005
Title:
Semiconductor component having chip on board leadframe
72
Patent #:
Issue Dt:
08/09/2005
Application #:
10633628
Filing Dt:
08/05/2003
Publication #:
Pub Dt:
03/18/2004
Title:
MAGNETORESISTIVE MEMORY OR SENSOR DEVICES HAVING IMPROVED SWITCHING PROPERTIES AND METHOD OF FABRICATION
73
Patent #:
Issue Dt:
08/29/2006
Application #:
10633851
Filing Dt:
08/04/2003
Publication #:
Pub Dt:
02/12/2004
Title:
INTEGRATED CIRCUIT PACKAGE ELECTRICAL ENHANCEMENT WITH IMPROVED LEAD FRAME DESIGN
74
Patent #:
Issue Dt:
02/22/2005
Application #:
10633923
Filing Dt:
08/04/2003
Publication #:
Pub Dt:
02/26/2004
Title:
METHOD FOR IMPLEMENTING SELECTED FUNCTIONALITY ON AN INTEGRATED CIRCUIT DEVICE
75
Patent #:
Issue Dt:
05/24/2005
Application #:
10633924
Filing Dt:
08/04/2003
Publication #:
Pub Dt:
02/12/2004
Title:
APPARATUS FOR IMPLEMENTING SELECTED FUNCTIONALITY ON AN INTEGRATED CIRCUIT DEVICE IN AN ELECTRONIC DEVICE
76
Patent #:
Issue Dt:
05/24/2005
Application #:
10633925
Filing Dt:
08/04/2003
Publication #:
Pub Dt:
02/12/2004
Title:
APPARATUS FOR FORMING A STACK OF PACKAGED MEMORY DICE
77
Patent #:
Issue Dt:
04/26/2005
Application #:
10634073
Filing Dt:
08/04/2003
Publication #:
Pub Dt:
02/26/2004
Title:
METHOD OF FORMING A STACK OF PACKAGED MEMORY DICE
78
Patent #:
Issue Dt:
03/22/2005
Application #:
10634074
Filing Dt:
08/04/2003
Publication #:
Pub Dt:
02/12/2004
Title:
METHODS FOR STACKING WIRE-BONDED INTEGRATED CIRCUIT DICE ON FLIP-CHIP BONDED INTEGRATED CIRCUIT DICE
79
Patent #:
Issue Dt:
05/31/2005
Application #:
10634075
Filing Dt:
08/04/2003
Publication #:
Pub Dt:
02/12/2004
Title:
ELECTRODE STRUCTURES, DISPLAY DEVICES CONTAINING THE SAME
80
Patent #:
Issue Dt:
09/12/2006
Application #:
10634123
Filing Dt:
08/04/2003
Publication #:
Pub Dt:
01/27/2005
Title:
SEMICONDUCTOR SUBSTRATES INCLUDING I/O REDISTRIBUTION USING WIRE BONDS AND ANISOTROPICALLY CONDUCTIVE FILM, METHODS OF FABRICATION AND ASSEMBLIES INCLUDING SAME
81
Patent #:
Issue Dt:
06/12/2007
Application #:
10634163
Filing Dt:
08/05/2003
Publication #:
Pub Dt:
02/10/2005
Title:
STUD ELECTRODE AND PROCESS FOR MAKING SAME
82
Patent #:
Issue Dt:
12/26/2006
Application #:
10634174
Filing Dt:
08/05/2003
Publication #:
Pub Dt:
02/10/2005
Title:
STRAINED SI/SIGE/SOI ISLANDS AND PROCESSES OF MAKING SAME
83
Patent #:
Issue Dt:
01/24/2006
Application #:
10634212
Filing Dt:
08/05/2003
Title:
MRAM SENSE LAYER ISOLATION
84
Patent #:
Issue Dt:
05/22/2007
Application #:
10634274
Filing Dt:
08/05/2003
Publication #:
Pub Dt:
02/10/2005
Title:
H2 PLASMA TREATMENT
85
Patent #:
Issue Dt:
03/20/2007
Application #:
10634352
Filing Dt:
08/05/2003
Publication #:
Pub Dt:
02/12/2004
Title:
USE OF LINEAR INJECTORS TO DEPOSIT UNIFORM SELECTIVE OZONE TEOS OXIDE FILM BY PULSING REACTANTS ON AND OFF
86
Patent #:
Issue Dt:
09/21/2004
Application #:
10634594
Filing Dt:
08/04/2003
Publication #:
Pub Dt:
02/26/2004
Title:
GLASS ATTACHMENT OVER MICRO-LENS ARRAYS
87
Patent #:
Issue Dt:
02/08/2005
Application #:
10634888
Filing Dt:
08/06/2003
Publication #:
Pub Dt:
04/15/2004
Title:
MICROTRANSFORMER FOR SYSTEM-ON-CHIP POWER SUPPLY
88
Patent #:
Issue Dt:
11/02/2004
Application #:
10634897
Filing Dt:
08/06/2003
Publication #:
Pub Dt:
02/12/2004
Title:
METHODS OF FORMING NON-VOLATILE RESISTANCE VARIABLE DEVICES AND METHODS OF FORMING SILVER SELENIDE COMPRISING STRUCTURES
89
Patent #:
Issue Dt:
06/05/2007
Application #:
10635947
Filing Dt:
08/06/2003
Publication #:
Pub Dt:
02/10/2005
Title:
WIRE BONDERS AND METHODS OF WIRE-BONDING
90
Patent #:
Issue Dt:
07/27/2010
Application #:
10636021
Filing Dt:
08/06/2003
Publication #:
Pub Dt:
02/10/2005
Title:
MICROFEATURE WORKPIECE PROCESSING SYSTEM FOR, E.G., SEMICONDUCTOR WAFER ANALYSIS
91
Patent #:
Issue Dt:
02/15/2005
Application #:
10636035
Filing Dt:
08/06/2003
Publication #:
Pub Dt:
02/10/2005
Title:
METHODS OF FORMING CAPACITORS
92
Patent #:
Issue Dt:
08/21/2007
Application #:
10636038
Filing Dt:
08/06/2003
Publication #:
Pub Dt:
02/10/2005
Title:
METHODS OF FORMING MATERIAL ON A SUBSTRATE, AND A METHOD OF FORMING A FIELD EFFECT TRANSISTOR GATE OXIDE ON A SUBSTRATE
93
Patent #:
Issue Dt:
03/29/2005
Application #:
10636173
Filing Dt:
08/07/2003
Publication #:
Pub Dt:
02/10/2005
Title:
METHOD FOR PROGRAMMING AND ERASING AN NROM CELL
94
Patent #:
Issue Dt:
10/03/2006
Application #:
10636179
Filing Dt:
08/07/2003
Publication #:
Pub Dt:
02/10/2005
Title:
MULTIPLE ERASE BLOCK TAGGING IN A FLASH MEMORY DEVICE
95
Patent #:
Issue Dt:
01/04/2005
Application #:
10636180
Filing Dt:
08/07/2003
Publication #:
Pub Dt:
02/12/2004
Title:
BURIED DIGIT LINE STACK AND PROCESS FOR MAKING SAME
96
Patent #:
Issue Dt:
08/01/2006
Application #:
10636181
Filing Dt:
08/07/2003
Publication #:
Pub Dt:
02/10/2005
Title:
METHOD FOR ERASING AN NROM CELL
97
Patent #:
Issue Dt:
02/15/2005
Application #:
10636332
Filing Dt:
08/06/2003
Publication #:
Pub Dt:
02/26/2004
Title:
STRESS BALANCED SEMICONDUCTOR PACKAGES, METHOD OF FABRICATION AND MODIFIED MOLD SEGMENT
98
Patent #:
Issue Dt:
01/25/2005
Application #:
10636535
Filing Dt:
08/08/2003
Publication #:
Pub Dt:
02/12/2004
Title:
CURRENT SWITCHING SENSOR DETECTOR
99
Patent #:
Issue Dt:
08/14/2007
Application #:
10637031
Filing Dt:
08/06/2003
Publication #:
Pub Dt:
02/12/2004
Title:
DESCRIPTOR FOR IDENTIFYING A DEFECTIVE DIE SITE
100
Patent #:
Issue Dt:
12/11/2007
Application #:
10637096
Filing Dt:
08/08/2003
Publication #:
Pub Dt:
02/12/2004
Title:
PROCESS FLOW FOR BUILDING MRAM STRUCTURES
Assignor
1
Exec Dt:
06/29/2018
Assignee
1
8000 S. FEDERAL WAY
BOISE, IDAHO 83707
Correspondence name and address
WSGR, C/O QUI LU FLOOD, SENIOR PARALEGAL
ONE MARKET, SPEAR TOWER, SUITE 3300
SAN FRANCISCO, CA 94105

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