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Reel/Frame:	047243/0001			Pages:	959
		Recorded:	08/23/2018
Attorney Dkt #:	4816.238
Conveyance:	RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).

Total properties: 17987
Page 88 of 180
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Patent #:	7374964	Issue Dt:	05/20/2008	Application #:	11055380	Filing Dt:	02/10/2005
Publication #:	US20060177975	Pub Dt:	08/10/2006
Title:	ATOMIC LAYER DEPOSITION OF CEO2/AL2O3 FILMS AS GATE DIELECTRICS

Patent #:	7259581	Issue Dt:	08/21/2007	Application #:	11057500	Filing Dt:	02/14/2005
Publication #:	US20060181298	Pub Dt:	08/17/2006
Title:	METHOD FOR TESTING SEMICONDUCTOR COMPONENTS

Patent #:	7072923	Issue Dt:	07/04/2006	Application #:	11057596	Filing Dt:	02/15/2005
Publication #:	US20050149591	Pub Dt:	07/07/2005
Title:	METHOD AND APPARATUS FOR GENERATING DETERMINISTIC, NON-REPEATING, PSEUDO-RANDOM ADDRESSES

Patent #:	7154778	Issue Dt:	12/26/2006	Application #:	11057634	Filing Dt:	02/14/2005
Publication #:	US20050199947	Pub Dt:	09/15/2005
Title:	NANOCRYSTAL WRITE ONCE READ ONLY MEMORY FOR ARCHIVAL STORAGE

Patent #:	7183191	Issue Dt:	02/27/2007	Application #:	11057921	Filing Dt:	02/15/2005
Publication #:	US20050164429	Pub Dt:	07/28/2005
Title:	METHOD FOR FABRICATING A CHIP SCALE PACKAGE USING WAFER LEVEL PROCESSING

Patent #:	7327034	Issue Dt:	02/05/2008	Application #:	11058140	Filing Dt:	02/15/2005
Publication #:	US20050148182	Pub Dt:	07/07/2005
Title:	COMPOSITIONS FOR PLANARIZATION OF METAL-CONTAINING SURFACES USING HALOGENS AND HALIDE SALTS

Patent #:	7399666	Issue Dt:	07/15/2008	Application #:	11058563	Filing Dt:	02/15/2005
Publication #:	US20060183272	Pub Dt:	08/17/2006
Title:	ATOMIC LAYER DEPOSITION OF ZR3N4/ZRO2 FILMS AS GATE DIELECTRICS

Patent #:	7099180	Issue Dt:	08/29/2006	Application #:	11058797	Filing Dt:	02/15/2005
Publication #:	US20060181922	Pub Dt:	08/17/2006
Title:	PHASE CHANGE MEMORY BITS RESET THROUGH A SERIES OF PULSES OF INCREASING AMPLITUDE

Patent #:	7400124	Issue Dt:	07/15/2008	Application #:	11059093	Filing Dt:	02/15/2005
Publication #:	US20060181254	Pub Dt:	08/17/2006
Title:	APPARATUS AND METHODS FOR REGULATED VOLTAGE

Patent #:	7126317	Issue Dt:	10/24/2006	Application #:	11059135	Filing Dt:	02/15/2005
Publication #:	US20050275390	Pub Dt:	12/15/2005
Title:	APPARATUS AND METHODS FOR REGULATED VOLTAGE

Patent #:	7200052	Issue Dt:	04/03/2007	Application #:	11059136	Filing Dt:	02/15/2005
Publication #:	US20060181936	Pub Dt:	08/17/2006
Title:	APPARATUS AND METHODS FOR REGULATED VOLTAGE

Patent #:	7192820	Issue Dt:	03/20/2007	Application #:	11059294	Filing Dt:	02/16/2005
Publication #:	US20050185446	Pub Dt:	08/25/2005
Title:	METHOD FOR REDUCING NON-UNIFORMITY OR TOPOGRAPHY VARIATION BETWEEN AN ARRAY AND CIRCUITRY IN A PROCESS FOR MANUFACTURING SEMICONDUCTOR INTEGRATED NON-VOLATILE MEMORY DEVICES

Patent #:	7229905	Issue Dt:	06/12/2007	Application #:	11059593	Filing Dt:	02/16/2005
Publication #:	US20050148116	Pub Dt:	07/07/2005
Title:	ALIGNMENT AND ORIENTATION FEATURES FOR A SEMICONDUCTOR PACKAGE

Patent #:	7489002	Issue Dt:	02/10/2009	Application #:	11059723	Filing Dt:	02/16/2005
Publication #:	US20050145911	Pub Dt:	07/07/2005
Title:	MEMORY HAVING A VERTICAL TRANSISTOR

Patent #:	7217634	Issue Dt:	05/15/2007	Application #:	11059770	Filing Dt:	02/17/2005
Publication #:	US20060183294	Pub Dt:	08/17/2006
Title:	METHODS OF FORMING INTEGRATED CIRCUITRY

Patent #:	6980461	Issue Dt:	12/27/2005	Application #:	11061069	Filing Dt:	02/18/2005
Publication #:	US20050162931	Pub Dt:	07/28/2005
Title:	REFERENCE CURRENT GENERATOR, AND METHOD OF PROGRAMMING, ADJUSTING AND/OR OPERATING SAME

Patent #:	7289347	Issue Dt:	10/30/2007	Application #:	11062075	Filing Dt:	02/18/2005
Publication #:	US20050146946	Pub Dt:	07/07/2005
Title:	SYSTEM AND METHOD FOR OPTICALLY INTERCONNECTING MEMORY DEVICES

Patent #:	7317200	Issue Dt:	01/08/2008	Application #:	11062436	Filing Dt:	02/23/2005
Publication #:	US20060186394	Pub Dt:	08/24/2006
Title:	SNSE-BASED LIMITED REPROGRAMMABLE CELL

Patent #:	7120054	Issue Dt:	10/10/2006	Application #:	11062661	Filing Dt:	02/22/2005
Publication #:	US20050141282	Pub Dt:	06/30/2005
Title:	PRECONDITIONING GLOBAL BITLINES

Patent #:	7325089	Issue Dt:	01/29/2008	Application #:	11062768	Filing Dt:	02/22/2005
Publication #:	US20050201153	Pub Dt:	09/15/2005
Title:	CONTROLLER FOR REFRESHING MEMORIES

Patent #:	7607177	Issue Dt:	10/20/2009	Application #:	11063090	Filing Dt:	02/22/2005
Publication #:	US20050185067	Pub Dt:	08/25/2005
Title:	SECURE COMPACT FLASH

Patent #:	7154354	Issue Dt:	12/26/2006	Application #:	11063132	Filing Dt:	02/22/2005
Publication #:	US20050140462	Pub Dt:	06/30/2005
Title:	HIGH PERMEABILITY LAYERED MAGNETIC FILMS TO REDUCE NOISE IN HIGH SPEED INTERCONNECTION

Patent #:	7413342	Issue Dt:	08/19/2008	Application #:	11063173	Filing Dt:	02/22/2005
Publication #:	US20060190210	Pub Dt:	08/24/2006
Title:	DRAM TEMPERATURE MEASUREMENT SYSTEM

Patent #:	7009885	Issue Dt:	03/07/2006	Application #:	11063383	Filing Dt:	02/22/2005
Publication #:	US20050162920	Pub Dt:	07/28/2005
Title:	CIRCUIT AND METHOD FOR REDUCING LEAKAGE CURRENT IN A ROW DRIVER CIRCUIT IN A FLASH MEMORY DURING A STANDBY MODE OF OPERATION

Patent #:	7285442	Issue Dt:	10/23/2007	Application #:	11063403	Filing Dt:	02/22/2005
Publication #:	US20050146010	Pub Dt:	07/07/2005
Title:	STACKABLE CERAMIC FBGA FOR HIGH THERMAL APPLICATIONS

Patent #:	7498247	Issue Dt:	03/03/2009	Application #:	11063717	Filing Dt:	02/23/2005
Publication #:	US20060189154	Pub Dt:	08/24/2006
Title:	ATOMIC LAYER DEPOSITION OF HF3N4/HFO2 FILMS AS GATE DIELECTRICS

Patent #:	8330202	Issue Dt:	12/11/2012	Application #:	11063825	Filing Dt:	02/23/2005
Publication #:	US20060186458	Pub Dt:	08/24/2006
Title:	GERMANIUM-SILICON-CARBIDE FLOATING GATES IN MEMORIES

Patent #:	7329946	Issue Dt:	02/12/2008	Application #:	11063963	Filing Dt:	02/23/2005
Publication #:	US20050145885	Pub Dt:	07/07/2005
Title:	I/O ARCHITECTURE FOR INTEGRATED CIRCUIT PACKAGE

Patent #:	7205656	Issue Dt:	04/17/2007	Application #:	11064107	Filing Dt:	02/22/2005
Publication #:	US20060197206	Pub Dt:	09/07/2006
Title:	STACKED DEVICE PACKAGE FOR PERIPHERAL AND CENTER DEVICE PAD LAYOUT DEVICE

Patent #:	7268035	Issue Dt:	09/11/2007	Application #:	11064163	Filing Dt:	02/23/2005
Publication #:	US20050285103	Pub Dt:	12/29/2005
Title:	METHODS OF FORMING SEMICONDUCTOR CONSTRUCTIONS COMPRISING CERIUM OXIDE AND TITANIUM OXIDE

Patent #:	7172465	Issue Dt:	02/06/2007	Application #:	11064344	Filing Dt:	02/22/2005
Publication #:	US20060189175	Pub Dt:	08/24/2006
Title:	EDGE CONNECTOR INCLUDING INTERNAL LAYER CONTACT, PRINTED CIRCUIT BOARD AND ELECTRONIC MODULE INCORPORATING SAME

Patent #:	7122420	Issue Dt:	10/17/2006	Application #:	11064982	Filing Dt:	02/23/2005
Publication #:	US20050158946	Pub Dt:	07/21/2005
Title:	METHODS OF RECESSING CONDUCTIVE MATERIAL AND METHODS OF FORMING CAPACITOR CONSTRUCTIONS

Patent #:	7119568	Issue Dt:	10/10/2006	Application #:	11065016	Filing Dt:	02/24/2005
Publication #:	US20050174138	Pub Dt:	08/11/2005
Title:	METHODS FOR WAFER LEVEL BURN-IN

Patent #:	7365388	Issue Dt:	04/29/2008	Application #:	11065778	Filing Dt:	02/25/2005
Publication #:	US20060192243	Pub Dt:	08/31/2006
Title:	EMBEDDED TRAP DIRECT TUNNEL NON-VOLATILE MEMORY

Patent #:	7701493	Issue Dt:	04/20/2010	Application #:	11066781	Filing Dt:	02/28/2005
Publication #:	US20060192864	Pub Dt:	08/31/2006
Title:	IMAGER ROW-WISE NOISE CORRECTION

Patent #:	7244981	Issue Dt:	07/17/2007	Application #:	11066900	Filing Dt:	02/25/2005
Publication #:	US20060202251	Pub Dt:	09/14/2006
Title:	SCALABLE HIGH PERFORMANCE NON-VOLATILE MEMORY CELLS USING MULTI-MECHANISM CARRIER TRANSPORT

Patent #:	7276760	Issue Dt:	10/02/2007	Application #:	11066905	Filing Dt:	02/25/2005
Publication #:	US20060192240	Pub Dt:	08/31/2006
Title:	LOW POWER MEMORY SUBSYSTEM WITH PROGRESSIVE NON-VOLATILITY

Patent #:	7328379	Issue Dt:	02/05/2008	Application #:	11067326	Filing Dt:	02/25/2005
Publication #:	US20050141303	Pub Dt:	06/30/2005
Title:	LOOK-UP TABLE FOR USE WITH REDUNDANT MEMORY

Patent #:	7139195	Issue Dt:	11/21/2006	Application #:	11067345	Filing Dt:	02/25/2005
Publication #:	US20050201158	Pub Dt:	09/15/2005
Title:	EEPROM MEMORY COMPRISING A NON-VOLATILE REGISTER INTEGRATED INTO THE MEMORY ARRAY THEREOF

Patent #:	6968482	Issue Dt:	11/22/2005	Application #:	11067355	Filing Dt:	02/25/2005
Publication #:	US20050141304	Pub Dt:	06/30/2005
Title:	MEMORY REDUNDANCY WITH PROGRAMMABLE NON-VOLATILE CONTROL

Patent #:	7389451	Issue Dt:	06/17/2008	Application #:	11067356	Filing Dt:	02/25/2005
Publication #:	US20050141305	Pub Dt:	06/30/2005
Title:	MEMORY REDUNDANCY WITH PROGRAMMABLE CONTROL

Patent #:	7209387	Issue Dt:	04/24/2007	Application #:	11067974	Filing Dt:	02/28/2005
Publication #:	US20060023504	Pub Dt:	02/02/2006
Title:	NON-VOLATILE PROGRAMMABLE FUSE APPARATUS IN A FLASH MEMORY WITH PAIRS OF SUPERCELLS PROGRAMMED IN A COMPLEMENTARY FASHION

Patent #:	7224632	Issue Dt:	05/29/2007	Application #:	11070213	Filing Dt:	03/03/2005
Publication #:	US20050146958	Pub Dt:	07/07/2005
Title:	REWRITE PREVENTION IN A VARIABLE RESISTANCE MEMORY

Patent #:	7544987	Issue Dt:	06/09/2009	Application #:	11070415	Filing Dt:	03/02/2005
Publication #:	US20050167726	Pub Dt:	08/04/2005
Title:	NOVEL HIGH-K DIELECTRIC MATERIALS AND PROCESSES FOR MANUFACTURING THEM

Patent #:	7109115	Issue Dt:	09/19/2006	Application #:	11071922	Filing Dt:	03/04/2005
Publication #:	US20050181599	Pub Dt:	08/18/2005
Title:	METHODS OF PROVIDING OHMIC CONTACT

Patent #:	7545009	Issue Dt:	06/09/2009	Application #:	11072159	Filing Dt:	03/04/2005
Publication #:	US20050161721	Pub Dt:	07/28/2005
Title:	WORD LINES FOR MEMORY CELLS

Patent #:	7202543	Issue Dt:	04/10/2007	Application #:	11072456	Filing Dt:	03/07/2005
Publication #:	US20060197169	Pub Dt:	09/07/2006
Title:	METHOD AND STRUCTURE TO REDUCE OPTICAL CROSSTALK IN A SOLID STATE IMAGER

Patent #:	7141824	Issue Dt:	11/28/2006	Application #:	11073773	Filing Dt:	03/07/2005
Publication #:	US20050146934	Pub Dt:	07/07/2005
Title:	TRANSISTOR WITH VARIABLE ELECTRON AFFINITY GATE

Patent #:	7038265	Issue Dt:	05/02/2006	Application #:	11073800	Filing Dt:	03/07/2005
Publication #:	US20050161710	Pub Dt:	07/28/2005
Title:	CAPACITOR HAVING TANTALUM OXYNITRIDE FILM AND METHOD FOR MAKING SAME

Patent #:	7510966	Issue Dt:	03/31/2009	Application #:	11074106	Filing Dt:	03/07/2005
Publication #:	US20060197225	Pub Dt:	09/07/2006
Title:	ELECTRICALLY CONDUCTIVE LINE, METHOD OF FORMING AN ELECTRICALLY CONDUCTIVE LINE, AND METHOD OF REDUCING TITANIUM SILICIDE AGGLOMERATION IN FABRICATION OF TITANIUM SILICIDE OVER POLYSILICON TRANSISTOR GATE LINES

Patent #:	7254074	Issue Dt:	08/07/2007	Application #:	11074518	Filing Dt:	03/07/2005
Publication #:	US20060198220	Pub Dt:	09/07/2006
Title:	OPEN DIGIT LINE ARRAY ARCHITECTURE FOR A MEMORY ARRAY

Patent #:	7445996	Issue Dt:	11/04/2008	Application #:	11074563	Filing Dt:	03/08/2005
Publication #:	US20060205146	Pub Dt:	09/14/2006
Title:	LOW RESISTANCE PERIPHERAL CONTACTS WHILE MAINTAINING DRAM ARRAY INTEGRITY

Patent #:	7235498	Issue Dt:	06/26/2007	Application #:	11075187	Filing Dt:	03/08/2005
Publication #:	US20050153569	Pub Dt:	07/14/2005
Title:	PROCESS FOR GROWING A DIELECTRIC LAYER ON A SILICON-CONTAINING SURFACE USING A MIXTURE OF N2O AND O3

Patent #:	7446415	Issue Dt:	11/04/2008	Application #:	11075770	Filing Dt:	03/09/2005
Publication #:	US20060046454	Pub Dt:	03/02/2006
Title:	METHOD FOR FILLING ELECTRICALLY DIFFERENT FEATURES

Patent #:	8241708	Issue Dt:	08/14/2012	Application #:	11075771	Filing Dt:	03/09/2005
Publication #:	US20060204651	Pub Dt:	09/14/2006
Title:	FORMATION OF INSULATOR OXIDE FILMS WITH ACID OR BASE CATALYZED HYDROLYSIS OF ALKOXIDES IN SUPERCRITICAL CARBON DIOXIDE

Patent #:	7170171	Issue Dt:	01/30/2007	Application #:	11075967	Filing Dt:	03/09/2005
Publication #:	US20050156314	Pub Dt:	07/21/2005
Title:	SUPPORT RING FOR USE WITH A CONTACT PAD AND SEMICONDUCTOR DEVICE COMPONENTS INCLUDING THE SAME

Patent #:	7332388	Issue Dt:	02/19/2008	Application #:	11076497	Filing Dt:	03/08/2005
Publication #:	US20060205133	Pub Dt:	09/14/2006
Title:	METHOD TO SIMULTANEOUSLY FORM BOTH FULLY SILICIDED AND PARTIALLY SILICIDED DUAL WORK FUNCTION TRANSISTOR GATES DURING THE MANUFACTURE OF A SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICES, AND SYSTEMS INCLUDING SAME

Patent #:	7244659	Issue Dt:	07/17/2007	Application #:	11076774	Filing Dt:	03/10/2005
Publication #:	US20060205128	Pub Dt:	09/14/2006
Title:	INTEGRATED CIRCUITS AND METHODS OF FORMING A FIELD EFFECT TRANSISTOR

Patent #:	7323412	Issue Dt:	01/29/2008	Application #:	11078537	Filing Dt:	03/10/2005
Publication #:	US20050159018	Pub Dt:	07/21/2005
Title:	ATOMIC LAYER DEPOSITION METHODS, AND METHODS OF FORMING MATERIALS OVER SEMICONDUCTOR SUBSTRATES

Patent #:	7307896	Issue Dt:	12/11/2007	Application #:	11078764	Filing Dt:	03/11/2005
Publication #:	US20060203599	Pub Dt:	09/14/2006
Title:	DETECTION OF ROW-TO-ROW SHORTS AND OTHER ROW DECODE DEFECTS IN MEMORY DEVICES

Patent #:	7444458	Issue Dt:	10/28/2008	Application #:	11079407	Filing Dt:	03/14/2005
Publication #:	US20050160216	Pub Dt:	07/21/2005
Title:	METHOD FOR ASSIGNING ADDRESSES TO MEMORY DEVICES

Patent #:	7187581	Issue Dt:	03/06/2007	Application #:	11079590	Filing Dt:	03/14/2005
Publication #:	US20050157580	Pub Dt:	07/21/2005
Title:	SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING SAME

Patent #:	7428284	Issue Dt:	09/23/2008	Application #:	11080105	Filing Dt:	03/14/2005
Publication #:	US20060203948	Pub Dt:	09/14/2006
Title:	PHASE DETECTOR AND METHOD PROVIDING RAPID LOCKING OF DELAY-LOCK LOOPS

Patent #:	7424634	Issue Dt:	09/09/2008	Application #:	11080236	Filing Dt:	03/14/2005
Publication #:	US20060224342	Pub Dt:	10/05/2006
Title:	SYSTEM AND METHOD FOR REDUCING JITTER OF SIGNALS COUPLED THROUGH ADJACENT SIGNAL LINES

Patent #:	7200047	Issue Dt:	04/03/2007	Application #:	11080351	Filing Dt:	03/14/2005
Publication #:	US20050201161	Pub Dt:	09/15/2005
Title:	HIGH VOLTAGE POSITIVE AND NEGATIVE TWO-PHASE DISCHARGE SYSTEM AND METHOD FOR CHANNEL ERASE IN FLASH MEMORY DEVICES

Patent #:	7217974	Issue Dt:	05/15/2007	Application #:	11080443	Filing Dt:	03/16/2005
Publication #:	US20050156230	Pub Dt:	07/21/2005
Title:	OUTPUT PREDICTION LOGIC CIRCUITS WITH ULTRA-THIN VERTICAL TRANSISTORS AND METHODS OF FORMATION

Patent #:	7247520	Issue Dt:	07/24/2007	Application #:	11081236	Filing Dt:	03/15/2005
Publication #:	US20050156300	Pub Dt:	07/21/2005
Title:	MICROELECTRONIC COMPONENT ASSEMBLIES AND MICROELECTRONIC COMPONENT LEAD FRAME STRUCTURES

Patent #:	7422948	Issue Dt:	09/09/2008	Application #:	11081336	Filing Dt:	03/16/2005
Publication #:	US20050181565	Pub Dt:	08/18/2005
Title:	THRESHOLD VOLTAGE ADJUSTMENT FOR LONG CHANNEL TRANSISTORS

Patent #:	7244678	Issue Dt:	07/17/2007	Application #:	11081413	Filing Dt:	03/16/2005
Publication #:	US20050159086	Pub Dt:	07/21/2005
Title:	METHODS FOR PLANARIZATION OF GROUP VIII METAL-CONTAINING SURFACES USING COMPLEXING AGENTS

Patent #:	7298025	Issue Dt:	11/20/2007	Application #:	11081925	Filing Dt:	03/15/2005
Publication #:	US20050156294	Pub Dt:	07/21/2005
Title:	MICROELECTRONIC COMPONENT ASSEMBLIES AND MICROELECTRONIC COMPONENT LEAD FRAME STRUCTURES

Patent #:	7425472	Issue Dt:	09/16/2008	Application #:	11082066	Filing Dt:	03/16/2005
Publication #:	US20050158919	Pub Dt:	07/21/2005
Title:	SEMICONDUCTOR FUSES AND SEMICONDUCTOR DEVICES CONTAINING THE SAME

Patent #:	7139852	Issue Dt:	11/21/2006	Application #:	11082572	Filing Dt:	03/16/2005
Publication #:	US20050182894	Pub Dt:	08/18/2005
Title:	MEMORY BUS POLARITY INDICATOR SYSTEM AND METHOD FOR REDUCING THE AFFECTS OF SIMULTANEOUS SWITCHING OUTPUTS (SSO) ON MEMORY BUS TIMING

Patent #:	7262555	Issue Dt:	08/28/2007	Application #:	11083433	Filing Dt:	03/17/2005
Publication #:	US20060208649	Pub Dt:	09/21/2006
Title:	METHOD AND SYSTEM FOR DISCRETELY CONTROLLABLE PLASMA PROCESSING

Patent #:	7199593	Issue Dt:	04/03/2007	Application #:	11083506	Filing Dt:	03/18/2005
Publication #:	US20050161256	Pub Dt:	07/28/2005
Title:	METHODS FOR MEASURING PARASITIC CAPACITANCE AND INDUCTANCE OF I/O LEADS ON AN ELECTRICAL COMPONENT USING A NETWORK ANALYZER

Patent #:	7358178	Issue Dt:	04/15/2008	Application #:	11083518	Filing Dt:	03/18/2005
Publication #:	US20050164486	Pub Dt:	07/28/2005
Title:	SEMICONDUCTOR SUBSTRATES INCLUDING I/O REDISTRIBUTION USING WIRE BONDS AND ANISOTROPICALLY CONDUCTIVE FILM, METHODS OF FABRICATION AND ASSEMBLIES INCLUDING SAME

Patent #:	7139896	Issue Dt:	11/21/2006	Application #:	11084338	Filing Dt:	03/17/2005
Publication #:	US20050162935	Pub Dt:	07/28/2005
Title:	LINEAR AND NON-LINEAR OBJECT MANAGEMENT

Patent #:	7697357	Issue Dt:	04/13/2010	Application #:	11084345	Filing Dt:	03/17/2005
Publication #:	US20060209604	Pub Dt:	09/21/2006
Title:	NEGATIVE VOLTAGE DRIVING FOR THE DIGIT LINE ISOLATION GATES

Patent #:	7085908	Issue Dt:	08/01/2006	Application #:	11084459	Filing Dt:	03/17/2005
Publication #:	US20050166025	Pub Dt:	07/28/2005
Title:	LINEAR OBJECT MANAGEMENT FOR A RANGE OF FLASH MEMORY

Patent #:	7611959	Issue Dt:	11/03/2009	Application #:	11084968	Filing Dt:	03/21/2005
Publication #:	US20050164521	Pub Dt:	07/28/2005
Title:	ZR-SN-TI-O FILMS

Patent #:	7348205	Issue Dt:	03/25/2008	Application #:	11085009	Filing Dt:	03/21/2005
Publication #:	US20050157573	Pub Dt:	07/21/2005
Title:	METHOD OF FORMING RESISTANCE VARIABLE DEVICES

Patent #:	7276765	Issue Dt:	10/02/2007	Application #:	11085018	Filing Dt:	03/21/2005
Publication #:	US20050161741	Pub Dt:	07/28/2005
Title:	BURIED TRANSISTORS FOR SILICON ON INSULATOR TECHNOLOGY

Patent #:	7155565	Issue Dt:	12/26/2006	Application #:	11085552	Filing Dt:	03/22/2005
Publication #:	US20050162879	Pub Dt:	07/28/2005
Title:	AUTOMATIC LEARNING IN A CAM

Patent #:	7492196	Issue Dt:	02/17/2009	Application #:	11085563	Filing Dt:	03/22/2005
Publication #:	US20050162203	Pub Dt:	07/28/2005
Title:	LOW INJECTION CHARGE PUMP

Patent #:	7042778	Issue Dt:	05/09/2006	Application #:	11085855	Filing Dt:	03/22/2005
Publication #:	US20050162967	Pub Dt:	07/28/2005
Title:	FLASH ARRAY IMPLEMENTATION WITH LOCAL AND GLOBAL BIT LINES

Patent #:	7167399	Issue Dt:	01/23/2007	Application #:	11085936	Filing Dt:	03/22/2005
Publication #:	US20050162909	Pub Dt:	07/28/2005
Title:	FLASH MEMORY DEVICE WITH A VARIABLE ERASE PULSE

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Publication #:	US20050161796	Pub Dt:	07/28/2005
Title:	METHODS FOR STACKING WIRE-BONDED INTEGRATED CIRCUIT DICE ON FLIP-CHIP BONDED INTEGRATED CIRCUIT DICE

Patent #:	7312164	Issue Dt:	12/25/2007	Application #:	11087212	Filing Dt:	03/23/2005
Publication #:	US20050164500	Pub Dt:	07/28/2005
Title:	SELECTIVE PASSIVATION OF EXPOSED SILICON

Patent #:	7273796	Issue Dt:	09/25/2007	Application #:	11087218	Filing Dt:	03/23/2005
Publication #:	US20060216906	Pub Dt:	09/28/2006
Title:	METHODS OF FORMING TRENCH ISOLATION IN THE FABRICATION OF INTEGRATED CIRCUITRY AND METHODS OF FABRICATING INTEGRATED CIRCUITRY

Patent #:	7262637	Issue Dt:	08/28/2007	Application #:	11087293	Filing Dt:	03/22/2005
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Title:	OUTPUT BUFFER AND METHOD HAVING A SUPPLY VOLTAGE INSENSITIVE SLEW RATE

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Title:	METHOD AND APPARATUS FOR STANDBY POWER REDUCTION IN SEMICONDUCTOR DEVICES

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Title:	CONDUCTIVE STRUCTURE FOR MICROELECTRONIC DEVICES AND METHODS OF FABRICATING SUCH STRUCTURES

Patent #:	7251177	Issue Dt:	07/31/2007	Application #:	11089132	Filing Dt:	03/24/2005
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Title:	SKEWED SENSE AMP FOR VARIABLE RESISTANCE MEMORY SENSING

Patent #:	7339839	Issue Dt:	03/04/2008	Application #:	11089382	Filing Dt:	03/24/2005
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Title:	TRIGGERING OF IO EQUILIBRATING ENDING SIGNAL WITH FIRING OF COLUMN ACCESS SIGNAL

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Title:	HIGH DENSITY SEMICONDUCTOR MEMORY

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Title:	METHODS FOR WAFER-LEVEL PACKAGING OF MICROELECTRONIC DEVICES AND MICROELECTRONIC DEVICES FORMED BY SUCH METHODS

Patent #:	7238616	Issue Dt:	07/03/2007	Application #:	11090204	Filing Dt:	03/28/2005
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Title:	PHOTO-ASSISTED METHOD FOR SEMICONDUCTOR FABRICATION

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Patent #:	7075819	Issue Dt:	07/11/2006	Application #:	11091258	Filing Dt:	03/28/2005
Publication #:	US20050169046	Pub Dt:	08/04/2005
Title:	CLOSED FLUX MAGNETIC MEMORY

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Title:	MEMORY CIRCUITRY WITH OXYGEN DIFFUSION BARRIER LAYER RECEIVED OVER A WELL BASE

100

Patent #:	7504767	Issue Dt:	03/17/2009	Application #:	11091610	Filing Dt:	03/28/2005
Publication #:	US20050168130	Pub Dt:	08/04/2005
Title:	ELECTRODE STRUCTURES, DISPLAY DEVICES CONTAINING THE SAME

Assignor

U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT

Exec Dt:

06/29/2018

Assignee

MICRON TECHNOLOGY, INC.

8000 S. FEDERAL WAY

BOISE, IDAHO 83707

Correspondence name and address
	WSGR, C/O QUI LU FLOOD, SENIOR PARALEGAL
	ONE MARKET, SPEAR TOWER, SUITE 3300
	SAN FRANCISCO, CA 94105

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