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NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:047540/0001   Pages: 843
Recorded: 07/13/2018
Attorney Dkt #:509265/2155
Conveyance: SECURITY INTEREST (SEE DOCUMENT FOR DETAILS).
1
Patent #:
Issue Dt:
07/03/2007
Application #:
10122381
Filing Dt:
04/16/2002
Publication #:
Pub Dt:
11/06/2003
Title:
APPARATUS AND METHOD TO FACILITATE HIERARCHICAL NETLIST CHECKING
2
Patent #:
Issue Dt:
04/05/2005
Application #:
10123050
Filing Dt:
04/12/2002
Publication #:
Pub Dt:
10/16/2003
Title:
LARGE SCALE SYNTHESIS OF GERMANIUM SELENIDE GLASS AND GERMANIUM SELENIDE GLASS COMPOUNDS
3
Patent #:
Issue Dt:
03/25/2003
Application #:
10123328
Filing Dt:
04/15/2002
Title:
METHOD FOR FABRICATING SEMICONDUCTOR COMPONENTS WITH TERMINAL CONTACTS HAVING ALTERNATE ELECTRICAL PATHS
4
Patent #:
Issue Dt:
08/19/2003
Application #:
10123579
Filing Dt:
04/15/2002
Publication #:
Pub Dt:
10/17/2002
Title:
METHOD OF MANUFACTURING A SINGLE ELECTRON RESISTOR MEMORY DEVICE
5
Patent #:
Issue Dt:
04/08/2003
Application #:
10123580
Filing Dt:
04/15/2002
Publication #:
Pub Dt:
10/17/2002
Title:
METHOD OF MANUFACTURING A SINGLE ELECTRON RESISTOR MEMORY DEVICE
6
Patent #:
Issue Dt:
10/02/2007
Application #:
10123827
Filing Dt:
04/15/2002
Publication #:
Pub Dt:
10/16/2003
Title:
SEMICONDUCTOR INTEGRATED CIRCUIT PACKAGE HAVING ELECTRICALLY DISCONNECTED SOLDER BALLS FOR MOUNTING
7
Patent #:
Issue Dt:
04/27/2004
Application #:
10123874
Filing Dt:
04/16/2002
Publication #:
Pub Dt:
12/05/2002
Title:
METHOD AND CIRCUIT FOR TIMING DYNAMIC READING OF A MEMORY CELL WITH CONTROL OF THE INTEGRATION TIME
8
Patent #:
Issue Dt:
08/12/2008
Application #:
10124019
Filing Dt:
04/16/2002
Publication #:
Pub Dt:
02/27/2003
Title:
VERTICAL TRANSISTOR WITH HORIZONTAL GATE LAYERS
9
Patent #:
Issue Dt:
04/03/2007
Application #:
10125331
Filing Dt:
04/18/2002
Publication #:
Pub Dt:
10/23/2003
Title:
REDUCING DATA HAZARDS IN PIPELINED PROCESSORS TO PROVIDE HIGH PROCESSOR UTILIZATION
10
Patent #:
Issue Dt:
06/01/2004
Application #:
10125979
Filing Dt:
04/19/2002
Publication #:
Pub Dt:
08/15/2002
Title:
TRANSISTOR DEVICES
11
Patent #:
Issue Dt:
02/14/2006
Application #:
10126274
Filing Dt:
04/18/2002
Publication #:
Pub Dt:
10/23/2003
Title:
METHOD FOR MEDIA CONTENT PRESENTATION IN CONSIDERATION OF SYSTEM POWER
12
Patent #:
Issue Dt:
02/20/2007
Application #:
10126348
Filing Dt:
04/18/2002
Publication #:
Pub Dt:
10/23/2003
Title:
WAFER-LEVEL TEST STRUCTURE FOR EDGE-EMITTING SEMICONDUCTOR LASERS
13
Patent #:
Issue Dt:
03/01/2005
Application #:
10126402
Filing Dt:
04/19/2002
Publication #:
Pub Dt:
10/23/2003
Title:
ACCURATELY TUNING RESISTORS
14
Patent #:
Issue Dt:
06/03/2003
Application #:
10126412
Filing Dt:
04/19/2002
Publication #:
Pub Dt:
12/05/2002
Title:
TRCD MARGIN
15
Patent #:
Issue Dt:
11/19/2002
Application #:
10126413
Filing Dt:
04/19/2002
Publication #:
Pub Dt:
12/05/2002
Title:
TRCD MARGIN
16
Patent #:
Issue Dt:
02/17/2004
Application #:
10126424
Filing Dt:
04/19/2002
Publication #:
Pub Dt:
12/05/2002
Title:
TRCD MARGIN
17
Patent #:
Issue Dt:
12/10/2002
Application #:
10126730
Filing Dt:
04/19/2002
Publication #:
Pub Dt:
12/05/2002
Title:
TRCD MARGIN
18
Patent #:
Issue Dt:
05/11/2004
Application #:
10128176
Filing Dt:
04/23/2002
Publication #:
Pub Dt:
11/14/2002
Title:
GATE AREA RELIEF STRIP FOR A MOLDED I/C PACKAGE
19
Patent #:
Issue Dt:
03/04/2008
Application #:
10128373
Filing Dt:
04/24/2002
Publication #:
Pub Dt:
10/30/2003
Title:
ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT HAVING A RING OSCILLATOR TIMER CIRCUIT
20
Patent #:
Issue Dt:
03/02/2004
Application #:
10131017
Filing Dt:
04/24/2002
Publication #:
Pub Dt:
10/30/2003
Title:
PROMOTING ADHESION OF FLUOROPOLYMER FILMS TO SEMICONDUCTOR SUBSTRATES
21
Patent #:
Issue Dt:
02/03/2004
Application #:
10132032
Filing Dt:
04/25/2002
Publication #:
Pub Dt:
10/30/2003
Title:
DRIVER CONTROL CIRCUIT
22
Patent #:
Issue Dt:
12/10/2002
Application #:
10132043
Filing Dt:
04/25/2002
Publication #:
Pub Dt:
08/22/2002
Title:
HEAT SINK CHIP PACKAGE
23
Patent #:
Issue Dt:
02/10/2004
Application #:
10132447
Filing Dt:
04/26/2002
Publication #:
Pub Dt:
01/22/2004
Title:
MAGNETORESISTIVE MEMORY OR SENSOR DEVICES HAVING IMPROVED SWITCHING PROPERTIES AND METHOD OF FABRICATION
24
Patent #:
Issue Dt:
08/17/2004
Application #:
10132835
Filing Dt:
04/25/2002
Publication #:
Pub Dt:
10/30/2003
Title:
ELECTRICAL INTERCONNECT USING LOCALLY CONDUCTIVE ADHESIVE
25
Patent #:
Issue Dt:
04/20/2004
Application #:
10133231
Filing Dt:
04/26/2002
Publication #:
Pub Dt:
12/19/2002
Title:
METHOD AND CIRCUIT FOR GENERATING REFERENCE VOLTAGES FOR READING A MULTILEVEL MEMORY CELL
26
Patent #:
Issue Dt:
09/06/2005
Application #:
10133250
Filing Dt:
04/26/2002
Publication #:
Pub Dt:
02/27/2003
Title:
METHOD FOR ASSEMBLING SEMICONDUCTOR DIE PACKAGES WITH STANDARD BALL GRID ARRAY FOOTPRINT
27
Patent #:
Issue Dt:
07/03/2007
Application #:
10133625
Filing Dt:
04/29/2002
Publication #:
Pub Dt:
10/30/2003
Title:
PROVIDING A CHAIN OF TOKENIZED ERROR AND STATE INFORMATION FOR A CALL STACK
28
Patent #:
Issue Dt:
05/20/2008
Application #:
10133947
Filing Dt:
04/25/2002
Publication #:
Pub Dt:
10/30/2003
Title:
ATOMIC LAYER DEPOSITION METHODS AND CHEMICAL VAPOR DEPOSITION METHODS
29
Patent #:
Issue Dt:
12/02/2003
Application #:
10134837
Filing Dt:
04/29/2002
Publication #:
Pub Dt:
09/12/2002
Title:
ARRAY ORGANIZATION FOR HIGH-PERFORMANCE MEMORY DEVICES
30
Patent #:
Issue Dt:
08/10/2004
Application #:
10135563
Filing Dt:
05/01/2002
Publication #:
Pub Dt:
11/07/2002
Title:
CURRENT SWITCHING SENSOR DETECTOR
31
Patent #:
Issue Dt:
08/31/2004
Application #:
10135921
Filing Dt:
04/30/2002
Publication #:
Pub Dt:
10/30/2003
Title:
PROTECTIVE LAYERS FOR MRAM DEVICES
32
Patent #:
Issue Dt:
02/17/2004
Application #:
10136123
Filing Dt:
05/01/2002
Publication #:
Pub Dt:
10/24/2002
Title:
BALL GRID ARRAY CHIP PACKAGES HAVING IMPROVED TESTING AND STACKING CHARACTERISTICS
33
Patent #:
Issue Dt:
12/28/2004
Application #:
10136186
Filing Dt:
05/01/2002
Publication #:
Pub Dt:
10/16/2003
Title:
SEMICONDUCTOR PACKAGES WITH LEADFRAME GRID ARRAYS AND COMPONENTS AND METHODS FOR MAKING THE SAME
34
Patent #:
Issue Dt:
09/27/2005
Application #:
10136583
Filing Dt:
04/30/2002
Title:
FILE MANAGEMENT OF ONE-TIME-PROGRAMMABLE NONVOLATILE MEMORY DEVICES
35
Patent #:
Issue Dt:
03/11/2003
Application #:
10136742
Filing Dt:
04/30/2002
Publication #:
Pub Dt:
03/06/2003
Title:
LOW VOLTAGE CHARGE PUMP APPARATUS AND METHOD
36
Patent #:
Issue Dt:
06/01/2004
Application #:
10136771
Filing Dt:
04/30/2002
Publication #:
Pub Dt:
09/05/2002
Title:
PROCESS FOR THE FORMATION OF RUSIXOY-CONTAINING BARRIER LAYERS FOR HIGH-K DIELECTRICS
37
Patent #:
Issue Dt:
09/15/2009
Application #:
10137058
Filing Dt:
05/02/2002
Publication #:
Pub Dt:
11/06/2003
Title:
ATOMIC LAYER DEPOSITION AND CONVERSION
38
Patent #:
Issue Dt:
03/30/2004
Application #:
10137293
Filing Dt:
05/03/2002
Publication #:
Pub Dt:
09/19/2002
Title:
BARRIER LAYER ASSOCIATED WITH A CONDUCTOR LAYER IN DAMASCENE STRUCTURES
39
Patent #:
Issue Dt:
10/04/2005
Application #:
10137384
Filing Dt:
05/03/2002
Publication #:
Pub Dt:
11/06/2003
Title:
METHOD OF FABRICATING A SEMICONDUCTOR MULTILEVEL INTERCONNECT STRUCTURE
40
Patent #:
Issue Dt:
05/16/2006
Application #:
10137499
Filing Dt:
05/02/2002
Publication #:
Pub Dt:
11/06/2003
Title:
ATOMIC LAYER-DEPOSITED LAAIO3 FILMS FOR GATE DIELECTRICS
41
Patent #:
Issue Dt:
04/20/2004
Application #:
10137500
Filing Dt:
05/02/2002
Publication #:
Pub Dt:
11/06/2003
Title:
LOW REMANENCE FLUX CONCENTRATOR FOR MRAM DEVICES
42
Patent #:
Issue Dt:
12/26/2006
Application #:
10137753
Filing Dt:
05/02/2002
Publication #:
Pub Dt:
11/06/2003
Title:
RATE POLICING ALGORITHM FOR PACKET FLOWS
43
Patent #:
Issue Dt:
05/13/2003
Application #:
10137755
Filing Dt:
05/02/2002
Publication #:
Pub Dt:
09/12/2002
Title:
MODULE ASSEMBLY FOR STACKED BGA PACKAGES
44
Patent #:
Issue Dt:
01/27/2004
Application #:
10139299
Filing Dt:
05/02/2002
Publication #:
Pub Dt:
09/12/2002
Title:
METHODS AND APPARATUSES FOR MONITORING AND CONTROLLING MECHANICAL OR CHEMICAL-MECHANICAL PLANARIZATION OF MICROELECTRONIC SUBSTRATE ASSEMBLIES
45
Patent #:
Issue Dt:
09/07/2004
Application #:
10139987
Filing Dt:
05/07/2002
Publication #:
Pub Dt:
04/17/2003
Title:
EVEN NUCLEATION BETWEEN SILICON AND OXIDE SURFACES FOR THIN SILICON NITRIDE FILM GROWTH
46
Patent #:
Issue Dt:
10/05/2004
Application #:
10140296
Filing Dt:
05/06/2002
Publication #:
Pub Dt:
09/12/2002
Title:
MULTIPLE OXIDE THICKNESSES FOR MERGED MEMORY AND LOGIC APPLICATIONS
47
Patent #:
Issue Dt:
05/03/2005
Application #:
10140297
Filing Dt:
05/06/2002
Publication #:
Pub Dt:
09/12/2002
Title:
MULTIPLE OXIDE THICKNESSES FOR MERGED MEMORY AND LOGIC APPLICATIONS
48
Patent #:
Issue Dt:
06/22/2004
Application #:
10140340
Filing Dt:
05/06/2002
Title:
SEMICONDUCTOR COMPONENT WITH ADJUSTMENT CIRCUITRY AND METHOD OF FABRICATION
49
Patent #:
Issue Dt:
03/03/2009
Application #:
10140347
Filing Dt:
05/06/2002
Publication #:
Pub Dt:
11/06/2003
Title:
WEB DISPATCH SERVICE
50
Patent #:
Issue Dt:
09/21/2004
Application #:
10140411
Filing Dt:
05/06/2002
Publication #:
Pub Dt:
11/06/2003
Title:
LOW POWER CONSUMPTION MEMORY DEVICE HAVING ROW-TO-COLUMN SHORT
51
Patent #:
Issue Dt:
06/10/2003
Application #:
10140580
Filing Dt:
05/07/2002
Title:
SEMICONDUCTOR PROCESSING METHODS
52
Patent #:
Issue Dt:
01/27/2004
Application #:
10141447
Filing Dt:
05/08/2002
Publication #:
Pub Dt:
11/13/2003
Title:
STACKED DIE MODULE AND TECHNIQUES FOR FORMING A STACKED DIE MODULE
53
Patent #:
Issue Dt:
12/23/2003
Application #:
10141837
Filing Dt:
05/10/2002
Publication #:
Pub Dt:
11/13/2003
Title:
METHOD AND APPARATUS FOR DISCHARGING AN ARRAY WELL IN A FLASH MEMORY DEVICE
54
Patent #:
Issue Dt:
06/07/2005
Application #:
10142329
Filing Dt:
05/09/2002
Title:
PHASE-CONTROLLED FIBER BRAGG GRATINGS AND MANUFACTURING METHODS
55
Patent #:
Issue Dt:
09/12/2006
Application #:
10143093
Filing Dt:
05/13/2002
Publication #:
Pub Dt:
11/13/2003
Title:
INTEGRATED CMOS IMAGER AND MICROCONTROLLER
56
Patent #:
Issue Dt:
03/06/2007
Application #:
10143578
Filing Dt:
05/13/2002
Publication #:
Pub Dt:
11/13/2003
Title:
DATA DOWNLOAD TO IMAGER CHIP USING IMAGE SENSOR AS A RECEPTOR
57
Patent #:
Issue Dt:
12/12/2006
Application #:
10143896
Filing Dt:
05/14/2002
Publication #:
Pub Dt:
11/20/2003
Title:
OUT OF ORDER DRAM SEQUENCER
58
Patent #:
Issue Dt:
04/26/2005
Application #:
10145562
Filing Dt:
05/14/2002
Publication #:
Pub Dt:
09/19/2002
Title:
METHODS OF FORMING MATERIALS WITHIN OPENINGS, AND METHODS OF FORMING ISOLATION REGIONS
59
Patent #:
Issue Dt:
04/13/2004
Application #:
10145986
Filing Dt:
05/15/2002
Publication #:
Pub Dt:
11/20/2003
Title:
METHODS EMPLOYING ELEVATED TEMPERATURES TO ENHANCE QUALITY CONTROL IN MICROELECTRONIC COMPONENT MANUFACTURE
60
Patent #:
Issue Dt:
05/18/2004
Application #:
10146112
Filing Dt:
05/16/2002
Publication #:
Pub Dt:
09/25/2003
Title:
LOW VOLTAGE CURRENT REFERENCE
61
Patent #:
Issue Dt:
04/06/2004
Application #:
10146890
Filing Dt:
05/17/2002
Publication #:
Pub Dt:
11/20/2003
Title:
METHOD FOR FORMING MRAM BIT HAVING A BOTTOM SENSE LAYER UTILIZING ELECTROLESS PLATING
62
Patent #:
Issue Dt:
01/15/2008
Application #:
10147146
Filing Dt:
05/16/2002
Publication #:
Pub Dt:
11/20/2003
Title:
DELAY LOCKED LOOP WITH FREQUENCY CONTROL
63
Patent #:
Issue Dt:
05/13/2003
Application #:
10147176
Filing Dt:
05/16/2002
Publication #:
Pub Dt:
09/12/2002
Title:
HEAT SINK CHIP PACKAGE
64
Patent #:
Issue Dt:
10/05/2004
Application #:
10147657
Filing Dt:
05/16/2002
Publication #:
Pub Dt:
11/20/2003
Title:
MEASURE-CONTROLLED CIRCUIT WITH FREQUENCY CONTROL
65
Patent #:
Issue Dt:
05/24/2005
Application #:
10150144
Filing Dt:
05/17/2002
Title:
METHOD AND SYSTEM FOR FABRICATING SEMICONDUCTOR COMPONENTS USING WAFER LEVEL CONTACT PRINTING
66
Patent #:
Issue Dt:
09/14/2004
Application #:
10150622
Filing Dt:
05/17/2002
Publication #:
Pub Dt:
11/20/2003
Title:
DOUBLE-SIDED CAPACITOR STRUCTURE FOR A SEMICONDUCTOR DEVICE AND A METHOD FOR FORMING THE STRUCTURE
67
Patent #:
Issue Dt:
01/26/2010
Application #:
10150623
Filing Dt:
05/17/2002
Publication #:
Pub Dt:
11/20/2003
Title:
METHODS OF FORMING PROGRAMMABLE MEMORY DEVICES
68
Patent #:
Issue Dt:
01/09/2007
Application #:
10150653
Filing Dt:
05/17/2002
Publication #:
Pub Dt:
09/04/2003
Title:
FLIP CHIP PACKAGING USING RECESSED INTERPOSER TERMINALS
69
Patent #:
Issue Dt:
12/05/2006
Application #:
10150893
Filing Dt:
05/17/2002
Publication #:
Pub Dt:
09/04/2003
Title:
INTERPOSER CONFIGURED TO REDUCE THE PROFILES OF SEMICONDUCTOR DEVICE ASSEMBLIES AND PACKAGES INCLUDING THE SAME AND METHODS
70
Patent #:
Issue Dt:
03/25/2008
Application #:
10150901
Filing Dt:
05/17/2002
Publication #:
Pub Dt:
09/04/2003
Title:
METHODS FOR ASSEMBLY AND PACKAGING OF FLIP CHIP CONFIGURED DICE WITH INTERPOSER
71
Patent #:
Issue Dt:
12/13/2005
Application #:
10150902
Filing Dt:
05/17/2002
Publication #:
Pub Dt:
09/04/2003
Title:
METHOD AND APPARATUS FOR DIELECTRIC FILLING OF FLIP CHIP ON INTERPOSER ASSEMBLY
72
Patent #:
Issue Dt:
10/28/2003
Application #:
10152649
Filing Dt:
05/20/2002
Publication #:
Pub Dt:
09/26/2002
Title:
FLASH MEMORY WITH ULTRA THIN VERTICAL BODY TRANSISTORS
73
Patent #:
Issue Dt:
09/23/2003
Application #:
10152842
Filing Dt:
05/23/2002
Publication #:
Pub Dt:
09/12/2002
Title:
TRENCH DRAM CELL WITH VERTICAL DEVICE AND BURIED WORD LINES
74
Patent #:
Issue Dt:
04/15/2003
Application #:
10153830
Filing Dt:
05/21/2002
Title:
SEMICONDUCTOR PROCESSING METHODS OF FORMING CONTACT OPENINGS, METHODS OF FORMING MEMORY CIRCUITRY, METHODS OF FORMING ELECTRICAL CONNECTIONS, AND METHODS OF FORMING DYNAMIC RANDOM ACCESS MEMORY (DRAM) CIRCUITRY
75
Patent #:
Issue Dt:
07/22/2003
Application #:
10154019
Filing Dt:
05/23/2002
Publication #:
Pub Dt:
01/02/2003
Title:
CHARGING A CAPACITANCE OF A MEMORY CELL AND CHARGER
76
Patent #:
Issue Dt:
12/28/2004
Application #:
10154640
Filing Dt:
05/24/2002
Publication #:
Pub Dt:
11/27/2003
Title:
METHODS FOR MOLDING A SEMICONDUCTOR DIE PACKAGE WITH ENHANCED THERMAL CONDUCTIVITY
77
Patent #:
Issue Dt:
05/20/2003
Application #:
10155132
Filing Dt:
05/23/2002
Publication #:
Pub Dt:
10/03/2002
Title:
BI-LEVEL DIGIT LINE ARCHITECTURE FOR HIGH DENSITY DRAMS
78
Patent #:
Issue Dt:
07/22/2003
Application #:
10155317
Filing Dt:
05/23/2002
Publication #:
Pub Dt:
09/26/2002
Title:
CONCAVE FACE WIRE BOND CAPILLARY AND METHOD
79
Patent #:
Issue Dt:
01/03/2006
Application #:
10155668
Filing Dt:
05/24/2002
Publication #:
Pub Dt:
11/27/2003
Title:
MEMORY DEVICE SEQUENCER AND METHOD SUPPORTING MULTIPLE MEMORY DEVICE CLOCK SPEEDS
80
Patent #:
Issue Dt:
09/07/2004
Application #:
10156097
Filing Dt:
05/29/2002
Publication #:
Pub Dt:
12/18/2003
Title:
HIGH ASPECT RATIO FILL METHOD AND RESULTING STRUCTURE
81
Patent #:
Issue Dt:
07/31/2007
Application #:
10156420
Filing Dt:
05/28/2002
Publication #:
Pub Dt:
12/04/2003
Title:
APPARATUS AND METHODS HAVING A COMMAND SEQUENCE
82
Patent #:
Issue Dt:
04/06/2004
Application #:
10157049
Filing Dt:
05/29/2002
Publication #:
Pub Dt:
12/04/2003
Title:
METHOD OF FORMING BIASABLE ISOLATION REGIONS USING EPITAXIALLY GROWN SILICON BETWEEN THE ISOLATION REGIONS
83
Patent #:
Issue Dt:
03/30/2004
Application #:
10158424
Filing Dt:
05/29/2002
Publication #:
Pub Dt:
10/03/2002
Title:
PROCESS FOR INTEGRATING IN A SAME CHIP A NON-VOLATILE MEMORY AND A HIGH-PERFORMANCE LOGIC CIRCUITRY
84
Patent #:
Issue Dt:
04/22/2003
Application #:
10158553
Filing Dt:
05/30/2002
Publication #:
Pub Dt:
12/26/2002
Title:
COLUMN MULTIPLEXER FOR SEMICONDUCTOR MEMORIES
85
Patent #:
Issue Dt:
07/15/2003
Application #:
10158554
Filing Dt:
05/30/2002
Publication #:
Pub Dt:
12/26/2002
Title:
SEMICONDUCTOR MEMORY SYSTEM
86
Patent #:
Issue Dt:
06/15/2004
Application #:
10159085
Filing Dt:
05/29/2002
Publication #:
Pub Dt:
12/04/2003
Title:
INTEGRATED CIRCUIT RESET CIRCUITRY
87
Patent #:
Issue Dt:
03/21/2006
Application #:
10159782
Filing Dt:
05/30/2002
Publication #:
Pub Dt:
01/23/2003
Title:
METHOD FOR ERROR CONTROL IN MULTILEVEL CELLS WITH CONFIGURABLE NUMBER OF STORED BITS
88
Patent #:
Issue Dt:
09/21/2004
Application #:
10159885
Filing Dt:
05/29/2002
Publication #:
Pub Dt:
12/04/2003
Title:
METHOD AND APPARATUS FOR ERASING FLASH MEMORY
89
Patent #:
Issue Dt:
09/16/2003
Application #:
10160063
Filing Dt:
06/04/2002
Title:
METHOD AND APPARATUS FOR PROGRAMMING ROW REDUNDANCY FUSES SO DECODING MATCHES INTERNAL PATTERN OF A MEMORY ARRAY
90
Patent #:
Issue Dt:
06/01/2010
Application #:
10160641
Filing Dt:
05/31/2002
Publication #:
Pub Dt:
12/04/2003
Title:
FORMING FERROELECTRIC POLYMER MEMORIES
91
Patent #:
Issue Dt:
05/16/2006
Application #:
10160698
Filing Dt:
05/30/2002
Publication #:
Pub Dt:
10/17/2002
Title:
SEMICONDUCTOR PROCESSING METHODS OF TRANSFERRING PATTERNS FROM PATTERNED PHOTORESISTS TO MATERIALS, AND STRUCTURES COMPRISING SILICON NITRIDE
92
Patent #:
Issue Dt:
07/18/2006
Application #:
10160705
Filing Dt:
05/30/2002
Publication #:
Pub Dt:
10/17/2002
Title:
SEMICONDUCTOR PROCESSING METHODS OF TRANSFERRING PATTERNS FROM PATTERNED PHOTORESISTS TO MATERIALS, AND STRUCTURES COMPRISING SILICON NITRIDE
93
Patent #:
Issue Dt:
09/07/2004
Application #:
10161053
Filing Dt:
05/30/2002
Publication #:
Pub Dt:
03/13/2003
Title:
OUTPUT BUFFER FOR A NONVOLATILE MEMORY WITH OUTPUT SIGNAL SWITCHING NOISE REDUCTION, AND NONVOLATILE MEMORY COMPRISING THE SAME
94
Patent #:
Issue Dt:
12/07/2004
Application #:
10161055
Filing Dt:
05/30/2002
Publication #:
Pub Dt:
03/27/2003
Title:
OUTPUT BUFFER FOR A NONVOLATILE MEMORY WITH OPTIMIZED SLEW-RATE CONTROL
95
Patent #:
Issue Dt:
10/14/2008
Application #:
10161134
Filing Dt:
05/30/2002
Publication #:
Pub Dt:
10/17/2002
Title:
SEMICONDUCTOR PROCESSING METHODS OF TRANSFERRING PATTERNS FROM PATTERNED PHOTORESISTS TO MATERIALS, AND STRUCTURES COMPRISING SILICON NITRIDE
96
Patent #:
Issue Dt:
02/22/2005
Application #:
10161136
Filing Dt:
05/30/2002
Publication #:
Pub Dt:
10/10/2002
Title:
SEMICONDUCTOR PROCESSING METHODS OF TRANSFERRING PATTERNS FROM PATTERNED PHOTORESISTS TO MATERIALS, AND STRUCTURES COMPRISING SILICON NITRIDE
97
Patent #:
Issue Dt:
03/13/2007
Application #:
10161439
Filing Dt:
06/04/2002
Publication #:
Pub Dt:
12/04/2003
Title:
METHOD FOR STATISTICAL ANALYSIS OF IMAGES FOR AUTOMATIC WHITE BALANCE OF COLOR CHANNEL GAINS FOR IMAGE SENSORS
98
Patent #:
Issue Dt:
05/04/2004
Application #:
10161501
Filing Dt:
05/31/2002
Publication #:
Pub Dt:
12/04/2003
Title:
REDUNDANCY CIRCUIT AND METHOD FOR SEMICONDUCTOR MEMORY DEVICES
99
Patent #:
Issue Dt:
03/13/2007
Application #:
10161615
Filing Dt:
06/05/2002
Publication #:
Pub Dt:
12/11/2003
Title:
METHOD OF FORMING FULLY-DEPLETED (FD) (SOI) MOSFET ACCESS TRANSISTOR
100
Patent #:
Issue Dt:
12/31/2002
Application #:
10161839
Filing Dt:
06/03/2002
Title:
STACKABLE SEMICONDUCTOR PACKAGE HAVING CONDUCTIVE LAYER AND INSULATING LAYERS AND METHOD OF FABRICATION
Assignors
1
Exec Dt:
07/03/2018
2
Exec Dt:
07/03/2018
Assignee
1
10 S. DEARBORN
7TH FLOOR
CHICAGO, ILLINOIS 60603
Correspondence name and address
MARCELA ROBLEDO
2475 HANOVER STREET
PALO ALTO, CA 94304

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