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09/18/2003
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Title:
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METHODS FOR FORMING A SLOT WITH A LATERALLY RECESSED AREA AT AN END THEREOF THROUGH AN INTERPOSER OR OTHER CARRIER SUBSTRATE
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Patent #:
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Issue Dt:
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09/06/2005
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Application #:
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10435569
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Filing Dt:
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05/08/2003
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Publication #:
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Pub Dt:
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11/11/2004
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Title:
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REMOVAL OF CARBON FROM AN INSULATIVE LAYER USING OZONE
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Patent #:
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Issue Dt:
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11/30/2004
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Application #:
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10435590
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Filing Dt:
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05/12/2003
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Publication #:
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Pub Dt:
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11/20/2003
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Title:
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SEMICONDUCTOR MEMORY HAVING MULTIPLE REDUNDANT COLUMNS WITH OFFSET SEGMENTATION BOUNDARIES
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Patent #:
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Issue Dt:
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06/13/2006
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Application #:
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10435791
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Filing Dt:
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05/12/2003
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Publication #:
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Pub Dt:
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11/18/2004
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Title:
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METHODS OF FORMING INTERMEDIATE SEMICONDUCTOR DEVICE STRUCTURES USING SPIN-ON, PHOTOPATTERNABLE, INTERLAYER DIELECTRIC MATERIALS
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Patent #:
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Issue Dt:
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09/25/2007
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Application #:
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10436640
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Filing Dt:
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05/13/2003
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Publication #:
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Pub Dt:
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10/30/2003
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Title:
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METHODS FOR FORMING PHOSPHORUS- AND/OR BORON-CONTAINING SILICA LAYERS ON SUBSTRATES
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Patent #:
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Issue Dt:
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10/14/2008
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Application #:
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10436775
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Filing Dt:
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05/13/2003
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Publication #:
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Pub Dt:
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12/02/2004
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Title:
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TEST SCAN CELLS
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Patent #:
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Issue Dt:
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08/09/2005
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Application #:
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10437214
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Filing Dt:
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05/13/2003
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Publication #:
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Pub Dt:
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10/30/2003
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Title:
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PROCESS FOR FABRICATING EXTERNAL CONTACTS ON SEMICONDUCTOR COMPONENTS
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Patent #:
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Issue Dt:
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08/11/2009
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Application #:
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10438146
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Filing Dt:
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05/13/2003
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Publication #:
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Pub Dt:
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10/30/2003
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Title:
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REDUCED AREA INTERSECTION BETWEEN ELECTRODE AND PROGRAMMING ELEMENT
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Patent #:
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Issue Dt:
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07/19/2005
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Application #:
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10438175
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Filing Dt:
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05/13/2003
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Publication #:
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Pub Dt:
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02/26/2004
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Title:
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PROGRAMMING METHOD OF THE MEMORY CELLS IN A MULTILEVEL NON-VOLATILE MEMORY DEVICE
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Patent #:
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Issue Dt:
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04/05/2005
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Application #:
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10438360
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Filing Dt:
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05/14/2003
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Publication #:
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Pub Dt:
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10/23/2003
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Title:
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ETCH STOP LAYER IN POLY-METAL STRUCTURES
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Patent #:
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Issue Dt:
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10/19/2004
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Application #:
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10438733
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Filing Dt:
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05/15/2003
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Publication #:
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Pub Dt:
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01/29/2004
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Title:
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PAGE-ERASABLE FLASH MEMORY
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Patent #:
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Issue Dt:
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05/11/2004
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Application #:
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10439729
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Filing Dt:
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05/16/2003
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Publication #:
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Pub Dt:
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10/23/2003
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Title:
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6F2 DRAM ARRAY WITH APPARATUS FOR STRESS TESTING AN ISOLATION GATE AND METHOD
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Patent #:
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Issue Dt:
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09/13/2005
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Application #:
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10440043
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Filing Dt:
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05/15/2003
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Publication #:
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Pub Dt:
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01/15/2004
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Title:
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SELF-REPAIR METHOD FOR NONVOLATILE MEMORY DEVICES WITH ERASING/PROGRAMMING FAILURE, AND RELATIVE NONVOLATILE MEMORY DEVICE
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Patent #:
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Issue Dt:
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06/05/2007
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Application #:
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10440590
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Filing Dt:
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05/19/2003
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Publication #:
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Pub Dt:
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12/18/2003
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Title:
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SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICE COMPONENTS WITH PERIPHERALLY LOCATED, CASTELLATED CONTACTS, ASSEMBLIES AND PACKAGES INCLUDING SUCH SEMICONDUCTOR DEVICES OR PACKAGES AND ASSOCIATED METHODS
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Patent #:
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Issue Dt:
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02/01/2005
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Application #:
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10441380
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Filing Dt:
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05/20/2003
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Publication #:
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Pub Dt:
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10/30/2003
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Title:
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METHODS FOR FABRICATION AN IMPROVED FLOATING GATE MEMORY CELL
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Patent #:
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Issue Dt:
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02/17/2004
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Application #:
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10441870
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Filing Dt:
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05/19/2003
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Publication #:
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Pub Dt:
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10/23/2003
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Title:
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METHODS OF PATTERNING RADIATION, METHODS OF FORMING RADIATION-PATTERNING TOOLS, AND RADIATION-PATTERNING TOOLS
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Patent #:
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Issue Dt:
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08/15/2006
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Application #:
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10442509
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Filing Dt:
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05/20/2003
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Publication #:
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Pub Dt:
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11/25/2004
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Title:
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DRAM CELLS AND ELECTRONIC SYSTEMS
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Patent #:
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Issue Dt:
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12/01/2009
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Application #:
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10442667
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Filing Dt:
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05/20/2003
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Publication #:
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Pub Dt:
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03/18/2004
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Title:
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PROCESSING ELEMENT AND METHOD CONNECTING REGISTERS TO PROCESSING LOGIC IN A PLURALITY OF CONFIGURATIONS
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Patent #:
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Issue Dt:
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02/13/2007
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Application #:
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10442789
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Filing Dt:
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05/21/2003
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Publication #:
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Pub Dt:
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11/25/2004
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Title:
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CONTROLLING MULTIPLE SIGNAL POLARITY IN A SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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08/24/2004
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Application #:
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10442844
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Filing Dt:
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05/20/2003
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Publication #:
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Pub Dt:
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11/13/2003
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Title:
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INTEGRATED VOLATILE AND NON-VOLATILE MEMORY
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Patent #:
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Issue Dt:
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11/29/2005
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Application #:
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10443021
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Filing Dt:
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05/22/2003
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Publication #:
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Pub Dt:
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11/25/2004
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Title:
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ATOMIC LAYER DEPOSITION (ALD) HIGH PERMEABILITY LAYERED MAGNETIC FILMS TO REDUCE NOISE IN HIGH SPEED INTERCONNECTION
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Patent #:
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Issue Dt:
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06/08/2004
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Application #:
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10443023
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Filing Dt:
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05/22/2003
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Publication #:
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Pub Dt:
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10/30/2003
| | | | |
Title:
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PD-SOI SUBSTRATE WITH SUPPRESSED FLOATING BODY EFFECT AND METHOD FOR ITS FABRICATION
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Patent #:
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Issue Dt:
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01/25/2005
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Application #:
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10443043
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Filing Dt:
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05/22/2003
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Publication #:
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Pub Dt:
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10/23/2003
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Title:
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FREQUENCY SENSING VOLTAGE REGULATOR
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Patent #:
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Issue Dt:
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02/16/2010
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Application #:
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10443337
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Filing Dt:
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05/21/2003
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Publication #:
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Pub Dt:
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11/25/2004
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Title:
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GETTERING OF SILICON ON INSULATOR USING RELAXED SILICON GERMANIUM EPITAXIAL PROXIMITY LAYERS
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Patent #:
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Issue Dt:
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09/25/2007
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Application #:
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10443340
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Filing Dt:
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05/21/2003
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Publication #:
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Pub Dt:
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11/25/2004
| | | | |
Title:
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ULTRA-THIN SEMICONDUCTORS BONDED ON GLASS SUBSTRATES
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Patent #:
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Issue Dt:
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04/12/2005
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Application #:
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10443490
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Filing Dt:
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05/22/2003
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Publication #:
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Pub Dt:
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11/13/2003
| | | | |
Title:
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DIELECTRIC CURE FOR REDUCING OXYGEN VACANCIES
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Patent #:
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Issue Dt:
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03/22/2005
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Application #:
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10445940
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Filing Dt:
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05/28/2003
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Publication #:
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Pub Dt:
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12/02/2004
| | | | |
Title:
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INTEGRATED CHARGE SENSING SCHEME FOR RESISTIVE MEMORIES
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Patent #:
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Issue Dt:
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01/30/2007
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Application #:
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10446384
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Filing Dt:
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05/27/2003
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Publication #:
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Pub Dt:
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10/30/2003
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Title:
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COLLAR POSITIONABLE ABOUT A PERIPHERY OF A CONTACT PAD AND AROUND A CONDUCTIVE STRUCTURE SECURED TO THE CONTACT PADS, SEMICONDUCTOR DEVICE COMPONENTS INCLUDING SAME, AND METHODS FOR FABRICATING SAME
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Patent #:
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Issue Dt:
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08/31/2004
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Application #:
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10447293
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Filing Dt:
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05/28/2003
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Publication #:
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Pub Dt:
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04/15/2004
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Title:
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TESTING METHOD AND DEVICE FOR NON-VOLATILE MEMORIES HAVING A LPC (LOW PIN COUNT) COMMUNICATION SERIAL INTERFACE
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Patent #:
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Issue Dt:
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07/19/2005
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Application #:
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10447808
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Filing Dt:
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05/29/2003
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Publication #:
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Pub Dt:
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12/04/2003
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Title:
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BIASABLE ISOLATION REGIONS USING EPITAXIALLY GROWN SILICON BETWEEN THE ISOLATION REGIONS
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Patent #:
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Issue Dt:
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09/05/2006
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Application #:
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10448687
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Filing Dt:
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05/30/2003
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Publication #:
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Pub Dt:
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12/02/2004
| | | | |
Title:
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METHODS FOR EPITAXIAL SILICON GROWTH
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Patent #:
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Issue Dt:
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11/28/2006
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Application #:
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10448696
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Filing Dt:
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05/29/2003
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Publication #:
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Pub Dt:
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12/02/2004
| | | | |
Title:
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DYNAMIC BIOS EXECUTION AND CONCURRENT UPDATE FOR A BLADE SERVER
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Patent #:
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Issue Dt:
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04/20/2004
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Application #:
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10449217
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Filing Dt:
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05/29/2003
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Publication #:
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Pub Dt:
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12/25/2003
| | | | |
Title:
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ANTIFUSE CIRCUIT WITH IMPROVED GATE OXIDE RELIABILITY
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Patent #:
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Issue Dt:
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11/29/2005
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Application #:
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10450238
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Filing Dt:
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06/10/2003
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Publication #:
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Pub Dt:
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02/05/2004
| | | | |
Title:
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SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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01/11/2005
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Application #:
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10453321
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Filing Dt:
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06/03/2003
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Publication #:
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Pub Dt:
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12/09/2004
| | | | |
Title:
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PERMANENT MASTER BLOCK LOCK IN A MEMORY DEVICE
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Patent #:
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Issue Dt:
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06/14/2005
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Application #:
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10454254
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Filing Dt:
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06/03/2003
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Publication #:
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Pub Dt:
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02/19/2004
| | | | |
Title:
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SELECTIVE PASSIVATION OF EXPOSED SILICON
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Patent #:
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Issue Dt:
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03/13/2007
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Application #:
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10454256
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Filing Dt:
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06/03/2003
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Publication #:
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Pub Dt:
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02/19/2004
| | | | |
Title:
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SEMICONDUCTOR DEVICES WITH OXIDE COATINGS SELECTIVELY POSITIONED OVER EXPOSED FEATURES INCLUDING SEMICONDUCTOR MATERIAL
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Patent #:
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Issue Dt:
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12/07/2004
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Application #:
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10454303
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Filing Dt:
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06/03/2003
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Publication #:
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Pub Dt:
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12/09/2004
| | | | |
Title:
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METHODS OF FORMING OPENINGS EXTENDING THROUGH ELECTRICALLY INSULATIVE MATERIAL TO ELECTRICALLY CONDUCTIVE MATERIAL
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Patent #:
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Issue Dt:
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12/06/2005
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Application #:
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10454407
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Filing Dt:
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06/03/2003
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Title:
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CARD IDENTIFICATION COMPATIBILITY
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Patent #:
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Issue Dt:
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09/14/2004
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Application #:
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10455975
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Filing Dt:
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06/06/2003
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Publication #:
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Pub Dt:
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11/20/2003
| | | | |
Title:
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SELF-ALIGNED DUAL-GATE TRANSISTOR DEVICE AND METHOD OF FORMING SELF-ALIGNED DUAL-GATE TRANSISTOR DEVICE
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Patent #:
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Issue Dt:
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06/12/2007
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Application #:
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10456185
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Filing Dt:
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06/06/2003
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Publication #:
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Pub Dt:
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02/10/2005
| | | | |
Title:
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FUTURE ACTIVITY LIST FOR PERIPHERAL BUS HOST CONTROLLER
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Patent #:
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Issue Dt:
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09/13/2005
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Application #:
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10456274
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Filing Dt:
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06/06/2003
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Publication #:
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Pub Dt:
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11/06/2003
| | | | |
Title:
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METHOD FOR ATTACHING SEMICONDUCTOR COMPONENTS TO A SUBSTRATE USING COMPONENT ATTACH SYSTEM HAVING RADIATION EXPOSURE ASSEMBLY
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|