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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:047540/0001   Pages: 843
Recorded: 07/13/2018
Attorney Dkt #:509265/2155
Conveyance: SECURITY INTEREST (SEE DOCUMENT FOR DETAILS).
1
Patent #:
Issue Dt:
09/02/2008
Application #:
11319798
Filing Dt:
12/27/2005
Publication #:
Pub Dt:
08/17/2006
Title:
METHOD FOR MANUFACTURING NON-VOLATILE MEMORY DEVICES INTEGRATED IN A SEMICONDUCTOR SUBSTRATE
2
Patent #:
Issue Dt:
05/06/2014
Application #:
11320376
Filing Dt:
12/28/2005
Publication #:
Pub Dt:
06/28/2007
Title:
DRAM cell design with folded digitline sense amplifier
3
Patent #:
Issue Dt:
04/24/2007
Application #:
11321012
Filing Dt:
12/28/2005
Publication #:
Pub Dt:
06/08/2006
Title:
APPARATUS AND METHOD FOR ADAPTING A LEVEL SENSITIVE DEVICE TO PRODUCE EDGE-TRIGGERED BEHAVIOR
4
Patent #:
Issue Dt:
02/07/2012
Application #:
11321437
Filing Dt:
12/29/2005
Publication #:
Pub Dt:
05/25/2006
Title:
METHOD OF INCREASING DEPOSITION RATE OF SILICON DIOXIDE ON A CATALYST
5
Patent #:
Issue Dt:
07/07/2009
Application #:
11321511
Filing Dt:
12/29/2005
Publication #:
Pub Dt:
05/18/2006
Title:
LOW TEMPERATURE PROCESS FOR POLYSILAZANE OXIDATION/DENSIFICATION
6
Patent #:
Issue Dt:
08/05/2008
Application #:
11323451
Filing Dt:
12/30/2005
Publication #:
Pub Dt:
05/25/2006
Title:
REDUCING DELAYS IN WORD LINE SELECTION
7
Patent #:
Issue Dt:
11/16/2010
Application #:
11323757
Filing Dt:
12/30/2005
Publication #:
Pub Dt:
07/05/2007
Title:
CONNECTION VERIFICATION TECHNIQUE
8
Patent #:
Issue Dt:
03/04/2008
Application #:
11323958
Filing Dt:
12/30/2005
Publication #:
Pub Dt:
05/18/2006
Title:
STRAPPING WORD LINES OF NAND MEMORY DEVICES
9
Patent #:
Issue Dt:
03/18/2008
Application #:
11324735
Filing Dt:
12/29/2005
Publication #:
Pub Dt:
06/29/2006
Title:
SEMICONDUCTOR DEVICE COMPRISING A CRYSTALLINE LAYER CONTAINING SILICON/GERMANIUM, AND COMPRISING A SILICON ENRICHED FLOATING CHARGE TRAPPING MEDIA OVER THE CRYSTALLINE LAYER
10
Patent #:
Issue Dt:
05/13/2008
Application #:
11324774
Filing Dt:
01/03/2006
Publication #:
Pub Dt:
08/03/2006
Title:
HIGH SPEED LOW VOLTAGE DRIVER
11
Patent #:
Issue Dt:
09/11/2007
Application #:
11325155
Filing Dt:
01/04/2006
Publication #:
Pub Dt:
05/25/2006
Title:
MRAM LAYER HAVING DOMAIN WALL TRAPS
12
Patent #:
Issue Dt:
06/26/2007
Application #:
11326642
Filing Dt:
01/06/2006
Publication #:
Pub Dt:
06/08/2006
Title:
METHODS OF FORMING SEMICONDUCTOR CONSTRUCTIONS
13
Patent #:
Issue Dt:
05/08/2007
Application #:
11326643
Filing Dt:
01/06/2006
Publication #:
Pub Dt:
06/08/2006
Title:
METHODS OF FORMING SEMICONDUCTOR CONSTRUCTIONS
14
Patent #:
Issue Dt:
08/07/2007
Application #:
11326739
Filing Dt:
01/05/2006
Publication #:
Pub Dt:
06/08/2006
Title:
DEPOSITION METHODS
15
Patent #:
Issue Dt:
05/08/2007
Application #:
11327454
Filing Dt:
01/09/2006
Publication #:
Pub Dt:
06/01/2006
Title:
PARALLEL CACHELETS
16
Patent #:
Issue Dt:
10/09/2007
Application #:
11327794
Filing Dt:
01/06/2006
Publication #:
Pub Dt:
06/01/2006
Title:
MICROFEATURE WORKPIECE PROCESSING APPARATUS AND METHODS FOR CONTROLLING DEPOSITION OF MATERIALS ON MICROFEATURE WORKPIECES
17
Patent #:
Issue Dt:
07/14/2009
Application #:
11328150
Filing Dt:
01/10/2006
Publication #:
Pub Dt:
06/15/2006
Title:
DRAM LAYOUT WITH VERTICAL FETS AND METHOD OF FORMATION
18
Patent #:
Issue Dt:
10/09/2007
Application #:
11328158
Filing Dt:
01/10/2006
Publication #:
Pub Dt:
07/13/2006
Title:
APPARATUS AND METHOD FOR MANUFACTURING TILTED MICROLENSES
19
Patent #:
Issue Dt:
08/19/2008
Application #:
11328225
Filing Dt:
01/10/2006
Publication #:
Pub Dt:
07/13/2006
Title:
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING GATE ELECTRODES OF POLYMETAL GATE AND DUAL-GATE STRUCTURE
20
Patent #:
Issue Dt:
07/29/2008
Application #:
11328694
Filing Dt:
01/04/2006
Publication #:
Pub Dt:
07/05/2007
Title:
SEMICONDUCTOR TEMPERATURE SENSOR WITH HIGH SENSITIVITY
21
Patent #:
Issue Dt:
03/06/2007
Application #:
11328865
Filing Dt:
01/09/2006
Publication #:
Pub Dt:
05/25/2006
Title:
LOW TEMPERATURE NITRIDE USED AS CU BARRIER LAYER
22
Patent #:
Issue Dt:
07/05/2011
Application #:
11329025
Filing Dt:
01/10/2006
Publication #:
Pub Dt:
07/12/2007
Title:
GALLIUM LANTHANIDE OXIDE FILMS
23
Patent #:
Issue Dt:
05/26/2009
Application #:
11329755
Filing Dt:
01/11/2006
Publication #:
Pub Dt:
07/12/2007
Title:
PHOTOLITHOGRAPHIC SYSTEMS AND METHODS FOR PRODUCING SUB-DIFFRACTION-LIMITED FEATURES
24
Patent #:
Issue Dt:
10/21/2008
Application #:
11330791
Filing Dt:
01/12/2006
Publication #:
Pub Dt:
07/13/2006
Title:
DVI LINK WITH PARALLEL TEST DATA
25
Patent #:
Issue Dt:
10/26/2010
Application #:
11330987
Filing Dt:
01/12/2006
Publication #:
Pub Dt:
07/12/2007
Title:
SEMICONDUCTOR TEMPERATURE SENSOR USING BANDGAP GENERATOR CIRCUIT
26
Patent #:
Issue Dt:
12/01/2009
Application #:
11331121
Filing Dt:
01/13/2006
Publication #:
Pub Dt:
07/19/2007
Title:
METHOD AND APPARATUS PROVIDING PIXEL STORAGE GATE CHARGE SENSING FOR ELECTRONIC STABILIZATION IN IMAGERS
27
Patent #:
Issue Dt:
12/11/2007
Application #:
11331890
Filing Dt:
01/12/2006
Publication #:
Pub Dt:
06/01/2006
Title:
STATIC CONTENT ADDRESSABLE MEMORY CELL
28
Patent #:
Issue Dt:
12/28/2010
Application #:
11331951
Filing Dt:
01/13/2006
Publication #:
Pub Dt:
07/19/2007
Title:
ADDITIONAL METAL ROUTING IN SEMICONDUCTOR DEVICES
29
Patent #:
Issue Dt:
03/24/2009
Application #:
11332510
Filing Dt:
01/17/2006
Publication #:
Pub Dt:
08/10/2006
Title:
CMOS IMAGER HAVING ON-CHIP ROM
30
Patent #:
Issue Dt:
10/09/2007
Application #:
11332991
Filing Dt:
01/17/2006
Publication #:
Pub Dt:
07/19/2007
Title:
SEMICONDUCTOR CONSTRUCTIONS AND LIGHT-DIRECTING CONDUITS
31
Patent #:
Issue Dt:
03/04/2008
Application #:
11333678
Filing Dt:
01/17/2006
Publication #:
Pub Dt:
06/01/2006
Title:
PARTIAL EDGE BEAD REMOVAL TO ALLOW IMPROVED GROUNDING DURING E-BEAM MASK WRITING
32
Patent #:
Issue Dt:
10/30/2007
Application #:
11334205
Filing Dt:
01/18/2006
Publication #:
Pub Dt:
08/03/2006
Title:
CONTROL OF VOLTAGES DURING ERASE AND RE-PROGRAM OPERATIONS OF MEMORY CELLS
33
Patent #:
Issue Dt:
02/13/2007
Application #:
11334338
Filing Dt:
01/17/2006
Publication #:
Pub Dt:
06/01/2006
Title:
LOW POWER PROGRAMMING TECHNIQUE FOR A FLOATING BODY MEMORY TRANSISTOR, MEMORY CELL, AND MEMORY ARRAY
34
Patent #:
Issue Dt:
04/06/2010
Application #:
11334504
Filing Dt:
01/19/2006
Publication #:
Pub Dt:
07/19/2007
Title:
ELECTRICALLY REWRITABLE NON-VOLATILE MEMORY ELEMENT AND METHOD OF MANUFACTURING THE SAME
35
Patent #:
Issue Dt:
06/09/2009
Application #:
11334626
Filing Dt:
01/19/2006
Publication #:
Pub Dt:
07/19/2007
Title:
LINEAR DISTRIBUTED PIXEL DIFFERENTIAL AMPLIFIER HAVING MIRRORED INPUTS
36
Patent #:
Issue Dt:
06/25/2013
Application #:
11335251
Filing Dt:
01/18/2006
Publication #:
Pub Dt:
07/19/2007
Title:
IMMERSION PHOTOLITHOGRAPHY SCANNER
37
Patent #:
Issue Dt:
04/21/2009
Application #:
11336228
Filing Dt:
01/20/2006
Publication #:
Pub Dt:
06/01/2006
Title:
METHODS OF FABRICATING A MICROLENS INCLUDING SELECTIVELY CURING FLOWABLE, UNCURED OPTICALLY TRASMISSIVE MATERIAL
38
Patent #:
Issue Dt:
09/25/2007
Application #:
11336229
Filing Dt:
01/20/2006
Publication #:
Pub Dt:
06/01/2006
Title:
MASK HAVING TRANSMISSIVE ELEMENTS AND A COMMON SIDELOBE INHIBITOR FOR SIDELOBE SUPPRESSION IN RADIATED PATTERNING
39
Patent #:
Issue Dt:
10/23/2007
Application #:
11336463
Filing Dt:
01/20/2006
Publication #:
Pub Dt:
06/15/2006
Title:
CMOS INVERTER CONSTRUCTIONS
40
Patent #:
Issue Dt:
04/29/2008
Application #:
11336538
Filing Dt:
01/20/2006
Publication #:
Pub Dt:
06/29/2006
Title:
METHOD OF TESTING USING COMPLIANT CONTACT STRUCTURES, CONTACTOR CARDS AND TEST SYSTEM
41
Patent #:
Issue Dt:
10/28/2008
Application #:
11336540
Filing Dt:
01/20/2006
Publication #:
Pub Dt:
06/01/2006
Title:
METHODS OF FORMING CONDUCTIVE ELEMENTS USING ORGANOMETALLIC LAYERS AND FLOWABLE, CURABLE CONDUCTIVE MATERIALS
42
Patent #:
Issue Dt:
02/10/2009
Application #:
11336567
Filing Dt:
01/20/2006
Publication #:
Pub Dt:
06/22/2006
Title:
MICROLENSES INCLUDING A PLURALITY OF MUTUALLY ADHERED LAYERS OF OPTICALLY TRANSMISSIVE MATERIAL AND SYSTEMS INCLUDING THE SAME
43
Patent #:
Issue Dt:
03/06/2007
Application #:
11336915
Filing Dt:
01/23/2006
Publication #:
Pub Dt:
06/29/2006
Title:
POWER-ON-RESET CIRCUIT BASED ON THE THRESHOLD LEVELS AND QUADRATIC I-V BEHAVIOR OF MOS TRANSISTORS
44
Patent #:
Issue Dt:
05/19/2009
Application #:
11337030
Filing Dt:
01/20/2006
Publication #:
Pub Dt:
08/17/2006
Title:
CIRCUIT FOR GENERATING AN INTERNAL ENABLING SIGNAL FOR AN OUTPUT BUFFER OF A MEMORY
45
Patent #:
Issue Dt:
09/25/2012
Application #:
11337085
Filing Dt:
01/19/2006
Publication #:
Pub Dt:
08/16/2007
Title:
ENHANCED SECURITY MEMORY ACCESS METHOD AND ARCHITECTURE
46
Patent #:
Issue Dt:
06/23/2009
Application #:
11338066
Filing Dt:
01/24/2006
Publication #:
Pub Dt:
06/22/2006
Title:
ISOLATION CIRCUIT
47
Patent #:
Issue Dt:
05/19/2009
Application #:
11338067
Filing Dt:
01/24/2006
Publication #:
Pub Dt:
07/26/2007
Title:
MEMORY DEVICE FABRICATION
48
Patent #:
Issue Dt:
05/06/2008
Application #:
11338174
Filing Dt:
01/23/2006
Publication #:
Pub Dt:
07/26/2007
Title:
METHOD OF CLEANING A SURFACE OF A COBALT-CONTAINING MATERIAL, METHOD OF FORMING AN OPENING TO A COBALT-CONTAINING MATERIAL, SEMICONDUCTOR PROCESSING METHOD OF FORMING AN INTEGRATED CIRCUIT COMPRISING A COPPER-CONTAINING CONDUCTIVE LINE, AND A COBALT-CONTAINING FILM
49
Patent #:
Issue Dt:
02/05/2008
Application #:
11338937
Filing Dt:
01/25/2006
Publication #:
Pub Dt:
06/22/2006
Title:
SEMICONDUCTOR MEMORY WITH WORDLINE TIMING
50
Patent #:
Issue Dt:
08/26/2008
Application #:
11339177
Filing Dt:
01/20/2006
Publication #:
Pub Dt:
06/08/2006
Title:
SEMICONDUCTOR COMPONENT HAVING THINNED DIE WITH CONDUCTIVE VIAS CONFIGURED AS CONDUCTIVE PIN TERMINAL CONTACTS
51
Patent #:
Issue Dt:
09/18/2007
Application #:
11339399
Filing Dt:
01/25/2006
Publication #:
Pub Dt:
06/22/2006
Title:
METHOD FOR PROGRAMMING AND ERASING AN NROM CELL
52
Patent #:
Issue Dt:
07/10/2007
Application #:
11339437
Filing Dt:
01/24/2006
Title:
MRAM SENSE LAYER ISOLATION
53
Patent #:
Issue Dt:
03/18/2008
Application #:
11339839
Filing Dt:
01/26/2006
Publication #:
Pub Dt:
09/14/2006
Title:
METHODS AND APPARATUS WITH SILICIDE ON CONDUCTIVE STRUCTURES
54
Patent #:
Issue Dt:
11/23/2010
Application #:
11339925
Filing Dt:
01/25/2006
Publication #:
Pub Dt:
06/15/2006
Title:
METHOD AND SYSTEM FOR GENERATING OBJECT CODE TO FACILITATE PREDICTIVE MEMORY RETRIEVAL
55
Patent #:
Issue Dt:
06/30/2009
Application #:
11340089
Filing Dt:
01/26/2006
Publication #:
Pub Dt:
06/22/2006
Title:
NOVEL TRANSMISSION LINES FOR CMOS INTEGRATED CIRCUITS
56
Patent #:
Issue Dt:
08/28/2007
Application #:
11340093
Filing Dt:
01/26/2006
Publication #:
Pub Dt:
07/26/2007
Title:
MEMORY BLOCK ERASING IN A FLASH MEMORY DEVICE
57
Patent #:
Issue Dt:
04/15/2008
Application #:
11340414
Filing Dt:
01/26/2006
Publication #:
Pub Dt:
09/07/2006
Title:
MEMORY DEVICE WITH A RAMP-LIKE VOLTAGE BIASING STRUCTURE BASED ON A CURRENT GENERATOR
58
Patent #:
Issue Dt:
05/20/2008
Application #:
11340886
Filing Dt:
01/27/2006
Publication #:
Pub Dt:
06/08/2006
Title:
METHOD AND APPARATUS FOR SEMICONDUCTOR DEVICE REPAIR WITH REDUCED NUMBER OF PROGRAMMABLE ELEMENTS
59
Patent #:
Issue Dt:
09/09/2008
Application #:
11341062
Filing Dt:
01/27/2006
Publication #:
Pub Dt:
08/02/2007
Title:
DUTY CYCLE ERROR CALCULATION CIRCUIT FOR A CLOCK GENERATOR HAVING A DELAY LOCKED LOOP AND DUTY CYCLE CORRECTION CIRCUIT
60
Patent #:
Issue Dt:
04/10/2007
Application #:
11341199
Filing Dt:
01/27/2006
Publication #:
Pub Dt:
06/22/2006
Title:
METHOD OF FILLING GAPS AND METHODS OF DEPOSITING MATERIALS USING HIGH DENSITY PLASMA CHEMICAL VAPOR DEPOSITION
61
Patent #:
Issue Dt:
10/07/2008
Application #:
11341201
Filing Dt:
01/27/2006
Publication #:
Pub Dt:
08/02/2007
Title:
METHODS OF PATTERNING PHOTORESIST, AND METHODS OF FORMING SEMICONDUCTOR CONSTRUCTIONS
62
Patent #:
Issue Dt:
03/02/2010
Application #:
11341774
Filing Dt:
01/26/2006
Publication #:
Pub Dt:
07/26/2007
Title:
APPARATUS AND METHOD FOR TRIMMING STATIC DELAY OF A SYNCHRONIZING CIRCUIT
63
Patent #:
Issue Dt:
06/03/2008
Application #:
11342425
Filing Dt:
01/30/2006
Publication #:
Pub Dt:
06/15/2006
Title:
DYNAMICALLY ADAPTABLE SEMICONDUCTOR PARAMETRIC TESTING
64
Patent #:
Issue Dt:
05/01/2007
Application #:
11343502
Filing Dt:
01/30/2006
Publication #:
Pub Dt:
06/15/2006
Title:
PLANARITY DIAGNOSTIC SYSTEM, E.G., FOR MICROELECTRONIC COMPONENT TEST SYSTEMS
65
Patent #:
Issue Dt:
06/17/2008
Application #:
11343517
Filing Dt:
01/30/2006
Publication #:
Pub Dt:
06/29/2006
Title:
REDUCTION OF FUSIBLE LINKS AND ASSOCIATED CIRCUITRY ON MEMORY DIES
66
Patent #:
Issue Dt:
07/28/2009
Application #:
11343593
Filing Dt:
01/30/2006
Publication #:
Pub Dt:
06/29/2006
Title:
PROCESS FOR MANUFACTURING INTEGRATED RESISTIVE ELEMENTS WITH SILICIDATION PROTECTION
67
Patent #:
Issue Dt:
04/22/2008
Application #:
11343818
Filing Dt:
01/31/2006
Publication #:
Pub Dt:
06/15/2006
Title:
PIPELINED BURST MEMORY ACCESS
68
Patent #:
Issue Dt:
02/02/2010
Application #:
11344519
Filing Dt:
01/31/2006
Publication #:
Pub Dt:
08/10/2006
Title:
REMOVABLE DATA STORAGE DEVICE AND RELATED ASSEMBLING METHOD
69
Patent #:
Issue Dt:
02/05/2008
Application #:
11344988
Filing Dt:
01/31/2006
Publication #:
Pub Dt:
06/08/2006
Title:
DELAY-LOCKED LOOP HAVING A PRE-SHIFT PHASE DETECTOR
70
Patent #:
Issue Dt:
03/27/2007
Application #:
11345080
Filing Dt:
02/01/2006
Publication #:
Pub Dt:
06/15/2006
Title:
BALLISTIC INJECTION NROM FLASH MEMORY
71
Patent #:
Issue Dt:
07/03/2007
Application #:
11345552
Filing Dt:
01/31/2006
Publication #:
Pub Dt:
06/15/2006
Title:
DELAY-LOCKED LOOP HAVING A PRE-SHIFT PHASE DETECTOR
72
Patent #:
Issue Dt:
09/11/2007
Application #:
11345982
Filing Dt:
02/02/2006
Publication #:
Pub Dt:
06/15/2006
Title:
NROM MEMORY CELL, MEMORY ARRAY, RELATED DEVICES AND METHODS
73
Patent #:
Issue Dt:
05/19/2009
Application #:
11346049
Filing Dt:
02/02/2006
Publication #:
Pub Dt:
03/19/2009
Title:
NROM MEMORY CELL, MEMORY ARRAY, RELATED DEVICES AND METHODS
74
Patent #:
Issue Dt:
09/11/2007
Application #:
11346063
Filing Dt:
02/02/2006
Publication #:
Pub Dt:
06/15/2006
Title:
NROM MEMORY CELL, MEMORY ARRAY, RELATED DEVICES AND METHODS
75
Patent #:
Issue Dt:
11/27/2007
Application #:
11346131
Filing Dt:
02/02/2006
Publication #:
Pub Dt:
06/15/2006
Title:
NROM MEMORY CELL, MEMORY ARRAY, RELATED DEVICES AND METHODS
76
Patent #:
Issue Dt:
11/21/2006
Application #:
11346386
Filing Dt:
02/03/2006
Publication #:
Pub Dt:
06/15/2006
Title:
MEMORY ARCHITECTURE AND METHOD OF MANUFACTURE AND OPERATION THEREOF
77
Patent #:
Issue Dt:
06/02/2009
Application #:
11346413
Filing Dt:
02/02/2006
Publication #:
Pub Dt:
01/08/2009
Title:
NROM MEMORY CELL, MEMORY ARRAY, RELATED DEVICES AND METHODS
78
Patent #:
Issue Dt:
07/06/2010
Application #:
11346421
Filing Dt:
02/02/2006
Publication #:
Pub Dt:
06/15/2006
Title:
NROM MEMORY CELL, MEMORY ARRAY, RELATED DEVICES AND METHODS
79
Patent #:
Issue Dt:
04/22/2008
Application #:
11346870
Filing Dt:
02/02/2006
Publication #:
Pub Dt:
06/15/2006
Title:
MANUFACTURING METHOD FOR A MOS TRANSISTOR COMPRISING LAYERED RELAXED AND STRAINED SIGE LAYERS AS A CHANNEL REGION
80
Patent #:
Issue Dt:
04/20/2010
Application #:
11346914
Filing Dt:
02/02/2006
Publication #:
Pub Dt:
08/02/2007
Title:
METHODS OF FORMING FIELD EFFECT TRANSISTORS, METHODS OF FORMING FIELD EFFECT TRANSISTOR GATES, METHODS OF FORMING INTEGRATED CIRCUITRY COMPRISING A TRANSISTOR GATE ARRAY AND CIRCUITRY PERIPHERAL TO THE GATE ARRAY, AND METHODS OF FORMING INTEGRATED CIRCUITRY COMPRIS
81
Patent #:
Issue Dt:
09/11/2007
Application #:
11346963
Filing Dt:
02/03/2006
Publication #:
Pub Dt:
06/29/2006
Title:
METHODS OF FORMING SEMICONDUCTOR CONSTRUCTIONS
82
Patent #:
Issue Dt:
07/31/2007
Application #:
11346985
Filing Dt:
02/02/2006
Publication #:
Pub Dt:
06/15/2006
Title:
SEMICONDUCTOR CIRCUITRY CONSTRUCTIONS
83
Patent #:
Issue Dt:
08/12/2008
Application #:
11347051
Filing Dt:
02/03/2006
Publication #:
Pub Dt:
06/29/2006
Title:
AGGLOMERATION CONTROL USING EARLY TRANSITION METAL ALLOYS
84
Patent #:
Issue Dt:
02/22/2011
Application #:
11347153
Filing Dt:
02/03/2006
Publication #:
Pub Dt:
08/09/2007
Title:
METHODS FOR FABRICATING AND FILLING CONDUCTIVE VIAS AND CONDUCTIVE VIAS SO FORMED
85
Patent #:
Issue Dt:
09/16/2008
Application #:
11347477
Filing Dt:
02/03/2006
Publication #:
Pub Dt:
08/09/2007
Title:
INPUT BUFFER WITH OPTIMAL BIASING AND METHOD THEREOF
86
Patent #:
Issue Dt:
01/04/2011
Application #:
11347863
Filing Dt:
02/06/2006
Publication #:
Pub Dt:
08/09/2007
Title:
MICROELECTRONIC DEVICES AND METHODS FOR MANUFACTURING MICROELECTRONIC DEVICES
87
Patent #:
Issue Dt:
06/24/2008
Application #:
11347930
Filing Dt:
02/06/2006
Publication #:
Pub Dt:
06/15/2006
Title:
METHOD FOR FABRICATING SEMICONDUCTOR COMPONENTS WITH CONDUCTIVE SPRING CONTACTS
88
Patent #:
Issue Dt:
10/07/2008
Application #:
11347961
Filing Dt:
02/06/2006
Publication #:
Pub Dt:
06/15/2006
Title:
APPARATUS WITH EQUALIZING VOLTAGE GENERATION CIRCUIT AND METHODS OF USE
89
Patent #:
Issue Dt:
12/30/2008
Application #:
11348513
Filing Dt:
02/06/2006
Publication #:
Pub Dt:
09/14/2006
Title:
METHOD FOR PROGRAMMING A MEMORY DEVICE SUITABLE TO MINIMIZE THE LATERAL COUPLING EFFECTS BETWEEN MEMORY CELLS
90
Patent #:
Issue Dt:
12/01/2009
Application #:
11348571
Filing Dt:
02/06/2006
Publication #:
Pub Dt:
06/15/2006
Title:
MEMORY DEVICES, ELECTRONIC SYSTEMS, AND METHODS OF FORMING MEMORY DEVICES
91
Patent #:
Issue Dt:
01/27/2009
Application #:
11348678
Filing Dt:
02/07/2006
Publication #:
Pub Dt:
08/09/2007
Title:
ERASE OPERATION IN A FLASH MEMORY DEVICE
92
Patent #:
Issue Dt:
08/26/2008
Application #:
11349397
Filing Dt:
02/06/2006
Publication #:
Pub Dt:
08/09/2007
Title:
DELAY LINE CIRCUIT
93
Patent #:
Issue Dt:
10/02/2007
Application #:
11349801
Filing Dt:
02/08/2006
Publication #:
Pub Dt:
07/13/2006
Title:
MULTIPHASE CLOCK GENERATION
94
Patent #:
Issue Dt:
11/10/2009
Application #:
11349854
Filing Dt:
02/08/2006
Publication #:
Pub Dt:
08/09/2007
Title:
MEMORY ARRAY SEGMENTATION AND METHODS
95
Patent #:
Issue Dt:
03/09/2010
Application #:
11349959
Filing Dt:
02/09/2006
Publication #:
Pub Dt:
08/10/2006
Title:
PHASE CHANGE MEMORY DEVICE
96
Patent #:
Issue Dt:
11/06/2007
Application #:
11350061
Filing Dt:
02/08/2006
Publication #:
Pub Dt:
06/15/2006
Title:
METHODS OF FORMING TRANSISTOR CONSTRUCTIONS
97
Patent #:
Issue Dt:
05/05/2009
Application #:
11350961
Filing Dt:
02/08/2006
Publication #:
Pub Dt:
06/15/2006
Title:
MEMORY SUBSYSTEM VOLTAGE CONTROL AND METHOD THAT REPROGRAMS A PREFERRED OPERATING VOLTAGE
98
Patent #:
Issue Dt:
10/16/2007
Application #:
11351006
Filing Dt:
02/08/2006
Publication #:
Pub Dt:
06/15/2006
Title:
METHODS OF MANUFACTURE OF A VIA STRUCTURE COMPRISING A PLURALITY OF CONDUCTIVE ELEMENTS AND METHODS OF FORMING MULTICHIP MODULES INCLUDING SUCH VIA STRUCTURES
99
Patent #:
Issue Dt:
10/02/2007
Application #:
11351008
Filing Dt:
02/08/2006
Publication #:
Pub Dt:
06/15/2006
Title:
OPERATIONAL VOLTAGE CONTROL CIRCUIT AND METHOD
100
Patent #:
Issue Dt:
02/16/2010
Application #:
11351009
Filing Dt:
02/08/2006
Publication #:
Pub Dt:
06/15/2006
Title:
INTERPOSER INCLUDING AT LEAST ONE PASSIVE ELEMENT AT LEAST PARTIALLY DEFINED BY A RECESS FORMED THEREIN, SYSTEM INCLUDING SAME, AND WAFER-SCALE INTERPOSER
Assignors
1
Exec Dt:
07/03/2018
2
Exec Dt:
07/03/2018
Assignee
1
10 S. DEARBORN
7TH FLOOR
CHICAGO, ILLINOIS 60603
Correspondence name and address
MARCELA ROBLEDO
2475 HANOVER STREET
PALO ALTO, CA 94304

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