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07/12/2007
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07/19/2007
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12/28/2010
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07/19/2007
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07/26/2007
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Pub Dt:
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06/08/2006
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Title:
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METHOD AND APPARATUS FOR SEMICONDUCTOR DEVICE REPAIR WITH REDUCED NUMBER OF PROGRAMMABLE ELEMENTS
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Patent #:
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Issue Dt:
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09/09/2008
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Application #:
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11341062
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Filing Dt:
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01/27/2006
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Publication #:
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Pub Dt:
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08/02/2007
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Title:
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DUTY CYCLE ERROR CALCULATION CIRCUIT FOR A CLOCK GENERATOR HAVING A DELAY LOCKED LOOP AND DUTY CYCLE CORRECTION CIRCUIT
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Patent #:
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Issue Dt:
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04/10/2007
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Application #:
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11341199
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Filing Dt:
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01/27/2006
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Publication #:
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Pub Dt:
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06/22/2006
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Title:
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METHOD OF FILLING GAPS AND METHODS OF DEPOSITING MATERIALS USING HIGH DENSITY PLASMA CHEMICAL VAPOR DEPOSITION
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Patent #:
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Issue Dt:
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10/07/2008
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Application #:
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11341201
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Filing Dt:
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01/27/2006
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Publication #:
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Pub Dt:
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08/02/2007
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Title:
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METHODS OF PATTERNING PHOTORESIST, AND METHODS OF FORMING SEMICONDUCTOR CONSTRUCTIONS
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Patent #:
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Issue Dt:
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03/02/2010
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Application #:
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11341774
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Filing Dt:
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01/26/2006
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Publication #:
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Pub Dt:
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07/26/2007
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Title:
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APPARATUS AND METHOD FOR TRIMMING STATIC DELAY OF A SYNCHRONIZING CIRCUIT
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Patent #:
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Issue Dt:
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06/03/2008
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Application #:
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11342425
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Filing Dt:
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01/30/2006
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Publication #:
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Pub Dt:
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06/15/2006
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Title:
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DYNAMICALLY ADAPTABLE SEMICONDUCTOR PARAMETRIC TESTING
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Patent #:
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Issue Dt:
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05/01/2007
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Application #:
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11343502
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Filing Dt:
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01/30/2006
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Publication #:
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Pub Dt:
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06/15/2006
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Title:
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PLANARITY DIAGNOSTIC SYSTEM, E.G., FOR MICROELECTRONIC COMPONENT TEST SYSTEMS
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Patent #:
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Issue Dt:
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06/17/2008
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Application #:
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11343517
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Filing Dt:
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01/30/2006
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Publication #:
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Pub Dt:
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06/29/2006
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Title:
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REDUCTION OF FUSIBLE LINKS AND ASSOCIATED CIRCUITRY ON MEMORY DIES
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Patent #:
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Issue Dt:
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07/28/2009
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Application #:
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11343593
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Filing Dt:
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01/30/2006
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Publication #:
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Pub Dt:
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06/29/2006
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Title:
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PROCESS FOR MANUFACTURING INTEGRATED RESISTIVE ELEMENTS WITH SILICIDATION PROTECTION
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Patent #:
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Issue Dt:
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04/22/2008
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Application #:
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11343818
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Filing Dt:
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01/31/2006
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Publication #:
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Pub Dt:
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06/15/2006
| | | | |
Title:
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PIPELINED BURST MEMORY ACCESS
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Patent #:
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Issue Dt:
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02/02/2010
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Application #:
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11344519
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Filing Dt:
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01/31/2006
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Publication #:
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Pub Dt:
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08/10/2006
| | | | |
Title:
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REMOVABLE DATA STORAGE DEVICE AND RELATED ASSEMBLING METHOD
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Patent #:
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Issue Dt:
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02/05/2008
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Application #:
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11344988
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Filing Dt:
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01/31/2006
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Publication #:
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Pub Dt:
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06/08/2006
| | | | |
Title:
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DELAY-LOCKED LOOP HAVING A PRE-SHIFT PHASE DETECTOR
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Patent #:
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Issue Dt:
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03/27/2007
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Application #:
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11345080
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Filing Dt:
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02/01/2006
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Publication #:
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Pub Dt:
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06/15/2006
| | | | |
Title:
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BALLISTIC INJECTION NROM FLASH MEMORY
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Patent #:
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Issue Dt:
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07/03/2007
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Application #:
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11345552
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Filing Dt:
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01/31/2006
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Publication #:
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Pub Dt:
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06/15/2006
| | | | |
Title:
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DELAY-LOCKED LOOP HAVING A PRE-SHIFT PHASE DETECTOR
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Patent #:
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Issue Dt:
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09/11/2007
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Application #:
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11345982
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Filing Dt:
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02/02/2006
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Publication #:
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Pub Dt:
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06/15/2006
| | | | |
Title:
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NROM MEMORY CELL, MEMORY ARRAY, RELATED DEVICES AND METHODS
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Patent #:
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Issue Dt:
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05/19/2009
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Application #:
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11346049
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Filing Dt:
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02/02/2006
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Publication #:
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Pub Dt:
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03/19/2009
| | | | |
Title:
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NROM MEMORY CELL, MEMORY ARRAY, RELATED DEVICES AND METHODS
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Patent #:
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Issue Dt:
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09/11/2007
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Application #:
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11346063
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Filing Dt:
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02/02/2006
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Publication #:
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Pub Dt:
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06/15/2006
| | | | |
Title:
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NROM MEMORY CELL, MEMORY ARRAY, RELATED DEVICES AND METHODS
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Patent #:
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Issue Dt:
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11/27/2007
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Application #:
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11346131
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Filing Dt:
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02/02/2006
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Publication #:
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Pub Dt:
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06/15/2006
| | | | |
Title:
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NROM MEMORY CELL, MEMORY ARRAY, RELATED DEVICES AND METHODS
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Patent #:
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Issue Dt:
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11/21/2006
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Application #:
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11346386
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Filing Dt:
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02/03/2006
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Publication #:
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Pub Dt:
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06/15/2006
| | | | |
Title:
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MEMORY ARCHITECTURE AND METHOD OF MANUFACTURE AND OPERATION THEREOF
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Patent #:
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Issue Dt:
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06/02/2009
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Application #:
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11346413
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Filing Dt:
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02/02/2006
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Publication #:
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Pub Dt:
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01/08/2009
| | | | |
Title:
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NROM MEMORY CELL, MEMORY ARRAY, RELATED DEVICES AND METHODS
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Patent #:
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Issue Dt:
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07/06/2010
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Application #:
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11346421
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Filing Dt:
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02/02/2006
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Publication #:
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Pub Dt:
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06/15/2006
| | | | |
Title:
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NROM MEMORY CELL, MEMORY ARRAY, RELATED DEVICES AND METHODS
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Patent #:
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Issue Dt:
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04/22/2008
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Application #:
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11346870
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Filing Dt:
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02/02/2006
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Publication #:
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Pub Dt:
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06/15/2006
| | | | |
Title:
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MANUFACTURING METHOD FOR A MOS TRANSISTOR COMPRISING LAYERED RELAXED AND STRAINED SIGE LAYERS AS A CHANNEL REGION
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Patent #:
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Issue Dt:
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04/20/2010
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Application #:
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11346914
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Filing Dt:
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02/02/2006
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Publication #:
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Pub Dt:
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08/02/2007
| | | | |
Title:
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METHODS OF FORMING FIELD EFFECT TRANSISTORS, METHODS OF FORMING FIELD EFFECT TRANSISTOR GATES, METHODS OF FORMING INTEGRATED CIRCUITRY COMPRISING A TRANSISTOR GATE ARRAY AND CIRCUITRY PERIPHERAL TO THE GATE ARRAY, AND METHODS OF FORMING INTEGRATED CIRCUITRY COMPRIS
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Patent #:
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Issue Dt:
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09/11/2007
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Application #:
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11346963
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Filing Dt:
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02/03/2006
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Publication #:
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Pub Dt:
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06/29/2006
| | | | |
Title:
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METHODS OF FORMING SEMICONDUCTOR CONSTRUCTIONS
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Patent #:
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Issue Dt:
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07/31/2007
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Application #:
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11346985
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Filing Dt:
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02/02/2006
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Publication #:
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Pub Dt:
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06/15/2006
| | | | |
Title:
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SEMICONDUCTOR CIRCUITRY CONSTRUCTIONS
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Patent #:
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Issue Dt:
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08/12/2008
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Application #:
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11347051
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Filing Dt:
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02/03/2006
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Publication #:
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Pub Dt:
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06/29/2006
| | | | |
Title:
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AGGLOMERATION CONTROL USING EARLY TRANSITION METAL ALLOYS
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Patent #:
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Issue Dt:
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02/22/2011
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Application #:
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11347153
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Filing Dt:
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02/03/2006
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Publication #:
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Pub Dt:
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08/09/2007
| | | | |
Title:
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METHODS FOR FABRICATING AND FILLING CONDUCTIVE VIAS AND CONDUCTIVE VIAS SO FORMED
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Patent #:
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Issue Dt:
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09/16/2008
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Application #:
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11347477
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Filing Dt:
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02/03/2006
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Publication #:
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Pub Dt:
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08/09/2007
| | | | |
Title:
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INPUT BUFFER WITH OPTIMAL BIASING AND METHOD THEREOF
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Patent #:
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Issue Dt:
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01/04/2011
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Application #:
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11347863
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Filing Dt:
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02/06/2006
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Publication #:
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Pub Dt:
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08/09/2007
| | | | |
Title:
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MICROELECTRONIC DEVICES AND METHODS FOR MANUFACTURING MICROELECTRONIC DEVICES
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Patent #:
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Issue Dt:
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06/24/2008
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11347930
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Filing Dt:
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02/06/2006
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Publication #:
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Pub Dt:
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06/15/2006
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Title:
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METHOD FOR FABRICATING SEMICONDUCTOR COMPONENTS WITH CONDUCTIVE SPRING CONTACTS
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Patent #:
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Issue Dt:
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10/07/2008
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11347961
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Filing Dt:
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02/06/2006
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Publication #:
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Pub Dt:
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06/15/2006
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Title:
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APPARATUS WITH EQUALIZING VOLTAGE GENERATION CIRCUIT AND METHODS OF USE
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Patent #:
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Issue Dt:
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12/30/2008
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Application #:
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11348513
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Filing Dt:
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02/06/2006
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Publication #:
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Pub Dt:
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09/14/2006
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Title:
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METHOD FOR PROGRAMMING A MEMORY DEVICE SUITABLE TO MINIMIZE THE LATERAL COUPLING EFFECTS BETWEEN MEMORY CELLS
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Patent #:
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Issue Dt:
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12/01/2009
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Application #:
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11348571
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Filing Dt:
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02/06/2006
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Publication #:
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Pub Dt:
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06/15/2006
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Title:
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MEMORY DEVICES, ELECTRONIC SYSTEMS, AND METHODS OF FORMING MEMORY DEVICES
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Issue Dt:
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01/27/2009
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11348678
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Filing Dt:
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02/07/2006
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Publication #:
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Pub Dt:
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08/09/2007
| | | | |
Title:
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ERASE OPERATION IN A FLASH MEMORY DEVICE
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Patent #:
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Issue Dt:
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08/26/2008
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11349397
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Filing Dt:
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02/06/2006
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Publication #:
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Pub Dt:
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08/09/2007
| | | | |
Title:
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DELAY LINE CIRCUIT
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Patent #:
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Issue Dt:
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10/02/2007
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Application #:
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11349801
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Filing Dt:
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02/08/2006
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Publication #:
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Pub Dt:
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07/13/2006
| | | | |
Title:
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MULTIPHASE CLOCK GENERATION
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Patent #:
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Issue Dt:
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11/10/2009
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Application #:
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11349854
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Filing Dt:
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02/08/2006
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Publication #:
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Pub Dt:
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08/09/2007
| | | | |
Title:
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MEMORY ARRAY SEGMENTATION AND METHODS
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Patent #:
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Issue Dt:
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03/09/2010
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Application #:
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11349959
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Filing Dt:
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02/09/2006
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Publication #:
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Pub Dt:
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08/10/2006
| | | | |
Title:
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PHASE CHANGE MEMORY DEVICE
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Patent #:
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Issue Dt:
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11/06/2007
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Application #:
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11350061
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Filing Dt:
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02/08/2006
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Publication #:
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Pub Dt:
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06/15/2006
| | | | |
Title:
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METHODS OF FORMING TRANSISTOR CONSTRUCTIONS
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Patent #:
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Issue Dt:
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05/05/2009
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Application #:
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11350961
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Filing Dt:
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02/08/2006
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Publication #:
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Pub Dt:
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06/15/2006
| | | | |
Title:
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MEMORY SUBSYSTEM VOLTAGE CONTROL AND METHOD THAT REPROGRAMS A PREFERRED OPERATING VOLTAGE
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Patent #:
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Issue Dt:
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10/16/2007
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Application #:
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11351006
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Filing Dt:
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02/08/2006
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Publication #:
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Pub Dt:
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06/15/2006
| | | | |
Title:
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METHODS OF MANUFACTURE OF A VIA STRUCTURE COMPRISING A PLURALITY OF CONDUCTIVE ELEMENTS AND METHODS OF FORMING MULTICHIP MODULES INCLUDING SUCH VIA STRUCTURES
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Patent #:
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Issue Dt:
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10/02/2007
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Application #:
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11351008
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Filing Dt:
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02/08/2006
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Publication #:
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Pub Dt:
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06/15/2006
| | | | |
Title:
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OPERATIONAL VOLTAGE CONTROL CIRCUIT AND METHOD
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Patent #:
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Issue Dt:
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02/16/2010
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Application #:
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11351009
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Filing Dt:
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02/08/2006
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Publication #:
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Pub Dt:
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06/15/2006
| | | | |
Title:
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INTERPOSER INCLUDING AT LEAST ONE PASSIVE ELEMENT AT LEAST PARTIALLY DEFINED BY A RECESS FORMED THEREIN, SYSTEM INCLUDING SAME, AND WAFER-SCALE INTERPOSER
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