|
|
Patent #:
|
|
Issue Dt:
|
12/15/2009
|
Application #:
|
11382668
|
Filing Dt:
|
05/10/2006
|
Publication #:
|
|
Pub Dt:
|
11/15/2007
| | | | |
Title:
|
ON-DIE ANTI-RESONANCE STRUCTURE FOR INTEGRATED CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
11/03/2009
|
Application #:
|
11383905
|
Filing Dt:
|
05/17/2006
|
Publication #:
|
|
Pub Dt:
|
09/21/2006
| | | | |
Title:
|
METHODS FOR FORMING A MRAM WITH NON-ORTHOGONAL WIRING
|
|
|
Patent #:
|
|
Issue Dt:
|
09/07/2010
|
Application #:
|
11383923
|
Filing Dt:
|
05/17/2006
|
Publication #:
|
|
Pub Dt:
|
11/22/2007
| | | | |
Title:
|
SYSTEM AND METHOD FOR RECIRCULATING FLUID SUPPLY FOR AN INJECTOR FOR A SEMICONDUCTOR FABRICATION CHAMBER
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11384734
|
Filing Dt:
|
03/20/2006
|
Publication #:
|
|
Pub Dt:
|
09/20/2007
| | | | |
Title:
|
Carrierless chip package for integrated circuit devices, and methods of making same
|
|
|
Patent #:
|
|
Issue Dt:
|
10/23/2007
|
Application #:
|
11384853
|
Filing Dt:
|
03/20/2006
|
Publication #:
|
|
Pub Dt:
|
07/20/2006
| | | | |
Title:
|
DYNAMIC RANDOM ACCESS MEMORY CIRCUITRY AND INTEGRATED CIRCUITRY
|
|
|
Patent #:
|
|
Issue Dt:
|
10/05/2010
|
Application #:
|
11384965
|
Filing Dt:
|
03/20/2006
|
Publication #:
|
|
Pub Dt:
|
09/27/2007
| | | | |
Title:
|
VARIABLE SECTOR-COUNT ECC
|
|
|
Patent #:
|
|
Issue Dt:
|
09/30/2008
|
Application #:
|
11386157
|
Filing Dt:
|
03/21/2006
|
Publication #:
|
|
Pub Dt:
|
07/27/2006
| | | | |
Title:
|
USE OF SELECTIVE OXIDATION TO FORM ASYMMETRICAL OXIDE FEATURES DURING THE MANUFACTURE OF A SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2008
|
Application #:
|
11386167
|
Filing Dt:
|
03/21/2006
|
Publication #:
|
|
Pub Dt:
|
07/27/2006
| | | | |
Title:
|
METHODS OF FABRICATING MULTIPLE SETS OF FIELD EFFECT TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/20/2007
|
Application #:
|
11386208
|
Filing Dt:
|
03/22/2006
|
Publication #:
|
|
Pub Dt:
|
07/20/2006
| | | | |
Title:
|
FABRICATION OF STACKED MICROELECTRONIC DEVICES
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11386474
|
Filing Dt:
|
03/22/2006
|
Publication #:
|
|
Pub Dt:
|
07/27/2006
| | | | |
Title:
|
Substrate mapping
|
|
|
Patent #:
|
|
Issue Dt:
|
09/07/2010
|
Application #:
|
11387707
|
Filing Dt:
|
03/24/2006
|
Publication #:
|
|
Pub Dt:
|
09/27/2007
| | | | |
Title:
|
METHOD OF FABRICATING DIFFERENT GATE OXIDES FOR DIFFERENT TRANSISTORS IN AN INTEGRATED CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
04/01/2008
|
Application #:
|
11388296
|
Filing Dt:
|
03/24/2006
|
Publication #:
|
|
Pub Dt:
|
09/27/2007
| | | | |
Title:
|
SYSTEM AND METHOD FOR RE-ROUTING SIGNALS BETWEEN MEMORY SYSTEM COMPONENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/19/2006
|
Application #:
|
11388593
|
Filing Dt:
|
03/24/2006
|
Publication #:
|
|
Pub Dt:
|
08/17/2006
| | | | |
Title:
|
RESAMPLING SYSTEM AND METHOD FOR GRAPHICS DATA INCLUDING SINE-WAVE COMPONENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/18/2008
|
Application #:
|
11389149
|
Filing Dt:
|
03/27/2006
|
Publication #:
|
|
Pub Dt:
|
07/27/2006
| | | | |
Title:
|
DIELECTRIC RELAXATION MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
11/25/2008
|
Application #:
|
11389150
|
Filing Dt:
|
03/27/2006
|
Publication #:
|
|
Pub Dt:
|
07/27/2006
| | | | |
Title:
|
DIELECTRIC RELAXATION MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
10/18/2011
|
Application #:
|
11389157
|
Filing Dt:
|
03/27/2006
|
Publication #:
|
|
Pub Dt:
|
07/27/2006
| | | | |
Title:
|
DEUTERATED STRUCTURES FOR IMAGE SENSORS AND METHODS FOR FORMING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
08/25/2009
|
Application #:
|
11389581
|
Filing Dt:
|
03/23/2006
|
Publication #:
|
|
Pub Dt:
|
09/27/2007
| | | | |
Title:
|
TOPOGRAPHY DIRECTED PATTERNING
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2008
|
Application #:
|
11389632
|
Filing Dt:
|
03/24/2006
|
Publication #:
|
|
Pub Dt:
|
07/27/2006
| | | | |
Title:
|
SEMICONDUCTOR CONSTRUCTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/14/2013
|
Application #:
|
11389707
|
Filing Dt:
|
03/27/2006
|
Publication #:
|
|
Pub Dt:
|
07/27/2006
| | | | |
Title:
|
METHOD FOR FORMING A RUTHENIUM METAL LAYER AND A STRUCTURE COMPRISING THE RUTHENIUM METAL LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
12/02/2008
|
Application #:
|
11389722
|
Filing Dt:
|
03/27/2006
|
Publication #:
|
|
Pub Dt:
|
07/27/2006
| | | | |
Title:
|
CHIP ON BOARD LEADFRAME FOR SEMICONDUCTOR COMPONENTS HAVING AREA ARRAY
|
|
|
Patent #:
|
|
Issue Dt:
|
01/27/2009
|
Application #:
|
11390321
|
Filing Dt:
|
03/27/2006
|
Publication #:
|
|
Pub Dt:
|
08/17/2006
| | | | |
Title:
|
Semiconductor component sealed on five sides by polymer sealing layer
|
|
|
Patent #:
|
|
Issue Dt:
|
07/14/2009
|
Application #:
|
11390747
|
Filing Dt:
|
03/28/2006
|
Publication #:
|
|
Pub Dt:
|
10/11/2007
| | | | |
Title:
|
PROGRAMMING METHOD TO REDUCE WORD LINE TO WORD LINE BREAKDOWN FOR NAND FLASH
|
|
|
Patent #:
|
|
Issue Dt:
|
07/22/2008
|
Application #:
|
11390852
|
Filing Dt:
|
03/28/2006
|
Publication #:
|
|
Pub Dt:
|
08/31/2006
| | | | |
Title:
|
FORWARD BIASING PROTECTION CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
07/05/2011
|
Application #:
|
11391087
|
Filing Dt:
|
03/28/2006
|
Publication #:
|
|
Pub Dt:
|
08/03/2006
| | | | |
Title:
|
FULLY DEPLETED SILICON-ON-INSULATOR CMOS LOGIC
|
|
|
Patent #:
|
|
Issue Dt:
|
09/27/2011
|
Application #:
|
11391286
|
Filing Dt:
|
03/29/2006
|
Publication #:
|
|
Pub Dt:
|
10/05/2006
| | | | |
Title:
|
SEMICONDUCTOR DEVICE HAVING A DUMMY GATE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/13/2009
|
Application #:
|
11391450
|
Filing Dt:
|
03/29/2006
|
Publication #:
|
|
Pub Dt:
|
11/02/2006
| | | | |
Title:
|
MEMORY MODULE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/21/2010
|
Application #:
|
11391774
|
Filing Dt:
|
03/29/2006
|
Publication #:
|
|
Pub Dt:
|
08/03/2006
| | | | |
Title:
|
METHODS OF FORMING INTERMEDIATE SEMICONDUCTOR DEVICE STRUCTURES USING SPIN-ON, PHOTOPATTERNABLE, INTERLAYER DIELECTRIC MATERIALS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/02/2007
|
Application #:
|
11392290
|
Filing Dt:
|
03/29/2006
|
Publication #:
|
|
Pub Dt:
|
08/03/2006
| | | | |
Title:
|
FORMING MULTI-LAYER MEMORY ARRAYS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/06/2013
|
Application #:
|
11393513
|
Filing Dt:
|
03/29/2006
|
Publication #:
|
|
Pub Dt:
|
11/01/2007
| | | | |
Title:
|
METHODS OF FORMING SEMICONDUCTOR CONSTRUCTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/08/2008
|
Application #:
|
11393666
|
Filing Dt:
|
03/31/2006
|
Publication #:
|
|
Pub Dt:
|
10/05/2006
| | | | |
Title:
|
SEMICONDUCTOR STORAGE DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/27/2010
|
Application #:
|
11393800
|
Filing Dt:
|
03/31/2006
|
Publication #:
|
|
Pub Dt:
|
10/05/2006
| | | | |
Title:
|
SEMICONDUCTOR DEVICE MANUFACTURING METHOD FOR PREVENTING PATTERNS FROM INCLINING IN DRYING PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/30/2008
|
Application #:
|
11394262
|
Filing Dt:
|
03/30/2006
|
Publication #:
|
|
Pub Dt:
|
10/04/2007
| | | | |
Title:
|
MEMORY MODULE, SYSTEM AND METHOD OF MAKING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
04/20/2010
|
Application #:
|
11394772
|
Filing Dt:
|
03/31/2006
|
Publication #:
|
|
Pub Dt:
|
08/17/2006
| | | | |
Title:
|
SEMICONDUCTOR DEVICES AND IN-PROCESS SEMICONDUCTOR DEVICES HAVING CONDUCTOR-FILLED VIAS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/2008
|
Application #:
|
11394988
|
Filing Dt:
|
03/30/2006
|
Publication #:
|
|
Pub Dt:
|
08/03/2006
| | | | |
Title:
|
PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION METHOD OF FORMING TITANIUM SILICIDE COMPRISING LAYERS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/01/2008
|
Application #:
|
11394989
|
Filing Dt:
|
03/30/2006
|
Publication #:
|
|
Pub Dt:
|
08/03/2006
| | | | |
Title:
|
PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION METHOD OF FORMING TITANIUM SILICIDE COMPRISING LAYERS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/21/2009
|
Application #:
|
11394994
|
Filing Dt:
|
03/30/2006
|
Publication #:
|
|
Pub Dt:
|
10/04/2007
| | | | |
Title:
|
WIRELESS COMMUNICATIONS WITH AUXILIARY ANTENNAS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/05/2008
|
Application #:
|
11395721
|
Filing Dt:
|
03/31/2006
|
Publication #:
|
|
Pub Dt:
|
08/03/2006
| | | | |
Title:
|
SEMICONDUCTOR CIRCUIT CONSTRUCTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/12/2010
|
Application #:
|
11396616
|
Filing Dt:
|
04/04/2006
|
Publication #:
|
|
Pub Dt:
|
10/25/2007
| | | | |
Title:
|
PHASE CHANGE MEMORY ELEMENTS USING SELF-ALIGNED PHASE CHANGE MATERIAL LAYERS AND METHODS OF MAKING AND USING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
01/15/2013
|
Application #:
|
11397358
|
Filing Dt:
|
04/04/2006
|
Publication #:
|
|
Pub Dt:
|
10/04/2007
| | | | |
Title:
|
METHOD FOR FORMING NANOFIN TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/17/2009
|
Application #:
|
11397413
|
Filing Dt:
|
04/04/2006
|
Publication #:
|
|
Pub Dt:
|
10/04/2007
| | | | |
Title:
|
DRAM WITH NANOFIN TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/27/2014
|
Application #:
|
11397430
|
Filing Dt:
|
04/04/2006
|
Publication #:
|
|
Pub Dt:
|
10/04/2007
| | | | |
Title:
|
Grown nanofin transistors
|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/2008
|
Application #:
|
11397459
|
Filing Dt:
|
04/04/2006
|
Publication #:
|
|
Pub Dt:
|
08/10/2006
| | | | |
Title:
|
INTERPOSERS WITH FLEXIBLE SOLDER PAD ELEMENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/16/2008
|
Application #:
|
11397527
|
Filing Dt:
|
04/04/2006
|
Publication #:
|
|
Pub Dt:
|
10/04/2007
| | | | |
Title:
|
NANOWIRE TRANSISTOR WITH SURROUNDING GATE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/14/2008
|
Application #:
|
11397689
|
Filing Dt:
|
04/05/2006
|
Publication #:
|
|
Pub Dt:
|
10/26/2006
| | | | |
Title:
|
SEMICONDUCTOR MEMORY DEVICE INCLUDING FUSE DETECTION CIRCUIT TO DETERMINE SUCCESSFUL FUSE-CUTTING RATE FOR OPTICAL FUSE-CUTTING CONDITIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/18/2008
|
Application #:
|
11398780
|
Filing Dt:
|
04/05/2006
|
Publication #:
|
|
Pub Dt:
|
11/01/2007
| | | | |
Title:
|
MEMORY DEVICE TESTING SYSTEM AND METHOD HAVING REAL TIME REDUNDANCY REPAIR ANALYSIS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/23/2012
|
Application #:
|
11398809
|
Filing Dt:
|
04/06/2006
|
Publication #:
|
|
Pub Dt:
|
10/11/2007
| | | | |
Title:
|
DEVICES AND METHODS TO IMPROVE CARRIER MOBILITY
|
|
|
Patent #:
|
|
Issue Dt:
|
10/21/2008
|
Application #:
|
11398858
|
Filing Dt:
|
04/06/2006
|
Publication #:
|
|
Pub Dt:
|
03/08/2007
| | | | |
Title:
|
PHASE CHANGE MEMORY CELL WITH TUBULAR HEATER AND MANUFACTURING METHOD THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
03/08/2011
|
Application #:
|
11398912
|
Filing Dt:
|
04/06/2006
|
Publication #:
|
|
Pub Dt:
|
08/10/2006
| | | | |
Title:
|
INTERPOSER CONFIGURED TO REDUCE THE PROFILES OF SEMICONDUCTOR DEVICE ASSEMBLIES, PACKAGES INCLUDING THE SAME, AND METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/19/2010
|
Application #:
|
11399372
|
Filing Dt:
|
04/07/2006
|
Publication #:
|
|
Pub Dt:
|
08/10/2006
| | | | |
Title:
|
RAISED PHOTODIODE SENSOR TO INCREASE FILL FACTOR AND QUANTUM EFFICIENCY IN SCALED PIXELS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/23/2008
|
Application #:
|
11399761
|
Filing Dt:
|
04/07/2006
|
Publication #:
|
|
Pub Dt:
|
08/17/2006
| | | | |
Title:
|
HIGH DENSITY STEPPED, NON-PLANAR NITRIDE READ ONLY MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
08/10/2010
|
Application #:
|
11399952
|
Filing Dt:
|
04/07/2006
|
Publication #:
|
|
Pub Dt:
|
08/17/2006
| | | | |
Title:
|
POWER UP INITIALIZATION FOR MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
01/04/2011
|
Application #:
|
11400348
|
Filing Dt:
|
04/07/2006
|
Publication #:
|
|
Pub Dt:
|
10/11/2007
| | | | |
Title:
|
HYBRID ELECTRICAL CONTACT
|
|
|
Patent #:
|
|
Issue Dt:
|
03/08/2011
|
Application #:
|
11400603
|
Filing Dt:
|
04/07/2006
|
Publication #:
|
|
Pub Dt:
|
10/11/2007
| | | | |
Title:
|
SIMPLIFIED PITCH DOUBLING PROCESS FLOW
|
|
|
Patent #:
|
|
Issue Dt:
|
06/05/2012
|
Application #:
|
11400707
|
Filing Dt:
|
04/06/2006
|
Publication #:
|
|
Pub Dt:
|
10/11/2007
| | | | |
Title:
|
METHOD OF MANUFACTURE OF CONSTANT GROOVE DEPTH PADS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/01/2009
|
Application #:
|
11400836
|
Filing Dt:
|
04/07/2006
|
Publication #:
|
|
Pub Dt:
|
10/11/2007
| | | | |
Title:
|
ATOMIC LAYER DEPOSITED TITANIUM-DOPED INDIUM OXIDE FILMS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/27/2007
|
Application #:
|
11400993
|
Filing Dt:
|
04/10/2006
|
Publication #:
|
|
Pub Dt:
|
08/17/2006
| | | | |
Title:
|
NON-VOLATILE MEMORY WITH ERASE VERIFY CIRCUIT HAVING COMPARATORS INDICATING UNDER-ERASURE, ERASURE, AND OVER-ERASURE OF MEMORY CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/02/2008
|
Application #:
|
11401153
|
Filing Dt:
|
04/10/2006
|
Publication #:
|
|
Pub Dt:
|
08/17/2006
| | | | |
Title:
|
DOUBLE DENSITY MRAM WITH PLANAR PROCESSING
|
|
|
Patent #:
|
|
Issue Dt:
|
02/20/2007
|
Application #:
|
11401166
|
Filing Dt:
|
04/10/2006
|
Publication #:
|
|
Pub Dt:
|
08/17/2006
| | | | |
Title:
|
SCRATCH CONTROL MEMORY ARRAY IN A FLASH MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/09/2010
|
Application #:
|
11401521
|
Filing Dt:
|
04/11/2006
|
Publication #:
|
|
Pub Dt:
|
11/09/2006
| | | | |
Title:
|
ELECTRONIC NON-VOLATILE MEMORY DEVICE HAVING A CNAND STRUCTURE AND BEING MONOLITHICALLY INTEGRATED ON SEMICONDUCTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
11/10/2009
|
Application #:
|
11401523
|
Filing Dt:
|
04/11/2006
|
Publication #:
|
|
Pub Dt:
|
01/25/2007
| | | | |
Title:
|
INTEGRATED ELECTRONIC DEVICE HAVING A LOW VOLTAGE ELECTRIC SUPPLY
|
|
|
Patent #:
|
|
Issue Dt:
|
07/07/2009
|
Application #:
|
11402018
|
Filing Dt:
|
04/10/2006
|
Publication #:
|
|
Pub Dt:
|
10/11/2007
| | | | |
Title:
|
METHODS OF FORMING A PLURALITY OF CAPACITORS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/21/2008
|
Application #:
|
11402535
|
Filing Dt:
|
04/12/2006
|
Publication #:
|
|
Pub Dt:
|
10/18/2007
| | | | |
Title:
|
MULTIPLE SELECT GATE ARCHITECTURE WITH SELECT GATES OF DIFFERENT LENGTHS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/21/2010
|
Application #:
|
11402659
|
Filing Dt:
|
04/11/2006
|
Publication #:
|
|
Pub Dt:
|
10/11/2007
| | | | |
Title:
|
METHODS OF FORMING SEMICONDUCTOR CONSTRUCTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/01/2008
|
Application #:
|
11403738
|
Filing Dt:
|
04/13/2006
|
Publication #:
|
|
Pub Dt:
|
08/24/2006
| | | | |
Title:
|
REDUCTION OF ADJACENT FLOATING GATE DATA PATTERN SENSITIVITY
|
|
|
Patent #:
|
|
Issue Dt:
|
06/10/2008
|
Application #:
|
11403780
|
Filing Dt:
|
04/13/2006
|
Publication #:
|
|
Pub Dt:
|
08/24/2006
| | | | |
Title:
|
REDUCTION OF ADJACENT FLOATING GATE DATA PATTERN SENSITIVITY
|
|
|
Patent #:
|
|
Issue Dt:
|
12/12/2006
|
Application #:
|
11403781
|
Filing Dt:
|
04/13/2006
|
Publication #:
|
|
Pub Dt:
|
09/07/2006
| | | | |
Title:
|
REDUCTION OF ADJACENT FLOATING GATE DATA PATTERN SENSITIVITY
|
|
|
Patent #:
|
|
Issue Dt:
|
12/29/2009
|
Application #:
|
11404209
|
Filing Dt:
|
04/13/2006
|
Publication #:
|
|
Pub Dt:
|
10/18/2007
| | | | |
Title:
|
DEVICES AND SYSTEMS INCLUDING THE BIT LINES AND BIT LINE CONTACTS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/15/2010
|
Application #:
|
11404306
|
Filing Dt:
|
04/14/2006
|
Publication #:
|
|
Pub Dt:
|
10/18/2007
| | | | |
Title:
|
METHOD OF PHOTORESIST STRIP FOR PLASMA DOPING PROCESS OF SEMICONDUCTOR MANUFACTURING
|
|
|
Patent #:
|
|
Issue Dt:
|
06/09/2009
|
Application #:
|
11404611
|
Filing Dt:
|
04/13/2006
|
Publication #:
|
|
Pub Dt:
|
10/05/2006
| | | | |
Title:
|
METHODS OF DEPOSITING MATERIALS OVER SUBSTRATES, AND METHODS OF FORMING LAYERS OVER SUBSTRATES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/21/2009
|
Application #:
|
11404785
|
Filing Dt:
|
04/17/2006
|
Publication #:
|
|
Pub Dt:
|
10/19/2006
| | | | |
Title:
|
MEMORY MODULE THAT IS CAPABLE OF CONTROLLING INPUT/OUTPUT IN ACCORDANCE WITH TYPE OF MEMORY CHIP
|
|
|
Patent #:
|
|
Issue Dt:
|
04/08/2008
|
Application #:
|
11405045
|
Filing Dt:
|
04/17/2006
|
Publication #:
|
|
Pub Dt:
|
08/17/2006
| | | | |
Title:
|
SUBSTRATE, SEMICONDUCTOR DIE, MULTICHIP MODULE, AND SYSTEM INCLUDING A VIA STRUCTURE COMPRISING A PLURALITY OF CONDUCTIVE ELEMENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/06/2012
|
Application #:
|
11405629
|
Filing Dt:
|
04/18/2006
|
Publication #:
|
|
Pub Dt:
|
10/18/2007
| | | | |
Title:
|
METHODS OF FILLING ISOLATION TRENCHES FOR SEMICONDUCTOR DEVICES AND RESULTING STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
08/10/2010
|
Application #:
|
11405637
|
Filing Dt:
|
04/18/2006
|
Publication #:
|
|
Pub Dt:
|
10/18/2007
| | | | |
Title:
|
METHOD AND APPARATUS PROVIDING HIGH DENSITY DATA STORAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/29/2008
|
Application #:
|
11405638
|
Filing Dt:
|
04/18/2006
|
Publication #:
|
|
Pub Dt:
|
08/24/2006
| | | | |
Title:
|
SEMICONDUCTOR PACKAGES AND METHODS FOR MAKING AND USING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
12/15/2009
|
Application #:
|
11405762
|
Filing Dt:
|
04/18/2006
|
Publication #:
|
|
Pub Dt:
|
10/18/2007
| | | | |
Title:
|
COUPLINGS WITHIN MEMORY DEVICES AND METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2009
|
Application #:
|
11406455
|
Filing Dt:
|
04/18/2006
|
Publication #:
|
|
Pub Dt:
|
08/24/2006
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURES AND MEMORY DEVICE CONSTRUCTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/11/2010
|
Application #:
|
11406594
|
Filing Dt:
|
04/19/2006
|
Publication #:
|
|
Pub Dt:
|
10/25/2007
| | | | |
Title:
|
NANOPARTICLE POSITIONING TECHNIQUE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/03/2010
|
Application #:
|
11406863
|
Filing Dt:
|
04/18/2006
|
Publication #:
|
|
Pub Dt:
|
09/07/2006
| | | | |
Title:
|
METHODS OF IMPLANTING DOPANT INTO CHANNEL REGIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/20/2009
|
Application #:
|
11407227
|
Filing Dt:
|
04/19/2006
|
Publication #:
|
|
Pub Dt:
|
10/25/2007
| | | | |
Title:
|
READ OPERATION FOR NAND MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
01/19/2010
|
Application #:
|
11407429
|
Filing Dt:
|
04/20/2006
|
Publication #:
|
|
Pub Dt:
|
09/28/2006
| | | | |
Title:
|
INTEGRATED CIRCUIT FABRICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
08/12/2008
|
Application #:
|
11407435
|
Filing Dt:
|
04/20/2006
|
Publication #:
|
|
Pub Dt:
|
08/24/2006
| | | | |
Title:
|
MICROFEATURE DEVICES AND METHODS FOR MANUFACTURING MICROFEATURE DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/14/2009
|
Application #:
|
11407560
|
Filing Dt:
|
04/19/2006
|
Publication #:
|
|
Pub Dt:
|
08/24/2006
| | | | |
Title:
|
MICROFEATURE SYSTEMS INCLUDING ADHERED MICROFEATURE WORKPIECES AND SUPPORT MEMBERS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/2014
|
Application #:
|
11408112
|
Filing Dt:
|
04/20/2006
|
Publication #:
|
|
Pub Dt:
|
12/14/2006
| | | | |
Title:
|
CMOS FABRICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
12/20/2011
|
Application #:
|
11408874
|
Filing Dt:
|
04/19/2006
|
Publication #:
|
|
Pub Dt:
|
09/07/2006
| | | | |
Title:
|
MEMORY DEVICES, TRANSISTORS, AND MEMORY CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/10/2008
|
Application #:
|
11409060
|
Filing Dt:
|
04/24/2006
|
Publication #:
|
|
Pub Dt:
|
11/16/2006
| | | | |
Title:
|
SYSTEMS AND METHODS FOR TESTING MICROFEATURE DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/02/2010
|
Application #:
|
11409350
|
Filing Dt:
|
04/21/2006
|
Publication #:
|
|
Pub Dt:
|
09/07/2006
| | | | |
Title:
|
APPARATUS FOR USE IN SEMICONDUCTOR WAFER PROCESSING FOR LATERALLY DISPLACING INDIVIDUAL SEMICONDUCTOR DEVICES AWAY FROM ONE ANOTHER
|
|
|
Patent #:
|
|
Issue Dt:
|
02/09/2010
|
Application #:
|
11409638
|
Filing Dt:
|
04/24/2006
|
Publication #:
|
|
Pub Dt:
|
10/25/2007
| | | | |
Title:
|
SEMICONDUCTOR COMPONENTS HAVING ENCAPSULATED THROUGH WIRE INTERCONNECTS (TWI)
|
|
|
Patent #:
|
|
Issue Dt:
|
12/02/2008
|
Application #:
|
11409729
|
Filing Dt:
|
04/24/2006
|
Publication #:
|
|
Pub Dt:
|
10/26/2006
| | | | |
Title:
|
OUTPUT DATA COMPRESSION SCHEME USING TRI-STATE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/08/2009
|
Application #:
|
11410100
|
Filing Dt:
|
04/25/2006
|
Publication #:
|
|
Pub Dt:
|
08/31/2006
| | | | |
Title:
|
METHOD OF CONTROLLING IMAGE QUALITY OF AN INTEGRATED CMOS IMAGER AND MICROCONTROLLER
|
|
|
Patent #:
|
|
Issue Dt:
|
10/09/2007
|
Application #:
|
11410213
|
Filing Dt:
|
04/25/2006
|
Publication #:
|
|
Pub Dt:
|
08/24/2006
| | | | |
Title:
|
APPARATUS AND METHOD FOR CONDITIONING POLISHING SURFACE, AND POLISHING APPARATUS AND METHOD OF OPERATION
|
|
|
Patent #:
|
|
Issue Dt:
|
08/23/2011
|
Application #:
|
11410588
|
Filing Dt:
|
04/24/2006
|
Publication #:
|
|
Pub Dt:
|
11/08/2007
| | | | |
Title:
|
MASKING TECHNIQUES AND TEMPLATES FOR DENSE SEMICONDUCTOR FABRICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
11/07/2006
|
Application #:
|
11410591
|
Filing Dt:
|
04/25/2006
|
Publication #:
|
|
Pub Dt:
|
09/07/2006
| | | | |
Title:
|
METHOD TO REALIZE FAST SILICON-ON-INSULATOR (SOI) OPTICAL DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/07/2006
|
Application #:
|
11411059
|
Filing Dt:
|
04/25/2006
|
Publication #:
|
|
Pub Dt:
|
09/07/2006
| | | | |
Title:
|
METHOD TO REALIZE FAST SILICON-ON-INSULATOR (SOI) OPTICAL DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/07/2010
|
Application #:
|
11411265
|
Filing Dt:
|
04/26/2006
|
Publication #:
|
|
Pub Dt:
|
08/31/2006
| | | | |
Title:
|
IMAGE SENSOR PACKAGES AND FRAME STRUCTURE THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
09/11/2007
|
Application #:
|
11411286
|
Filing Dt:
|
04/25/2006
|
Publication #:
|
|
Pub Dt:
|
08/24/2006
| | | | |
Title:
|
LOW SUPPLY VOLTAGE BIAS CIRCUIT, SEMICONDUCTOR DEVICE, WAFER AND SYSTEM INCLUDING SAME, AND METHOD OF GENERATING A BIAS REFERENCE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/05/2009
|
Application #:
|
11411287
|
Filing Dt:
|
04/25/2006
|
Publication #:
|
|
Pub Dt:
|
08/31/2006
| | | | |
Title:
|
METHODS FOR ASSEMBLING SEMICONDUCTOR DEVICES AND INTERPOSERS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/25/2011
|
Application #:
|
11411311
|
Filing Dt:
|
04/26/2006
|
Publication #:
|
|
Pub Dt:
|
11/01/2007
| | | | |
Title:
|
SELF-ALIGNED BIOPOLAR JUNCTION TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/07/2008
|
Application #:
|
11411376
|
Filing Dt:
|
04/26/2006
|
Publication #:
|
|
Pub Dt:
|
11/01/2007
| | | | |
Title:
|
MULTIPLE SELECT GATES WITH NON-VOLATILE MEMORY CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/10/2009
|
Application #:
|
11411401
|
Filing Dt:
|
04/25/2006
|
Publication #:
|
|
Pub Dt:
|
10/25/2007
| | | | |
Title:
|
PROCESS FOR IMPROVING CRITICAL DIMENSION UNIFORMITY OF INTEGRATED CIRCUIT ARRAYS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/2008
|
Application #:
|
11411490
|
Filing Dt:
|
04/25/2006
|
Publication #:
|
|
Pub Dt:
|
10/25/2007
| | | | |
Title:
|
METHODS OF FORMING SEMICONDUCTOR CONSTRUCTIONS
|
|