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Reel/Frame:	047797/0854			Pages:	47
		Recorded:	10/16/2018
Attorney Dkt #:	CORRECTIVE ASSIGNMENT
Conveyance:	CORRECTIVE ASSIGNMENT TO CORRECT THE FOLLOWING NUMBERS 6272046,7277824,7282374,7286384,7299106,7337032,7460920,7519447 PREVIOUSLY RECORDED ON REEL 039676 FRAME 0237. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST.

Total properties: 408
Page 1 of 5
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Patent #:	5768192	Issue Dt:	06/16/1998	Application #:	08681430	Filing Dt:	07/23/1996
Title:	NON-VOLATILE SEMICONDUCTOR MEMORY CELL UTILIZING ASYMMETRICAL CHARGE TRAPPING

Patent #:	5966603	Issue Dt:	10/12/1999	Application #:	08873384	Filing Dt:	06/11/1997
Title:	NROM FABRICATION METHOD WITH A PERIPHERY PORTION

Patent #:	6232663	Issue Dt:	05/15/2001	Application #:	08904630	Filing Dt:	08/01/1997
Title:	SEMICONDUCTOR DEVICE HAVING INTERLAYER INSULATOR AND METHOD FOR FABRICATING THEREOF

Patent #:	6768165	Issue Dt:	07/27/2004	Application #:	08905286	Filing Dt:	08/01/1997
Title:	TWO BIT NON-VOLATILE ELECTRICALLY ERASABLE AND PROGRAMMABLE SEMICONDUCTOR MEMORY CELL UTILIZING ASYMMETRICAL CHARGE TRAPPING

Patent #:	5963465	Issue Dt:	10/05/1999	Application #:	08989690	Filing Dt:	12/12/1997
Title:	SYMMETRIC SEGMENTED MEMORY ARRY ARCHITECTURE

Patent #:	6177312	Issue Dt:	01/23/2001	Application #:	09048459	Filing Dt:	03/26/1998
Title:	METHOD FOR REMOVING CONTAMINATE NITROGEN FROM THE PERIPHERAL GATE REGION OF A NON-VOLATILE MEMORY DEVICE DURING PRODUCTION OF SUCH DEVICE

Patent #:	6030871	Issue Dt:	02/29/2000	Application #:	09072462	Filing Dt:	05/05/1998
Title:	PROCESS FOR PRODUCING TWO BIR ROM CELL UTILIZING ANGLED IMPLANT

Patent #:	6215148	Issue Dt:	04/10/2001	Application #:	09082280	Filing Dt:	05/20/1998
Title:	NROM CELL WITH IMPROVED PROGRAMMING, ERASING AND CYCLING

Patent #:	6187640	Issue Dt:	02/13/2001	Application #:	09193252	Filing Dt:	11/17/1998
Title:	SEMICONDUCTOR DEVICE MANUFACTURING METHOD INCLUDING VARIOUS OXIDATION STEPS WITH DIFFERENT CONCENTRATION OF CHLORINE TO FORM A FIELD OXIDE

Patent #:	6128226	Issue Dt:	10/03/2000	Application #:	09244439	Filing Dt:	02/04/1999
Title:	METHOD AND APPARATUS FOR OPERATING WITH A CLOSE TO GROUND SIGNAL

Patent #:	6078539	Issue Dt:	06/20/2000	Application #:	09244445	Filing Dt:	02/04/1999
Title:	METHOD AND DEVICE FOR INITIATING A MEMORY ARRAY DURING POWER UP

Patent #:	6233180	Issue Dt:	05/15/2001	Application #:	09244454	Filing Dt:	02/04/1999
Title:	DEVICE FOR DETERMINING THE VALIDITY OF WORD-LINE CONDITIONS AND FOR DELAYING DATA JENSING OPERATION

Patent #:	6133095	Issue Dt:	10/17/2000	Application #:	09245811	Filing Dt:	02/04/1999
Title:	METHOD FOR CREATING DIFFUSION AREAS FOR SOURCES AND DRAINS WITHOUT AN ETCH STEP

Patent #:	6011725	Issue Dt:	01/04/2000	Application #:	09246183	Filing Dt:	02/04/1999
Title:	TWO BIT NON-VOLATILE ELECTRICALLY ERASABLE AND PROGRAMMABLE SEMICONDUCTOR MEMORY CELL UTILIZING ASYMMETRICAL CHARGE TRAPPING

Patent #:	6134156	Issue Dt:	10/17/2000	Application #:	09246776	Filing Dt:	02/04/1999
Title:	METHOD FOR INITIATING A RETRIEVAL PROCEDURE IN VIRTUAL GROUND ARRAYS

Patent #:	6118267	Issue Dt:	09/12/2000	Application #:	09246880	Filing Dt:	02/04/1999
Title:	APPARATUS FOR SWITCHING A REFERENCE VOLTAGE BETWEEN HIGH AND LOW IMPEDANCE STATES

Patent #:	6337502	Issue Dt:	01/08/2002	Application #:	09336666	Filing Dt:	06/18/1999
Title:	METHOD AND CIRCUIT FOR MINIMIZING THE CHARGING EFFECT DURING MANUFACTURE OF SEMICONDUCTOR DEVICES

Patent #:	6285574	Issue Dt:	09/04/2001	Application #:	09348720	Filing Dt:	07/06/1999
Title:	SYMMETRIC SEGMENTED MEMORY ARRAY ARCHITECTURE

Patent #:	6297096	Issue Dt:	10/02/2001	Application #:	09365369	Filing Dt:	07/30/1999
Title:	NROM FABRICATION METHOD

Patent #:	6348711	Issue Dt:	02/19/2002	Application #:	09413408	Filing Dt:	10/06/1999
Title:	NROM CELL WITH SELF-ALIGNED PROGRAMMING AND ERASURE AREAS

Patent #:	6362049	Issue Dt:	03/26/2002	Application #:	09435213	Filing Dt:	11/05/1999
Title:	High yield performacne semiconductor process flow for nand flash memory products

Patent #:	6201282	Issue Dt:	03/13/2001	Application #:	09471823	Filing Dt:	12/23/1999
Title:	TWO BIT ROM CELL AND PROCESS FOR PRODUCING SAME

Patent #:	6246610	Issue Dt:	06/12/2001	Application #:	09511652	Filing Dt:	02/22/2000
Title:	Symmetrical program and erase scheme to improve erase time degradation in NAND devices

Patent #:	6429063	Issue Dt:	08/06/2002	Application #:	09519745	Filing Dt:	03/06/2000
Title:	NROM CELL WITH GENERALLY DECOUPLED PRIMARY AND SECONDARY INJECTION

Patent #:	6727143	Issue Dt:	04/27/2004	Application #:	09533619	Filing Dt:	03/22/2000
Title:	METHOD AND SYSTEM FOR REDUCING CHARGE GAIN AND CHARGE LOSS WHEN USING AN ARC LAYER IN INTERLAYER DIELECTRIC FORMATION

Patent #:	6633499	Issue Dt:	10/14/2003	Application #:	09536125	Filing Dt:	03/28/2000
Title:	METHOD FOR REDUCING VOLTAGE DROPS IN SYMMETRIC ARRAY ARCHITECTURES

Patent #:	6430077	Issue Dt:	08/06/2002	Application #:	09536126	Filing Dt:	03/28/2000
Title:	METHOD FOR REGULATING READ VOLTAGE LEVEL AT THE DRAIN OF A CELL IN A SYMMETRIC ARRAY

Patent #:	6285599	Issue Dt:	09/04/2001	Application #:	09562747	Filing Dt:	05/02/2000
Title:	Decoded source lines to tighten erase Vt distribution

Patent #:	6365945	Issue Dt:	04/02/2002	Application #:	09563024	Filing Dt:	05/02/2000
Title:	Submicron semiconductor device having a self-aligned channel stop region and a method for fabricating the semiconductor device using a trim and etch

Patent #:	6396741	Issue Dt:	05/28/2002	Application #:	09563923	Filing Dt:	05/04/2000
Title:	A METHOD OF PROGRAMMING NONVOLATILE MEMORY CELLS".

Patent #:	6292394	Issue Dt:	09/18/2001	Application #:	09606205	Filing Dt:	06/29/2000
Title:	Method for programming of a semiconductor memory cell

Patent #:	6579781	Issue Dt:	06/17/2003	Application #:	09619231	Filing Dt:	07/19/2000
Title:	ELIMINATION OF N+ CONTACT IMPLANT FROM FLASH TECHNOLOGIES BY REPLACEMENT WITH STANDARD DOUBLE-DIFFUSED AND N+ IMPLANTS

Patent #:	6579778	Issue Dt:	06/17/2003	Application #:	09634991	Filing Dt:	08/08/2000
Title:	SOURCE BUS FORMATION FOR A FLASH MEMORY USING SILICIDE

Patent #:	6567289	Issue Dt:	05/20/2003	Application #:	09644359	Filing Dt:	08/23/2000
Title:	PHYSICAL MEMORY LAYOUT WITH VARIOUS SIZED MEMORY SECTORS

Patent #:	6335874	Issue Dt:	01/01/2002	Application #:	09659240	Filing Dt:	09/11/2000
Title:	Symmetric segmented memory array architecture

Patent #:	6529410	Issue Dt:	03/04/2003	Application #:	09665916	Filing Dt:	09/20/2000
Title:	NAND ARRAY STRUCTURE AND METHOD WITH BURIED LAYER

Patent #:	6477083	Issue Dt:	11/05/2002	Application #:	09686685	Filing Dt:	10/11/2000
Title:	SELECT TRANSISTOR ARCHITECTURE FOR A VIRTUAL GROUND NON-VOLATILE MEMORY CELL ARRAY

Patent #:	6297993	Issue Dt:	10/02/2001	Application #:	09712382	Filing Dt:	11/13/2000
Title:	Acceleration voltage implementation for a high density flash memory device

Patent #:	6307787	Issue Dt:	10/23/2001	Application #:	09724669	Filing Dt:	11/28/2000
Title:	Burst read incorporating output based redundancy

Patent #:	6579769	Issue Dt:	06/17/2003	Application #:	09726384	Filing Dt:	12/01/2000
Publication #:	US20010000247	Pub Dt:	04/12/2001
Title:	SEMICONDUCTOR DEVICE MANUFACTURING METHOD

Patent #:	6633496	Issue Dt:	10/14/2003	Application #:	09727781	Filing Dt:	12/04/2000
Publication #:	US20010046150	Pub Dt:	11/29/2001
Title:	SYMMETRIC ARCHITECTURE FOR MEMORY CELLS HAVING WIDELY SPREAD METAL BIT LINES

Patent #:	6928001	Issue Dt:	08/09/2005	Application #:	09730586	Filing Dt:	12/07/2000
Publication #:	US20040222437	Pub Dt:	11/11/2004
Title:	PROGRAMMING AND ERASING METHODS FOR AN NON-VOLATILE MEMORY CELL

Patent #:	6614692	Issue Dt:	09/02/2003	Application #:	09761818	Filing Dt:	01/18/2001
Publication #:	US20020132436	Pub Dt:	09/19/2002
Title:	EEPROM ARRAY AND METHOD FOR OPERATION THEREOF

Patent #:	6627555	Issue Dt:	09/30/2003	Application #:	09777234	Filing Dt:	02/05/2001
Publication #:	US20010026970	Pub Dt:	10/04/2001
Title:	METHOD AND CIRCUIT FOR MINIMIZING THE CHARGING EFFECT DURING MANUFACTURE OF SEMICONDUCTOR DEVICES

Patent #:	6477084	Issue Dt:	11/05/2002	Application #:	09778502	Filing Dt:	02/07/2001
Publication #:	US20010004332	Pub Dt:	06/21/2001
Title:	NROM CELL WITH IMPROVED PROGRAMMING, ERASING AND CYCLING

Patent #:	6573140	Issue Dt:	06/03/2003	Application #:	09810155	Filing Dt:	03/16/2001
Title:	PROCESS FOR MAKING A DUAL BIT MEMORY DEVICE WITH ISOLATED POLYSILICON FLOATING GATES

Patent #:	6385093	Issue Dt:	05/07/2002	Application #:	09822995	Filing Dt:	03/30/2001
Title:	I/O partitioning system and methodology to reduce band-to-band tunneling current during erase

Patent #:	6677805	Issue Dt:	01/13/2004	Application #:	09826351	Filing Dt:	04/05/2001
Publication #:	US20020145464	Pub Dt:	10/10/2002
Title:	CHARGE PUMP STAGE WITH BODY EFFECT MINIMIZATION

Patent #:	6665769	Issue Dt:	12/16/2003	Application #:	09827510	Filing Dt:	04/05/2001
Publication #:	US20020194422	Pub Dt:	12/19/2002
Title:	METHOD AND APPARATUS FOR DYNAMICALLY MASKING AN N-BIT MEMORY ARRAY HAVING INDIVIDUALLY PROGRAMMABLE CELLS

Patent #:	6448750	Issue Dt:	09/10/2002	Application #:	09827755	Filing Dt:	04/05/2001
Title:	VOLTAGE REGULATOR FOR NON-VOLATILE MEMORY WITH LARGE POWER SUPPLY REJECTION RATION AND MINIMAL CURRENT DRAIN

Patent #:	6535434	Issue Dt:	03/18/2003	Application #:	09827756	Filing Dt:	04/05/2001
Publication #:	US20020145918	Pub Dt:	10/10/2002
Title:	ARCHITECTURE AND SCHEME FOR A NON-STROBED READ SEQUENCE

Patent #:	6584017	Issue Dt:	06/24/2003	Application #:	09827757	Filing Dt:	04/05/2001
Publication #:	US20020145911	Pub Dt:	10/10/2002
Title:	METHOD FOR PROGRAMMING A REFERENCE CELL

Patent #:	6636440	Issue Dt:	10/21/2003	Application #:	09841052	Filing Dt:	04/25/2001
Publication #:	US20020191465	Pub Dt:	12/19/2002
Title:	METHOD FOR OPERATION OF AN EEPROM ARRAY, INCLUDING REFRESH THEREOF

Patent #:	6664588	Issue Dt:	12/16/2003	Application #:	09879915	Filing Dt:	06/14/2001
Publication #:	US20020000606	Pub Dt:	01/03/2002
Title:	NROM CELL WITH SELF-ALIGNED PROGRAMMING AND ERASURE AREAS

Patent #:	6573151	Issue Dt:	06/03/2003	Application #:	09884204	Filing Dt:	06/19/2001
Title:	METHOD OF FORMING ZERO MARKS

Patent #:	7125763	Issue Dt:	10/24/2006	Application #:	09885426	Filing Dt:	06/19/2001
Title:	SILICIDED BURIED BITLINE PROCESS FOR A NON-VOLATILE MEMORY CELL

Patent #:	6643178	Issue Dt:	11/04/2003	Application #:	09920249	Filing Dt:	07/31/2001
Publication #:	US20030039147	Pub Dt:	02/27/2003
Title:	SYSTEM FOR SOURCE SIDE SENSING

Patent #:	6566699	Issue Dt:	05/20/2003	Application #:	09939570	Filing Dt:	08/28/2001
Publication #:	US20020064911	Pub Dt:	05/30/2002
Title:	NON-VOLATILE ELECTRICALLY ERASABLE AND PROGRAMMABLE SEMICONDUCTOR MEMORY CELL UTILIZING ASYMMETRICAL CHARGE TRAPPING

Patent #:	6803279	Issue Dt:	10/12/2004	Application #:	09966754	Filing Dt:	10/01/2001
Publication #:	US20020052081	Pub Dt:	05/02/2002
Title:	NROM FABRICATION METHOD

Patent #:	6566194	Issue Dt:	05/20/2003	Application #:	09968465	Filing Dt:	10/01/2001
Publication #:	US20030085417	Pub Dt:	05/08/2003
Title:	SALICIDED GATE FOR VIRTUAL GROUND ARRAYS

Patent #:	6643181	Issue Dt:	11/04/2003	Application #:	09983510	Filing Dt:	10/24/2001
Publication #:	US20030076710	Pub Dt:	04/24/2003
Title:	METHOD FOR ERASING A MEMORY CELL

Patent #:	6791396	Issue Dt:	09/14/2004	Application #:	09983511	Filing Dt:	10/24/2001
Publication #:	US20030076159	Pub Dt:	04/24/2003
Title:	STACK ELEMENT CIRCUIT

Patent #:	7098107	Issue Dt:	08/29/2006	Application #:	09988122	Filing Dt:	11/19/2001
Publication #:	US20030096475	Pub Dt:	05/22/2003
Title:	PROTECTIVE LAYER IN MEMORY DEVICE AND METHOD THEREFOR

Patent #:	6583007	Issue Dt:	06/24/2003	Application #:	10023278	Filing Dt:	12/20/2001
Publication #:	US20030119254	Pub Dt:	06/26/2003
Title:	REDUCING SECONDARY INJECTION EFFECTS

Patent #:	6885585	Issue Dt:	04/26/2005	Application #:	10023469	Filing Dt:	12/20/2001
Publication #:	US20030117861	Pub Dt:	06/26/2003
Title:	NROM NOR ARRAY

Patent #:	6567303	Issue Dt:	05/20/2003	Application #:	10050483	Filing Dt:	01/16/2002
Title:	CHARGE INJECTION

Patent #:	6574139	Issue Dt:	06/03/2003	Application #:	10052484	Filing Dt:	01/18/2002
Publication #:	US20030081458	Pub Dt:	05/01/2003
Title:	METHOD AND DEVICE FOR READING DUAL BIT MEMORY CELLS USING MULTIPLE REFERENCE CELLS WITH TWO SIDE READ

Patent #:	6704217	Issue Dt:	03/09/2004	Application #:	10059075	Filing Dt:	01/30/2002
Publication #:	US20020196698	Pub Dt:	12/26/2002
Title:	SYMMETRIC SEGMENTED MEMORY ARRAY ARCHITECTURE

Patent #:	6917541	Issue Dt:	07/12/2005	Application #:	10060185	Filing Dt:	02/01/2002
Publication #:	US20030043623	Pub Dt:	03/06/2003
Title:	NONVOLATILE SEMICONDUCTOR MEMORY DEVICE

Patent #:	6574149	Issue Dt:	06/03/2003	Application #:	10097924	Filing Dt:	03/15/2002
Publication #:	US20020093851	Pub Dt:	07/18/2002
Title:	SEMICONDUCTOR MEMORY AND ITS USAGE

Patent #:	6649972	Issue Dt:	11/18/2003	Application #:	10122078	Filing Dt:	04/15/2002
Publication #:	US20030011020	Pub Dt:	01/16/2003
Title:	TWO BIT NON-VOLATILE ELECTRICALLY ERASABLE AND PROGRAMMABLE SEMICONDUCTOR MEMORY CELL UTILIZING ASYMMETRICAL CHARGE TRAPPING

Patent #:	6855977	Issue Dt:	02/15/2005	Application #:	10139745	Filing Dt:	05/07/2002
Publication #:	US20020163828	Pub Dt:	11/07/2002
Title:	MEMORY DEVICE WITH A SELF-ASSEMBLED POLYMER FILM AND METHOD OF MAKING THE SAME

Patent #:	7518908	Issue Dt:	04/14/2009	Application #:	10155215	Filing Dt:	05/28/2002
Publication #:	US20030039153	Pub Dt:	02/27/2003
Title:	EEPROM ARRAY AND METHOD FOR OPERATION THEREOF

Patent #:	6937521	Issue Dt:	08/30/2005	Application #:	10155216	Filing Dt:	05/28/2002
Publication #:	US20030002345	Pub Dt:	01/02/2003
Title:	PROGRAMMING AND ERASING METHODS FOR A NON -VOLATILE MEMORY CELL

Patent #:	6829172	Issue Dt:	12/07/2004	Application #:	10155217	Filing Dt:	05/28/2002
Publication #:	US20030072192	Pub Dt:	04/17/2003
Title:	PROGRAMMING OF NONVOLATILE MEMORY CELLS

Patent #:	6570211	Issue Dt:	05/27/2003	Application #:	10180673	Filing Dt:	06/26/2002
Title:	2BIT/CELL ARCHITECTURE FOR FLOATING GATE FLASH MEMORY PRODUCT AND ASSOCIATED METHOD

Patent #:	6828625	Issue Dt:	12/07/2004	Application #:	10189533	Filing Dt:	07/08/2002
Publication #:	US20030096476	Pub Dt:	05/22/2003
Title:	PROTECTIVE LAYER IN MEMORY DEVICE AND METHOD THEREFOR

Patent #:	6917544	Issue Dt:	07/12/2005	Application #:	10191451	Filing Dt:	07/10/2002
Publication #:	US20040008541	Pub Dt:	01/15/2004
Title:	MULTIPLE USE MEMORY CHIP

Patent #:	6826107	Issue Dt:	11/30/2004	Application #:	10209644	Filing Dt:	08/01/2002
Publication #:	US20040022113	Pub Dt:	02/05/2004
Title:	HIGH VOLTAGE INSERTION IN FLASH MEMORY CARDS

Patent #:	6781897	Issue Dt:	08/24/2004	Application #:	10209645	Filing Dt:	08/01/2002
Publication #:	US20040022092	Pub Dt:	02/05/2004
Title:	DEFECTS DETECTION

Patent #:	6928527	Issue Dt:	08/09/2005	Application #:	10211234	Filing Dt:	08/05/2002
Publication #:	US20030145188	Pub Dt:	07/31/2003
Title:	LOOK AHEAD METHODS AND APPARATUS

Patent #:	7062619	Issue Dt:	06/13/2006	Application #:	10211235	Filing Dt:	08/05/2002
Publication #:	US20030145176	Pub Dt:	07/31/2003
Title:	MASS STORAGE DEVICE ARCHITECTURE AND OPERATION

Patent #:	6700818	Issue Dt:	03/02/2004	Application #:	10211248	Filing Dt:	08/05/2002
Publication #:	US20030156456	Pub Dt:	08/21/2003
Title:	METHOD FOR OPERATING A MEMORY DEVICE

Patent #:	6975536	Issue Dt:	12/13/2005	Application #:	10211249	Filing Dt:	08/05/2002
Publication #:	US20030142544	Pub Dt:	07/31/2003
Title:	MASS STORAGE ARRAY AND METHODS FOR OPERATION THEREOF

Patent #:	6768682	Issue Dt:	07/27/2004	Application #:	10259761	Filing Dt:	09/30/2002
Publication #:	US20030107919	Pub Dt:	06/12/2003
Title:	NONVOLATILE SEMICONDUCTOR MEMORY AND METHOD FOR CONTROLLING PROGRAMMING VOLTAGE OF NONVOLATILE SEMICONDUCTOR MEMORY

Patent #:	6847346	Issue Dt:	01/25/2005	Application #:	10278883	Filing Dt:	10/24/2002
Publication #:	US20030103390	Pub Dt:	06/05/2003
Title:	SEMICONDUCTOR DEVICE EQUIPPED WITH TRANSFER CIRCUIT FOR CASCADE CONNECTION

Patent #:	6794248	Issue Dt:	09/21/2004	Application #:	10279981	Filing Dt:	10/25/2002
Publication #:	US20030162354	Pub Dt:	08/28/2003
Title:	METHOD OF FABRICATING SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE DRIVER

Patent #:	7159124	Issue Dt:	01/02/2007	Application #:	10298512	Filing Dt:	11/19/2002
Publication #:	US20030140206	Pub Dt:	07/24/2003
Title:	NON-VOLATILE SEMICONDUCTOR MEMORY WITH A FUNCTION FOR PREVENTING UNAUTHORIZED READING

Patent #:	7148739	Issue Dt:	12/12/2006	Application #:	10322491	Filing Dt:	12/19/2002
Publication #:	US20040119525	Pub Dt:	06/24/2004
Title:	CHARGE PUMP ELEMENT WITH BODY EFFECT CANCELLATION FOR EARLY CHARGE PUMP STAGES

Patent #:	6842383	Issue Dt:	01/11/2005	Application #:	10354050	Filing Dt:	01/30/2003
Publication #:	US20040151034	Pub Dt:	08/05/2004
Title:	METHOD AND CIRCUIT FOR OPERATING A MEMORY CELL USING A SINGLE CHARGE PUMP

Patent #:	6967896	Issue Dt:	11/22/2005	Application #:	10354188	Filing Dt:	01/30/2003
Publication #:	US20040153620	Pub Dt:	08/05/2004
Title:	ADDRESS SCRAMBLE

Patent #:	6975541	Issue Dt:	12/13/2005	Application #:	10394254	Filing Dt:	03/24/2003
Publication #:	US20040190341	Pub Dt:	09/30/2004
Title:	ALTERNATING APPLICATION OF PULSES ON TWO SIDES OF A CELL

Patent #:	6885244	Issue Dt:	04/26/2005	Application #:	10394255	Filing Dt:	03/24/2003
Publication #:	US20040189385	Pub Dt:	09/30/2004
Title:	OPERATIONAL AMPLIFIER WITH FAST RISE TIME

Patent #:	6803299	Issue Dt:	10/12/2004	Application #:	10412317	Filing Dt:	04/14/2003
Publication #:	US20030201477	Pub Dt:	10/30/2003
Title:	NON-VOLATILE ELECTRICALLY ERASABLE AND PROGRAMMABLE SEMICONDUCTOR MEMORY CELL UTILIZING ASYMMETRICAL CHARGE TRAPPING

Patent #:	6858481	Issue Dt:	02/22/2005	Application #:	10413818	Filing Dt:	04/15/2003
Publication #:	US20030173612	Pub Dt:	09/18/2003
Title:	MEMORY DEVICE WITH ACTIVE AND PASSIVE LAYERS

Patent #:	6768157	Issue Dt:	07/27/2004	Application #:	10413829	Filing Dt:	04/15/2003
Publication #:	US20030178667	Pub Dt:	09/25/2003
Title:	MEMORY DEVICE

Patent #:	6804151	Issue Dt:	10/12/2004	Application #:	10437390	Filing Dt:	05/14/2003
Publication #:	US20030214844	Pub Dt:	11/20/2003
Title:	NONVOLATILE SEMICONDUCTOR MEMORY DEVICE OF VIRTUAL-GROUND MEMORY ARRAY WITH RELIABLE DATA READING

Patent #:	6788580	Issue Dt:	09/07/2004	Application #:	10454630	Filing Dt:	06/05/2003
Publication #:	US20030206435	Pub Dt:	11/06/2003
Title:	NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND DATA ERASING METHOD

Patent #:	7064983	Issue Dt:	06/20/2006	Application #:	10454820	Filing Dt:	06/05/2003
Publication #:	US20040081010	Pub Dt:	04/29/2004
Title:	METHOD FOR PROGRAMMING A REFERENCE CELL

100

Patent #:	6906966	Issue Dt:	06/14/2005	Application #:	10461437	Filing Dt:	06/16/2003
Publication #:	US20040252555	Pub Dt:	12/16/2004
Title:	FAST DISCHARGE FOR PROGRAM AND VERIFICATION

Assignor

CYPRESS SEMICONDUCTOR CORPORATION

Exec Dt:

12/29/2017

Assignee

MORGAN STANLEY SENIOR FUNDING

1585 BROADWAY STREET

NEW YORK, NEW YORK 10036

Correspondence name and address
	CYPRESS SEMICONDUCTOR CORPORATION
	198 CHAMPION COURT
	SAN JOSE, CA 95134

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