Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
|
| Reel/Frame: | 048002/0433 | |
| Pages: | 3 |
| | Recorded: | 12/03/2018 | | |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
|
|
Total properties:
1
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/31/2019
|
Application #:
|
16186882
|
Filing Dt:
|
11/12/2018
|
|
Title:
|
Test Circuitry and Techniques for Logic Tiles of FPGA
|
|
|
Assignee
|
|
|
|
|
| 2465 LATHAM STREET |
| SUITE 100 |
| MOUNTAIN VIEW, CALIFORNIA 94040 |
|
|
Correspondence name and address
|
| |
NEIL A. STEINBERG
|
| |
5335 WISCONSIN AVE, NW
|
| |
SUITE 440
|
| |
WASHINGTON, D.C. 20015
|
Search Results as of:
05/11/2024 10:24 PM
If you have any comments or questions concerning the data displayed,
contact
PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified:
August 25, 2017 v.2.6
|
