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11/21/2000
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09057271
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04/08/1998
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Title:
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METHOD AND CIRCUIT FOR DETECTING OVERFLOW IN OPERAND MULTIPLICATION
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08/22/2000
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09102381
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06/22/1998
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Title:
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FABRIC CUTTING WEIGHT WITH INTEGRAL SPIKES
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03/06/2001
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09121216
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07/23/1998
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Title:
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METHOD FOR DETERMINING THE HOT CARRIER LIFETIME OF A TRANSISTOR
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09/10/2002
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09121922
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07/25/1998
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SYNTHESIS OF COMBINATORIAL LIBRARIES OF COMPOUNDS REMINISCENT OF NATURAL PRODUCTS
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11/12/2002
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09161258
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09/25/1998
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PLASTIC LENS SYSTEMS AND METHODS
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03/06/2001
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09164823
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10/01/1998
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Title:
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METHOD FOR PROVIDING COOPERATIVE RUN-TO-RUN CONTROL FOR MULTI-PRODUCT AND MULTI-PROCESS SEMICONDUCTOR FABRICATION
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07/10/2001
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09164881
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10/01/1998
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Title:
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INTERFEROMETER METHOD FOR PROVIDING STABILITY OF A LASER
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01/15/2002
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09165609
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10/02/1998
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Title:
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USING PADDED INSTRUCTIONS IN A BLOCK-ORIENTED CACHE
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08/22/2000
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09165783
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10/02/1998
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Title:
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METHOD TO MANUFACTURE MULTIPLE DAMASCENE BY UTILIZING ETCH SELECTIVITY
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12/05/2000
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09165957
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10/02/1998
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Title:
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COPPER ETCHING COMPOSITIONS, PROCESSES AND PRODUCTS DERIVED THEREFROM
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12/05/2000
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09166440
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10/05/1998
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Title:
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CIRCUIT AND METHOD FOR REDUCING DATA DEPENDENCIES BETWEEN INSTRUCTIONS
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08/28/2001
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09167622
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10/06/1998
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Title:
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DEVICE AND METHOD FOR ETCHING NITRIDE SPACERS FORMED UPON AN INTEGRATED CIRCUIT GATE CONDUCTOR
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11/27/2001
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09168456
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10/08/1998
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Title:
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MICROMECHANICAL DISPLAYS AND FABRICATION METHOD
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Issue Dt:
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09/12/2000
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09169281
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10/08/1998
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Title:
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METHOD FOR IMPLANTING SEMICONDUCTOR CONDUCTIVE LAYERS
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11/19/2002
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09169347
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10/09/1998
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Title:
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HIERARCHICAL TEXTURE CACHE
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12/05/2000
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09170335
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10/13/1998
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POWER SUPPLY INDEPENDENT TEMPERATURE SENSOR
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11/28/2000
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09170619
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10/13/1998
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Title:
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METHOD OF FABRICATING ULTRA SHALLOW JUNCTION CMOS TRANSISTORS WITH NITRIDE DISPOSABLE SPACER
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11/07/2000
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09172088
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10/14/1998
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Title:
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SHALLOW TRENCH ISOLATION FORMATION WITH SPACER-ASSISTED ION IMPLANTATION
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03/04/2003
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09172732
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10/13/1998
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Title:
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ARTICLE EXHIBITING ENHANCED ADHESION BETWEEN A DIELECTRIC SUBSTRATE AND HEAT SPREADER AND METHOD
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04/17/2001
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09172759
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10/15/1998
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Title:
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SYSTEM FOR GATED DETECTION OF OPTICAL PULSES CONTAINING A SMALL NUMBER OF PHOTONS USING AN AVALANCHE PHTOTDIODE
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05/08/2001
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09172982
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10/14/1998
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Title:
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METHOD OF MAKING DUAL DAMASCENE CONDUCTIVE INTERCONNECTIONS AND INTEGRATED CIRCUIT DEVICE COMPRISING SAME
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02/13/2001
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09173015
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10/15/1998
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Title:
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INTEGRATION OF ISOLATION WITH EPITAXIAL GROWTH REGIONS FOR ENHANCED DEVICE FORMATION
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Issue Dt:
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07/04/2000
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09173233
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10/15/1998
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Title:
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TRANSISTOR HAVING A METAL SILICIDE SELF-ALIGNED TO THE GATE
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Patent #:
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Issue Dt:
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08/15/2000
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09174037
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Filing Dt:
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10/16/1998
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Title:
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MECHANISM FOR MINIMIZING OVERHEAD USAGE OF A HOST SYSTEM BY POLLING FOR SUBSEQUENT INTERRUPTS AFTER SERVICE OF A PRIOR INTERRUPT
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Patent #:
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Issue Dt:
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10/16/2001
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09174900
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10/19/1998
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Title:
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METHOD AND SYSTEM FOR DATA TRANSMISSION IN ACCELERATED GRAPHICS PORT SYSTEMS
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07/03/2001
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09175652
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10/20/1998
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Title:
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SEMICONDUCTOR DEVICE HAVING SILICIDE LAYERS FORMED USING A COLLIMATED METAL LAYER
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Issue Dt:
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07/18/2000
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09175709
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10/20/1998
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Title:
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MECHANISM FOR SYNCHRONIZING SERVICE OF INTERRUPTS BY A PLURALITY OF DATA PROCESSORS
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Patent #:
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Issue Dt:
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12/04/2001
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09176737
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Filing Dt:
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10/21/1998
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Publication #:
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Pub Dt:
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05/24/2001
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Title:
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SYSTEM AND METHOD FOR PROCESSOR DUAL VOLTAGE DETECTION AND OVER STRESS PROTECTION
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Issue Dt:
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11/07/2000
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09176891
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10/22/1998
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Title:
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SLURRY FOR CHEMICAL MECHANICAL POLISHING OF COPPER
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04/30/2002
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09177043
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10/22/1998
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Pub Dt:
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01/10/2002
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Title:
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DOPANT DIFFUSION-RETARDING BARRIER REGION FORMED WITHIN POLYSILICON GATE LAYER
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07/31/2001
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09178080
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Filing Dt:
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10/22/1998
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Title:
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METHOD OF MAKING AIR GAP ISOLATION BY MAKING A LATERAL EPI BRIDGE FOR LOW K ISOLATION ADVANCED CMOS FABRICATION
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Issue Dt:
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07/31/2001
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Application #:
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09178225
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Filing Dt:
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10/23/1998
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Title:
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TRANSISTOR WITH AN ULTRA SHORT CHANNEL LENGTH DEFINED BY A LATERALLY DIFFUSED NITROGEN IMPLANT
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Patent #:
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Issue Dt:
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03/27/2001
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Application #:
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09179410
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Filing Dt:
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10/27/1998
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Title:
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SEMICONDUCTOR DEVICE HAVING A LOW DIELECTRIC CONSTANT MATERIAL
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Patent #:
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Issue Dt:
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06/20/2000
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Application #:
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09181129
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Filing Dt:
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10/28/1998
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Title:
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METHOD AND APPARATUS FOR MAKING ELECTRICAL CONTACT TO A SUBSTRATE DURING ELECTROPLATING
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Issue Dt:
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07/23/2002
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Application #:
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09182524
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Filing Dt:
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10/30/1998
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Title:
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APPARATUS AND METHOD FOR CALIBRATING A HOME NETWORKING STATION RECEIVING NETWORK SIGNALS ON A TELEPHONE LINE MEDIUM
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Patent #:
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Issue Dt:
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07/03/2001
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09182725
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Filing Dt:
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10/29/1998
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Title:
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RESTORING CHECKPOINTED PROCESSES WITHOUT RESTORING ATTRIBUTES OF EXTERNAL DATA REFERENCED BY THE PROCESSES
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Issue Dt:
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04/17/2001
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Application #:
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09182874
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Filing Dt:
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10/30/1998
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Title:
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NANO-DEVICES USING BLOCK-COPOLYMERS
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Patent #:
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Issue Dt:
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12/26/2000
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09182942
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Filing Dt:
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10/29/1998
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Title:
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SCAN TOOL RECIPE SERVER
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Patent #:
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Issue Dt:
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08/01/2000
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09182987
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Filing Dt:
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10/30/1998
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Title:
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APPARATUS AND METHOD FOR CONTROLLING TRANSMISSION PARAMETERS OF SELECTED HOME NETWORK STATIONS TRANSMITTING ON A TELEPHONE MEDIUM
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Issue Dt:
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07/25/2000
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Application #:
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09182988
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Filing Dt:
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10/30/1998
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Title:
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APPARATUS AND METHOD FOR CONTROLLING TRANSMISSION PARAMETERS OF HOME NETWORK STATIONS TRANSMITTING ON A TELEPHONE LINE MEDIUM
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Issue Dt:
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03/21/2000
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Application #:
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09183356
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Filing Dt:
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10/30/1998
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Title:
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CRITICAL DIMENSION EQUALIZATION ACROSS THE FIELD BY SECOND BLANKET EXPOSURE AT LOW DOSE OVER BLEACHABLE RESIST
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Issue Dt:
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01/11/2000
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09183522
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Filing Dt:
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10/30/1998
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Title:
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FABRICATION OF CHROME/PHASE GRATING PHASE SHIFT MASK BY INTERFEROMETRIC LITHOGRAPHY
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Issue Dt:
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12/18/2001
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09183945
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Filing Dt:
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10/31/1998
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Title:
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UART AUTOMATIC PARITY SUPPORT FOR FRAMES WITH ADDRESS BITS
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Issue Dt:
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05/08/2001
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09184009
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Filing Dt:
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11/02/1998
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Title:
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STORAGE-ANNEALING PLATED CU INTERCONNECTS
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Issue Dt:
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10/30/2001
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09184277
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Filing Dt:
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10/31/1998
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Title:
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UART SUPPORT FOR ADDRESS BIT ON SEVEN BIT FRAMES
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Patent #:
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Issue Dt:
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03/07/2000
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Application #:
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09185981
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Filing Dt:
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11/04/1998
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Title:
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SYSTEM FOR UNIFORMLY HEATING PHOTORESIST
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Patent #:
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Issue Dt:
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07/25/2000
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Application #:
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09186053
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Filing Dt:
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11/03/1998
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Title:
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METHOD TO SELECTIVELY ELECTROPLATE CONDUCTIVE MATERIAL INTO TRENCHES
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Issue Dt:
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11/21/2000
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Application #:
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09186065
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Filing Dt:
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11/05/1998
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Title:
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SHALLOW JUNCTION FORMATION BY OUT-DIFFUSION FROM A DOPED DIELECTRIC LAYER THROUGH A SALICIDE LAYER
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Issue Dt:
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07/29/2003
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09186078
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Filing Dt:
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11/05/1998
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Title:
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SHALLOW TRENCH ISOLATION FORMATION WITH ION IMPLANTATION
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Issue Dt:
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11/21/2000
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09186781
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Filing Dt:
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11/04/1998
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Title:
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BARRIER MATERIALS FOR METAL INTERCONNECT
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Patent #:
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Issue Dt:
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05/15/2001
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Application #:
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09186920
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Filing Dt:
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11/06/1998
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Title:
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BILAYER ANTI-REFLECTIVE COATING AND ETCH HARD MASK
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Issue Dt:
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01/02/2001
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09187169
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Filing Dt:
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11/06/1998
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Title:
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ELECTRON BEAN CURING OF LOW-K DIELECTRICS IN INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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09/05/2000
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Application #:
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09187171
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Filing Dt:
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11/06/1998
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Title:
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MULTIPLE THRESHOLD VOLTAGE TRANSISTOR IMPLEMENTED BY A DAMASCENE PROCESS
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Patent #:
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Issue Dt:
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05/01/2001
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Application #:
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09187172
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Filing Dt:
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11/06/1998
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Title:
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RECESSED CHANNEL STRUCTURE FOR MANUFACTURING SHALLOW SOURCE/DRAIN EXTENSIONS
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Patent #:
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Issue Dt:
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11/06/2001
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Application #:
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09187232
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Filing Dt:
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11/06/1998
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Title:
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METHOD FOR FORMING A DUAL DAMASCENE TRENCH AND UNDERLYING BORDERLESS VIA IN LOW DIELECTRIC CONSTANT MATERIALS
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Patent #:
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Issue Dt:
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04/24/2001
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Application #:
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09187252
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Filing Dt:
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11/06/1998
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Title:
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METHOD OF FABRICATING AN INTEGRATED CIRCUIT HAVING PUNCH-THROUGH SUPPRESSION
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Patent #:
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Issue Dt:
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05/09/2000
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Application #:
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09187391
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Filing Dt:
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11/06/1998
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Title:
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ANTIREFLECTIVE SILICONOXYNITRIDE HARDMASK LAYER USED DURING ETCHING PROCESSES IN INTEGRATED CIRCUIT FABRICATION
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Patent #:
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Issue Dt:
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05/29/2001
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Application #:
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09187427
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Filing Dt:
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11/06/1998
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Title:
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FORMATION OF JUNCTIONS BY DIFFUSION FROM A DOPED FILM AT SILICIDATION
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Patent #:
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Issue Dt:
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05/15/2001
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Application #:
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09187428
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Filing Dt:
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11/06/1998
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE HAVING AN IMPROVED GATE ELECTRODE PROFILE
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Patent #:
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Issue Dt:
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12/05/2000
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Application #:
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09187430
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Filing Dt:
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11/06/1998
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Title:
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METHOD OF FORMING A DUAL DAMASCENE TRENCH AND BORDERLESS VIA STRUCTURE
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Patent #:
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Issue Dt:
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04/30/2002
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09187498
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Filing Dt:
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11/06/1998
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Title:
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METHOD OF MANUFACTURING A TRANSISTOR WITH LOCAL INSULATOR STRUCTURE
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Patent #:
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Issue Dt:
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12/26/2000
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Application #:
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09187520
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Filing Dt:
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11/06/1998
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Title:
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LOW RESISTANCE METAL CONTACT TECHNOLOGY
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Patent #:
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Issue Dt:
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08/01/2000
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Application #:
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09187521
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Filing Dt:
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11/06/1998
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Title:
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FORMATION OF JUNCTIONS BY DIFFUSION FROM A DOPED FILM INTO AND THROUGH A SILICIDE DURING SILICIDATION
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Patent #:
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Issue Dt:
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08/01/2000
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Application #:
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09187524
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Filing Dt:
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11/06/1998
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Title:
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METHOD OF CONTROLLING EFFECTIVE CHANNEL LENGTH OF SEMICONDUCTOR DEVICE BY NON-DOPING IMPLANTATION AT ELEVATED ENERGIES
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Patent #:
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Issue Dt:
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03/06/2001
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Application #:
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09187542
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Filing Dt:
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11/06/1998
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Title:
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FERROELECTRIC-ENHANCED TANTALUM PENTOXIDE FOR DIELECTRIC MATERIAL APPLICATIONS IN CMOS DEVICES
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Patent #:
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Issue Dt:
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01/30/2001
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Application #:
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09187630
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Filing Dt:
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11/06/1998
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Title:
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DUAL AMORPHIZATION IMPLANT PROCESS FOR ULTRA-SHALLOW DRAIN AND SOURCE EXTENSIONS
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Patent #:
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Issue Dt:
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11/16/1999
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Application #:
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09187635
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Filing Dt:
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11/06/1998
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Title:
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DAMASCENE PROCESS FOR FORMING ULTRA-SHALLOW SOURCE/DRAIN EXTENSIONS AND POCKET IN ULSI MOSFET
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Patent #:
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Issue Dt:
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07/31/2001
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Application #:
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09187852
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Filing Dt:
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11/06/1998
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Title:
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MAINTAINING OBJECT INFORMATION CONCURRENT WITH DATA OPTIMIZATION FOR DEBUGGING
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Patent #:
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Issue Dt:
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08/28/2001
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Application #:
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09187861
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Filing Dt:
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11/06/1998
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Title:
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INTEGRATED CIRCUIT HAVING ISOLATION STRUCTURES
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Patent #:
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Issue Dt:
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03/13/2001
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Application #:
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09187890
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Filing Dt:
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11/06/1998
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Title:
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METHOD OF FABRICATING AN INTEGRATED CIRCUIT WITH ULTRA-SHALLOW SOURCE/DRAIN EXTENSIONS
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Patent #:
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Issue Dt:
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04/17/2001
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Application #:
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09187894
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Filing Dt:
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11/06/1998
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Title:
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ASYMMETRICAL IGFET DEVICES WITH SPACERS FORMED BY HDP TECHNIQUES
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Patent #:
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Issue Dt:
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03/13/2001
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Application #:
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09188085
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Filing Dt:
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11/06/1998
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Title:
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MASK FOR ASYMMETRICAL TRANSISTOR FORMATION WITH PAIRED TRANSISTORS
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Patent #:
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Issue Dt:
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08/08/2000
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Application #:
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09189228
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Filing Dt:
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11/11/1998
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Title:
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SYSTEM FOR CONTROLLING REFLECTION RETICLE TEMPERATURE IN MICROLITHOGRAPHY
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Patent #:
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Issue Dt:
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08/10/1999
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Application #:
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09189279
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Filing Dt:
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11/10/1998
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Title:
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NITROGENATED GATE STRUCTURE FOR IMPROVED TRANSISTOR PERFORMANCE AND METHOD FOR MAKING SAME
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Patent #:
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Issue Dt:
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10/12/1999
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Application #:
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09189922
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Filing Dt:
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11/12/1998
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Title:
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GRADED PB FOR C4 PUMP TECHNOLOGY
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Patent #:
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Issue Dt:
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10/03/2000
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Application #:
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09190768
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Filing Dt:
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11/12/1998
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Title:
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METHOD FOR REMOVING COPPER RESIDUE FROM SURFACES OF A SEMICONDUCTOR WAFER
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Patent #:
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Issue Dt:
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02/27/2001
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Application #:
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09190864
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Filing Dt:
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11/09/1998
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Title:
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METHOD AND SYSTEM FOR SELECTIVELY DISABLING SIMULATION MODEL INSTRUMENTATION
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Patent #:
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Issue Dt:
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02/27/2001
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Application #:
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09190865
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Filing Dt:
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11/09/1998
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Title:
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METHOD AND SYSTEM FOR INSTRUMENTING SIMULATION MODELS
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Patent #:
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Issue Dt:
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04/02/2002
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Application #:
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09190986
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Filing Dt:
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11/12/1998
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Title:
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MANUFACTURING REFERENCE DATABASE
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Patent #:
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Issue Dt:
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08/07/2001
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Application #:
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09191763
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Filing Dt:
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11/13/1998
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Title:
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INTERLAYER BETWEEN TITANIUM NITRIDE AND HIGH DENSITY PLASMA OXIDE
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Patent #:
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Issue Dt:
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05/28/2002
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Application #:
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09192092
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Filing Dt:
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11/13/1998
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Title:
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METHOD AND SYSTEM FOR PROCESSING DOCUMENT REQUESTS IN A NETWORK SYSTEM
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Patent #:
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Issue Dt:
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10/09/2001
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Application #:
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09193262
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Filing Dt:
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11/18/1998
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Title:
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METHOD OF MAKING A SEMICONDUCTOR DEVICE WITH SELF-ALIGNED ACTIVE, LIGHTLY-DOPED DRAIN, AND HALO REGIONS
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Patent #:
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Issue Dt:
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11/14/2000
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Application #:
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09193619
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Filing Dt:
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11/17/1998
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Title:
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METHOD OF MAKING SEMICONDUCTOR DEVICE HAVING SACRIFICIAL SALICIDATION LAYER
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Patent #:
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Issue Dt:
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03/27/2001
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Application #:
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09195092
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Filing Dt:
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11/18/1998
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Title:
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SILICON NITRIDE ETCH BATH SYSTEM
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Patent #:
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Issue Dt:
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12/04/2001
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Application #:
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09195187
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Filing Dt:
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11/18/1998
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Title:
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DELTA COMPRESSED ASYNCHRONOUS REMOTE COPY
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Patent #:
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Issue Dt:
|
06/04/2002
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Application #:
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09195300
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Filing Dt:
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11/18/1998
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Title:
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SEMICONDUCTOR WAFER REVIEW SYSTEM AND METHOD
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Patent #:
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Issue Dt:
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09/05/2000
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Application #:
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09195336
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Filing Dt:
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11/18/1998
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Title:
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SEMICONDUCTOR DEVICE WITH VERTICAL HALO REGION AND METHODS OF MANUFACTURE
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Patent #:
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Issue Dt:
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08/28/2001
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Application #:
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09196907
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Filing Dt:
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11/20/1998
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Title:
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METHOD AND APPARATUS FOR REDUCING PARASITIC BIPOLAR CURRENT IN A SILICON-ON-INSULATOR TRANSISTOR
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Patent #:
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Issue Dt:
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03/12/2002
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Application #:
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09197020
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Filing Dt:
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11/20/1998
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Title:
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PIEZO PROGRAMMABLE RETICLE FOR EUV LITHOGRAPHY
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Patent #:
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Issue Dt:
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01/23/2001
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Application #:
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09197167
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Filing Dt:
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11/20/1998
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Title:
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CORRECTION OF PATTERN-DEPENDENT ERRORS IN A PARTICLE BEAM LITHOGRAPHY SYSTEM
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Patent #:
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Issue Dt:
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09/19/2000
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Application #:
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09198362
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Filing Dt:
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11/24/1998
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Title:
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METHOD OF FORMING A VOID FREE COPPER INTERCONNECTS
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Patent #:
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Issue Dt:
|
09/04/2001
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Application #:
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09198820
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Filing Dt:
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11/23/1998
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Title:
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PLANAR METALLIZED SUBSTRATE WITH EMBEDDED CAMBER CONTROL MATERIAL AND METHOD THEREOF
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Patent #:
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Issue Dt:
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04/17/2001
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Application #:
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09199267
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Filing Dt:
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11/25/1998
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Title:
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COPPER DENDRITE PREVENTION BY CHEMICAL REMOVAL OF DIELECTRIC
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Patent #:
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Issue Dt:
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12/19/2000
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Application #:
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09199347
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Filing Dt:
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11/25/1998
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Title:
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CHEMICAL TREATMENT FOR PREVENTING COPPER DENDRITE FORMATION AND GROWTH
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Patent #:
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Issue Dt:
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06/13/2000
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Application #:
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09199348
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Filing Dt:
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11/25/1998
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Title:
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METHOD OF PREVENTING COPPER DENDRITE FORMATION AND GROWTH
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Patent #:
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Issue Dt:
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01/02/2001
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Application #:
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09199352
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Filing Dt:
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11/25/1998
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Title:
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CHEMICALLY REMOVABLE CU CMP SLURRY ABRASIVE
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Patent #:
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Issue Dt:
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12/19/2000
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Application #:
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09199674
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Filing Dt:
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11/25/1998
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Title:
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METHOD OF FORMING A METAL GATE ELECTRODE USING REPLACED POLYSILICON STRUCTURE
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Patent #:
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Issue Dt:
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01/23/2001
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Application #:
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09199911
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Filing Dt:
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11/25/1998
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Title:
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BPSG REFLOW METHOD TO REDUCE THERMAL BUDGET FOR NEXT GENERATION DEVICE INCLUDING HEATINGT A STEAM AMBIENT
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Patent #:
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Issue Dt:
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06/26/2001
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Application #:
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09199967
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Filing Dt:
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11/25/1998
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Title:
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INTERRUPT GATING METHOD FOR PCI BRIDGES
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Patent #:
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|
Issue Dt:
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09/26/2000
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Application #:
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09200016
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Filing Dt:
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11/25/1998
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Title:
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IN-SITU SION DEPOSITION/BAKE/TEOS DEPOSITION PROCESS FOR REDUCTION OF DEFECTS IN INTERLEVEL DIELECTRIC FOR INTEGRATED CIRCUIT INTERCONNECTS
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