skip navigationU S P T O SealUnited States Patent and Trademark Office AOTW logo
Home|Site Index|Search|Guides|Contacts|eBusiness|eBiz alerts|News|Help
Assignments on the Web > Patent Query
Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:049490/0001   Pages: 892
Recorded: 11/29/2018
Conveyance: SECURITY AGREEMENT
1
Patent #:
Issue Dt:
11/21/2000
Application #:
09057271
Filing Dt:
04/08/1998
Title:
METHOD AND CIRCUIT FOR DETECTING OVERFLOW IN OPERAND MULTIPLICATION
2
Patent #:
Issue Dt:
08/22/2000
Application #:
09102381
Filing Dt:
06/22/1998
Title:
FABRIC CUTTING WEIGHT WITH INTEGRAL SPIKES
3
Patent #:
Issue Dt:
03/06/2001
Application #:
09121216
Filing Dt:
07/23/1998
Title:
METHOD FOR DETERMINING THE HOT CARRIER LIFETIME OF A TRANSISTOR
4
Patent #:
Issue Dt:
09/10/2002
Application #:
09121922
Filing Dt:
07/25/1998
Title:
SYNTHESIS OF COMBINATORIAL LIBRARIES OF COMPOUNDS REMINISCENT OF NATURAL PRODUCTS
5
Patent #:
Issue Dt:
11/12/2002
Application #:
09161258
Filing Dt:
09/25/1998
Title:
PLASTIC LENS SYSTEMS AND METHODS
6
Patent #:
Issue Dt:
03/06/2001
Application #:
09164823
Filing Dt:
10/01/1998
Title:
METHOD FOR PROVIDING COOPERATIVE RUN-TO-RUN CONTROL FOR MULTI-PRODUCT AND MULTI-PROCESS SEMICONDUCTOR FABRICATION
7
Patent #:
Issue Dt:
07/10/2001
Application #:
09164881
Filing Dt:
10/01/1998
Title:
INTERFEROMETER METHOD FOR PROVIDING STABILITY OF A LASER
8
Patent #:
Issue Dt:
01/15/2002
Application #:
09165609
Filing Dt:
10/02/1998
Title:
USING PADDED INSTRUCTIONS IN A BLOCK-ORIENTED CACHE
9
Patent #:
Issue Dt:
08/22/2000
Application #:
09165783
Filing Dt:
10/02/1998
Title:
METHOD TO MANUFACTURE MULTIPLE DAMASCENE BY UTILIZING ETCH SELECTIVITY
10
Patent #:
Issue Dt:
12/05/2000
Application #:
09165957
Filing Dt:
10/02/1998
Title:
COPPER ETCHING COMPOSITIONS, PROCESSES AND PRODUCTS DERIVED THEREFROM
11
Patent #:
Issue Dt:
12/05/2000
Application #:
09166440
Filing Dt:
10/05/1998
Title:
CIRCUIT AND METHOD FOR REDUCING DATA DEPENDENCIES BETWEEN INSTRUCTIONS
12
Patent #:
Issue Dt:
08/28/2001
Application #:
09167622
Filing Dt:
10/06/1998
Title:
DEVICE AND METHOD FOR ETCHING NITRIDE SPACERS FORMED UPON AN INTEGRATED CIRCUIT GATE CONDUCTOR
13
Patent #:
Issue Dt:
11/27/2001
Application #:
09168456
Filing Dt:
10/08/1998
Title:
MICROMECHANICAL DISPLAYS AND FABRICATION METHOD
14
Patent #:
Issue Dt:
09/12/2000
Application #:
09169281
Filing Dt:
10/08/1998
Title:
METHOD FOR IMPLANTING SEMICONDUCTOR CONDUCTIVE LAYERS
15
Patent #:
Issue Dt:
11/19/2002
Application #:
09169347
Filing Dt:
10/09/1998
Title:
HIERARCHICAL TEXTURE CACHE
16
Patent #:
Issue Dt:
12/05/2000
Application #:
09170335
Filing Dt:
10/13/1998
Title:
POWER SUPPLY INDEPENDENT TEMPERATURE SENSOR
17
Patent #:
Issue Dt:
11/28/2000
Application #:
09170619
Filing Dt:
10/13/1998
Title:
METHOD OF FABRICATING ULTRA SHALLOW JUNCTION CMOS TRANSISTORS WITH NITRIDE DISPOSABLE SPACER
18
Patent #:
Issue Dt:
11/07/2000
Application #:
09172088
Filing Dt:
10/14/1998
Title:
SHALLOW TRENCH ISOLATION FORMATION WITH SPACER-ASSISTED ION IMPLANTATION
19
Patent #:
Issue Dt:
03/04/2003
Application #:
09172732
Filing Dt:
10/13/1998
Title:
ARTICLE EXHIBITING ENHANCED ADHESION BETWEEN A DIELECTRIC SUBSTRATE AND HEAT SPREADER AND METHOD
20
Patent #:
Issue Dt:
04/17/2001
Application #:
09172759
Filing Dt:
10/15/1998
Title:
SYSTEM FOR GATED DETECTION OF OPTICAL PULSES CONTAINING A SMALL NUMBER OF PHOTONS USING AN AVALANCHE PHTOTDIODE
21
Patent #:
Issue Dt:
05/08/2001
Application #:
09172982
Filing Dt:
10/14/1998
Title:
METHOD OF MAKING DUAL DAMASCENE CONDUCTIVE INTERCONNECTIONS AND INTEGRATED CIRCUIT DEVICE COMPRISING SAME
22
Patent #:
Issue Dt:
02/13/2001
Application #:
09173015
Filing Dt:
10/15/1998
Title:
INTEGRATION OF ISOLATION WITH EPITAXIAL GROWTH REGIONS FOR ENHANCED DEVICE FORMATION
23
Patent #:
Issue Dt:
07/04/2000
Application #:
09173233
Filing Dt:
10/15/1998
Title:
TRANSISTOR HAVING A METAL SILICIDE SELF-ALIGNED TO THE GATE
24
Patent #:
Issue Dt:
08/15/2000
Application #:
09174037
Filing Dt:
10/16/1998
Title:
MECHANISM FOR MINIMIZING OVERHEAD USAGE OF A HOST SYSTEM BY POLLING FOR SUBSEQUENT INTERRUPTS AFTER SERVICE OF A PRIOR INTERRUPT
25
Patent #:
Issue Dt:
10/16/2001
Application #:
09174900
Filing Dt:
10/19/1998
Title:
METHOD AND SYSTEM FOR DATA TRANSMISSION IN ACCELERATED GRAPHICS PORT SYSTEMS
26
Patent #:
Issue Dt:
07/03/2001
Application #:
09175652
Filing Dt:
10/20/1998
Title:
SEMICONDUCTOR DEVICE HAVING SILICIDE LAYERS FORMED USING A COLLIMATED METAL LAYER
27
Patent #:
Issue Dt:
07/18/2000
Application #:
09175709
Filing Dt:
10/20/1998
Title:
MECHANISM FOR SYNCHRONIZING SERVICE OF INTERRUPTS BY A PLURALITY OF DATA PROCESSORS
28
Patent #:
Issue Dt:
12/04/2001
Application #:
09176737
Filing Dt:
10/21/1998
Publication #:
Pub Dt:
05/24/2001
Title:
SYSTEM AND METHOD FOR PROCESSOR DUAL VOLTAGE DETECTION AND OVER STRESS PROTECTION
29
Patent #:
Issue Dt:
11/07/2000
Application #:
09176891
Filing Dt:
10/22/1998
Title:
SLURRY FOR CHEMICAL MECHANICAL POLISHING OF COPPER
30
Patent #:
Issue Dt:
04/30/2002
Application #:
09177043
Filing Dt:
10/22/1998
Publication #:
Pub Dt:
01/10/2002
Title:
DOPANT DIFFUSION-RETARDING BARRIER REGION FORMED WITHIN POLYSILICON GATE LAYER
31
Patent #:
Issue Dt:
07/31/2001
Application #:
09178080
Filing Dt:
10/22/1998
Title:
METHOD OF MAKING AIR GAP ISOLATION BY MAKING A LATERAL EPI BRIDGE FOR LOW K ISOLATION ADVANCED CMOS FABRICATION
32
Patent #:
Issue Dt:
07/31/2001
Application #:
09178225
Filing Dt:
10/23/1998
Title:
TRANSISTOR WITH AN ULTRA SHORT CHANNEL LENGTH DEFINED BY A LATERALLY DIFFUSED NITROGEN IMPLANT
33
Patent #:
Issue Dt:
03/27/2001
Application #:
09179410
Filing Dt:
10/27/1998
Title:
SEMICONDUCTOR DEVICE HAVING A LOW DIELECTRIC CONSTANT MATERIAL
34
Patent #:
Issue Dt:
06/20/2000
Application #:
09181129
Filing Dt:
10/28/1998
Title:
METHOD AND APPARATUS FOR MAKING ELECTRICAL CONTACT TO A SUBSTRATE DURING ELECTROPLATING
35
Patent #:
Issue Dt:
07/23/2002
Application #:
09182524
Filing Dt:
10/30/1998
Title:
APPARATUS AND METHOD FOR CALIBRATING A HOME NETWORKING STATION RECEIVING NETWORK SIGNALS ON A TELEPHONE LINE MEDIUM
36
Patent #:
Issue Dt:
07/03/2001
Application #:
09182725
Filing Dt:
10/29/1998
Title:
RESTORING CHECKPOINTED PROCESSES WITHOUT RESTORING ATTRIBUTES OF EXTERNAL DATA REFERENCED BY THE PROCESSES
37
Patent #:
Issue Dt:
04/17/2001
Application #:
09182874
Filing Dt:
10/30/1998
Title:
NANO-DEVICES USING BLOCK-COPOLYMERS
38
Patent #:
Issue Dt:
12/26/2000
Application #:
09182942
Filing Dt:
10/29/1998
Title:
SCAN TOOL RECIPE SERVER
39
Patent #:
Issue Dt:
08/01/2000
Application #:
09182987
Filing Dt:
10/30/1998
Title:
APPARATUS AND METHOD FOR CONTROLLING TRANSMISSION PARAMETERS OF SELECTED HOME NETWORK STATIONS TRANSMITTING ON A TELEPHONE MEDIUM
40
Patent #:
Issue Dt:
07/25/2000
Application #:
09182988
Filing Dt:
10/30/1998
Title:
APPARATUS AND METHOD FOR CONTROLLING TRANSMISSION PARAMETERS OF HOME NETWORK STATIONS TRANSMITTING ON A TELEPHONE LINE MEDIUM
41
Patent #:
Issue Dt:
03/21/2000
Application #:
09183356
Filing Dt:
10/30/1998
Title:
CRITICAL DIMENSION EQUALIZATION ACROSS THE FIELD BY SECOND BLANKET EXPOSURE AT LOW DOSE OVER BLEACHABLE RESIST
42
Patent #:
Issue Dt:
01/11/2000
Application #:
09183522
Filing Dt:
10/30/1998
Title:
FABRICATION OF CHROME/PHASE GRATING PHASE SHIFT MASK BY INTERFEROMETRIC LITHOGRAPHY
43
Patent #:
Issue Dt:
12/18/2001
Application #:
09183945
Filing Dt:
10/31/1998
Title:
UART AUTOMATIC PARITY SUPPORT FOR FRAMES WITH ADDRESS BITS
44
Patent #:
Issue Dt:
05/08/2001
Application #:
09184009
Filing Dt:
11/02/1998
Title:
STORAGE-ANNEALING PLATED CU INTERCONNECTS
45
Patent #:
Issue Dt:
10/30/2001
Application #:
09184277
Filing Dt:
10/31/1998
Title:
UART SUPPORT FOR ADDRESS BIT ON SEVEN BIT FRAMES
46
Patent #:
Issue Dt:
03/07/2000
Application #:
09185981
Filing Dt:
11/04/1998
Title:
SYSTEM FOR UNIFORMLY HEATING PHOTORESIST
47
Patent #:
Issue Dt:
07/25/2000
Application #:
09186053
Filing Dt:
11/03/1998
Title:
METHOD TO SELECTIVELY ELECTROPLATE CONDUCTIVE MATERIAL INTO TRENCHES
48
Patent #:
Issue Dt:
11/21/2000
Application #:
09186065
Filing Dt:
11/05/1998
Title:
SHALLOW JUNCTION FORMATION BY OUT-DIFFUSION FROM A DOPED DIELECTRIC LAYER THROUGH A SALICIDE LAYER
49
Patent #:
Issue Dt:
07/29/2003
Application #:
09186078
Filing Dt:
11/05/1998
Title:
SHALLOW TRENCH ISOLATION FORMATION WITH ION IMPLANTATION
50
Patent #:
Issue Dt:
11/21/2000
Application #:
09186781
Filing Dt:
11/04/1998
Title:
BARRIER MATERIALS FOR METAL INTERCONNECT
51
Patent #:
Issue Dt:
05/15/2001
Application #:
09186920
Filing Dt:
11/06/1998
Title:
BILAYER ANTI-REFLECTIVE COATING AND ETCH HARD MASK
52
Patent #:
Issue Dt:
01/02/2001
Application #:
09187169
Filing Dt:
11/06/1998
Title:
ELECTRON BEAN CURING OF LOW-K DIELECTRICS IN INTEGRATED CIRCUITS
53
Patent #:
Issue Dt:
09/05/2000
Application #:
09187171
Filing Dt:
11/06/1998
Title:
MULTIPLE THRESHOLD VOLTAGE TRANSISTOR IMPLEMENTED BY A DAMASCENE PROCESS
54
Patent #:
Issue Dt:
05/01/2001
Application #:
09187172
Filing Dt:
11/06/1998
Title:
RECESSED CHANNEL STRUCTURE FOR MANUFACTURING SHALLOW SOURCE/DRAIN EXTENSIONS
55
Patent #:
Issue Dt:
11/06/2001
Application #:
09187232
Filing Dt:
11/06/1998
Title:
METHOD FOR FORMING A DUAL DAMASCENE TRENCH AND UNDERLYING BORDERLESS VIA IN LOW DIELECTRIC CONSTANT MATERIALS
56
Patent #:
Issue Dt:
04/24/2001
Application #:
09187252
Filing Dt:
11/06/1998
Title:
METHOD OF FABRICATING AN INTEGRATED CIRCUIT HAVING PUNCH-THROUGH SUPPRESSION
57
Patent #:
Issue Dt:
05/09/2000
Application #:
09187391
Filing Dt:
11/06/1998
Title:
ANTIREFLECTIVE SILICONOXYNITRIDE HARDMASK LAYER USED DURING ETCHING PROCESSES IN INTEGRATED CIRCUIT FABRICATION
58
Patent #:
Issue Dt:
05/29/2001
Application #:
09187427
Filing Dt:
11/06/1998
Title:
FORMATION OF JUNCTIONS BY DIFFUSION FROM A DOPED FILM AT SILICIDATION
59
Patent #:
Issue Dt:
05/15/2001
Application #:
09187428
Filing Dt:
11/06/1998
Title:
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE HAVING AN IMPROVED GATE ELECTRODE PROFILE
60
Patent #:
Issue Dt:
12/05/2000
Application #:
09187430
Filing Dt:
11/06/1998
Title:
METHOD OF FORMING A DUAL DAMASCENE TRENCH AND BORDERLESS VIA STRUCTURE
61
Patent #:
Issue Dt:
04/30/2002
Application #:
09187498
Filing Dt:
11/06/1998
Title:
METHOD OF MANUFACTURING A TRANSISTOR WITH LOCAL INSULATOR STRUCTURE
62
Patent #:
Issue Dt:
12/26/2000
Application #:
09187520
Filing Dt:
11/06/1998
Title:
LOW RESISTANCE METAL CONTACT TECHNOLOGY
63
Patent #:
Issue Dt:
08/01/2000
Application #:
09187521
Filing Dt:
11/06/1998
Title:
FORMATION OF JUNCTIONS BY DIFFUSION FROM A DOPED FILM INTO AND THROUGH A SILICIDE DURING SILICIDATION
64
Patent #:
Issue Dt:
08/01/2000
Application #:
09187524
Filing Dt:
11/06/1998
Title:
METHOD OF CONTROLLING EFFECTIVE CHANNEL LENGTH OF SEMICONDUCTOR DEVICE BY NON-DOPING IMPLANTATION AT ELEVATED ENERGIES
65
Patent #:
Issue Dt:
03/06/2001
Application #:
09187542
Filing Dt:
11/06/1998
Title:
FERROELECTRIC-ENHANCED TANTALUM PENTOXIDE FOR DIELECTRIC MATERIAL APPLICATIONS IN CMOS DEVICES
66
Patent #:
Issue Dt:
01/30/2001
Application #:
09187630
Filing Dt:
11/06/1998
Title:
DUAL AMORPHIZATION IMPLANT PROCESS FOR ULTRA-SHALLOW DRAIN AND SOURCE EXTENSIONS
67
Patent #:
Issue Dt:
11/16/1999
Application #:
09187635
Filing Dt:
11/06/1998
Title:
DAMASCENE PROCESS FOR FORMING ULTRA-SHALLOW SOURCE/DRAIN EXTENSIONS AND POCKET IN ULSI MOSFET
68
Patent #:
Issue Dt:
07/31/2001
Application #:
09187852
Filing Dt:
11/06/1998
Title:
MAINTAINING OBJECT INFORMATION CONCURRENT WITH DATA OPTIMIZATION FOR DEBUGGING
69
Patent #:
Issue Dt:
08/28/2001
Application #:
09187861
Filing Dt:
11/06/1998
Title:
INTEGRATED CIRCUIT HAVING ISOLATION STRUCTURES
70
Patent #:
Issue Dt:
03/13/2001
Application #:
09187890
Filing Dt:
11/06/1998
Title:
METHOD OF FABRICATING AN INTEGRATED CIRCUIT WITH ULTRA-SHALLOW SOURCE/DRAIN EXTENSIONS
71
Patent #:
Issue Dt:
04/17/2001
Application #:
09187894
Filing Dt:
11/06/1998
Title:
ASYMMETRICAL IGFET DEVICES WITH SPACERS FORMED BY HDP TECHNIQUES
72
Patent #:
Issue Dt:
03/13/2001
Application #:
09188085
Filing Dt:
11/06/1998
Title:
MASK FOR ASYMMETRICAL TRANSISTOR FORMATION WITH PAIRED TRANSISTORS
73
Patent #:
Issue Dt:
08/08/2000
Application #:
09189228
Filing Dt:
11/11/1998
Title:
SYSTEM FOR CONTROLLING REFLECTION RETICLE TEMPERATURE IN MICROLITHOGRAPHY
74
Patent #:
Issue Dt:
08/10/1999
Application #:
09189279
Filing Dt:
11/10/1998
Title:
NITROGENATED GATE STRUCTURE FOR IMPROVED TRANSISTOR PERFORMANCE AND METHOD FOR MAKING SAME
75
Patent #:
Issue Dt:
10/12/1999
Application #:
09189922
Filing Dt:
11/12/1998
Title:
GRADED PB FOR C4 PUMP TECHNOLOGY
76
Patent #:
Issue Dt:
10/03/2000
Application #:
09190768
Filing Dt:
11/12/1998
Title:
METHOD FOR REMOVING COPPER RESIDUE FROM SURFACES OF A SEMICONDUCTOR WAFER
77
Patent #:
Issue Dt:
02/27/2001
Application #:
09190864
Filing Dt:
11/09/1998
Title:
METHOD AND SYSTEM FOR SELECTIVELY DISABLING SIMULATION MODEL INSTRUMENTATION
78
Patent #:
Issue Dt:
02/27/2001
Application #:
09190865
Filing Dt:
11/09/1998
Title:
METHOD AND SYSTEM FOR INSTRUMENTING SIMULATION MODELS
79
Patent #:
Issue Dt:
04/02/2002
Application #:
09190986
Filing Dt:
11/12/1998
Title:
MANUFACTURING REFERENCE DATABASE
80
Patent #:
Issue Dt:
08/07/2001
Application #:
09191763
Filing Dt:
11/13/1998
Title:
INTERLAYER BETWEEN TITANIUM NITRIDE AND HIGH DENSITY PLASMA OXIDE
81
Patent #:
Issue Dt:
05/28/2002
Application #:
09192092
Filing Dt:
11/13/1998
Title:
METHOD AND SYSTEM FOR PROCESSING DOCUMENT REQUESTS IN A NETWORK SYSTEM
82
Patent #:
Issue Dt:
10/09/2001
Application #:
09193262
Filing Dt:
11/18/1998
Title:
METHOD OF MAKING A SEMICONDUCTOR DEVICE WITH SELF-ALIGNED ACTIVE, LIGHTLY-DOPED DRAIN, AND HALO REGIONS
83
Patent #:
Issue Dt:
11/14/2000
Application #:
09193619
Filing Dt:
11/17/1998
Title:
METHOD OF MAKING SEMICONDUCTOR DEVICE HAVING SACRIFICIAL SALICIDATION LAYER
84
Patent #:
Issue Dt:
03/27/2001
Application #:
09195092
Filing Dt:
11/18/1998
Title:
SILICON NITRIDE ETCH BATH SYSTEM
85
Patent #:
Issue Dt:
12/04/2001
Application #:
09195187
Filing Dt:
11/18/1998
Title:
DELTA COMPRESSED ASYNCHRONOUS REMOTE COPY
86
Patent #:
Issue Dt:
06/04/2002
Application #:
09195300
Filing Dt:
11/18/1998
Title:
SEMICONDUCTOR WAFER REVIEW SYSTEM AND METHOD
87
Patent #:
Issue Dt:
09/05/2000
Application #:
09195336
Filing Dt:
11/18/1998
Title:
SEMICONDUCTOR DEVICE WITH VERTICAL HALO REGION AND METHODS OF MANUFACTURE
88
Patent #:
Issue Dt:
08/28/2001
Application #:
09196907
Filing Dt:
11/20/1998
Title:
METHOD AND APPARATUS FOR REDUCING PARASITIC BIPOLAR CURRENT IN A SILICON-ON-INSULATOR TRANSISTOR
89
Patent #:
Issue Dt:
03/12/2002
Application #:
09197020
Filing Dt:
11/20/1998
Title:
PIEZO PROGRAMMABLE RETICLE FOR EUV LITHOGRAPHY
90
Patent #:
Issue Dt:
01/23/2001
Application #:
09197167
Filing Dt:
11/20/1998
Title:
CORRECTION OF PATTERN-DEPENDENT ERRORS IN A PARTICLE BEAM LITHOGRAPHY SYSTEM
91
Patent #:
Issue Dt:
09/19/2000
Application #:
09198362
Filing Dt:
11/24/1998
Title:
METHOD OF FORMING A VOID FREE COPPER INTERCONNECTS
92
Patent #:
Issue Dt:
09/04/2001
Application #:
09198820
Filing Dt:
11/23/1998
Title:
PLANAR METALLIZED SUBSTRATE WITH EMBEDDED CAMBER CONTROL MATERIAL AND METHOD THEREOF
93
Patent #:
Issue Dt:
04/17/2001
Application #:
09199267
Filing Dt:
11/25/1998
Title:
COPPER DENDRITE PREVENTION BY CHEMICAL REMOVAL OF DIELECTRIC
94
Patent #:
Issue Dt:
12/19/2000
Application #:
09199347
Filing Dt:
11/25/1998
Title:
CHEMICAL TREATMENT FOR PREVENTING COPPER DENDRITE FORMATION AND GROWTH
95
Patent #:
Issue Dt:
06/13/2000
Application #:
09199348
Filing Dt:
11/25/1998
Title:
METHOD OF PREVENTING COPPER DENDRITE FORMATION AND GROWTH
96
Patent #:
Issue Dt:
01/02/2001
Application #:
09199352
Filing Dt:
11/25/1998
Title:
CHEMICALLY REMOVABLE CU CMP SLURRY ABRASIVE
97
Patent #:
Issue Dt:
12/19/2000
Application #:
09199674
Filing Dt:
11/25/1998
Title:
METHOD OF FORMING A METAL GATE ELECTRODE USING REPLACED POLYSILICON STRUCTURE
98
Patent #:
Issue Dt:
01/23/2001
Application #:
09199911
Filing Dt:
11/25/1998
Title:
BPSG REFLOW METHOD TO REDUCE THERMAL BUDGET FOR NEXT GENERATION DEVICE INCLUDING HEATINGT A STEAM AMBIENT
99
Patent #:
Issue Dt:
06/26/2001
Application #:
09199967
Filing Dt:
11/25/1998
Title:
INTERRUPT GATING METHOD FOR PCI BRIDGES
100
Patent #:
Issue Dt:
09/26/2000
Application #:
09200016
Filing Dt:
11/25/1998
Title:
IN-SITU SION DEPOSITION/BAKE/TEOS DEPOSITION PROCESS FOR REDUCTION OF DEFECTS IN INTERLEVEL DIELECTRIC FOR INTEGRATED CIRCUIT INTERCONNECTS
Assignor
1
Exec Dt:
11/27/2018
Assignee
1
1100 NORTH MARKET STREET
WILMINGTON, DELAWARE 19801
Correspondence name and address
CT CORPORATION
4400 EASTON COMMONS WAY
SUITE 125
COLUMBUS, OH 43219

Search Results as of: 04/27/2024 03:32 AM
If you have any comments or questions concerning the data displayed, contact PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified: August 25, 2017 v.2.6
| .HOME | INDEX| SEARCH | eBUSINESS | CONTACT US | PRIVACY STATEMENT