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Patent #:
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|
Issue Dt:
|
02/05/2002
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Application #:
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09616951
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Filing Dt:
|
07/14/2000
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Title:
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Capacitor having sidewall spacer protecting the dielectric layer
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|
Patent #:
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|
Issue Dt:
|
09/03/2002
|
Application #:
|
09617158
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Filing Dt:
|
07/17/2000
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Title:
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DELIBERATE VOID IN INNERLAYER DIELECTRIC GAPFILL TO REDUCE DIELECTRIC CONSTANT
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|
Patent #:
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|
Issue Dt:
|
02/25/2003
|
Application #:
|
09617259
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Filing Dt:
|
07/14/2000
|
Title:
|
OSCILLATOR WITH DIGITALLY VARIABLE PHASE FOR A PHASE-LOCKED LOOP
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|
Patent #:
|
|
Issue Dt:
|
07/06/2004
|
Application #:
|
09617558
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Filing Dt:
|
07/17/2000
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Title:
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PROGRAMMABLE COMPENSATED DELAY FOR DDR SDRAM INTERFACE USING PROGRAMMABLE DELAY LOOP FOR REFERENCE CALIBRATION
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|
Patent #:
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|
Issue Dt:
|
03/18/2003
|
Application #:
|
09617908
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Filing Dt:
|
07/14/2000
|
Title:
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METHOD AND APPARATUS FOR MAKING INTEGRATED CIRCUITS HAVING GATED CLOCK TREES
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|
Patent #:
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|
Issue Dt:
|
03/30/2004
|
Application #:
|
09618057
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Filing Dt:
|
07/17/2000
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Title:
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IN-BAND MANAGEMENT OF A STACKED GROUP OF SWITCHES BY A SINGLE CPU
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|
Patent #:
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|
Issue Dt:
|
12/09/2003
|
Application #:
|
09618167
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Filing Dt:
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07/17/2000
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Title:
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METHOD TO ACHIEVE LOW AND STABLE FERROMAGNETIC COUPLING FIELD
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|
Patent #:
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|
Issue Dt:
|
12/27/2005
|
Application #:
|
09618291
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Filing Dt:
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07/18/2000
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Title:
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FLOW CONTROL ARRANGEMENT IN A NETWORK SWITCH BASED ON PRIORITY TRAFFIC
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|
Patent #:
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|
Issue Dt:
|
08/07/2001
|
Application #:
|
09619789
|
Filing Dt:
|
07/20/2000
|
Title:
|
Damascene T-gate using a relacs flow
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|
Patent #:
|
|
Issue Dt:
|
07/03/2001
|
Application #:
|
09619836
|
Filing Dt:
|
07/20/2000
|
Title:
|
Damascene T-gate using a spacer flow
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|
Patent #:
|
|
Issue Dt:
|
03/19/2002
|
Application #:
|
09619838
|
Filing Dt:
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07/20/2000
|
Title:
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Capacitively coupled DTMOS on SOI for multiple devices
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|
Patent #:
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|
Issue Dt:
|
11/20/2001
|
Application #:
|
09620145
|
Filing Dt:
|
07/20/2000
|
Title:
|
T-gate formation using modified damascene processing with two masks
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|
Patent #:
|
|
Issue Dt:
|
07/09/2002
|
Application #:
|
09620300
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Filing Dt:
|
07/20/2000
|
Title:
|
T-GATE FORMATION USING A MODIFIED CONVENTIONAL POLY PROCESS
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|
Patent #:
|
|
Issue Dt:
|
09/17/2002
|
Application #:
|
09620981
|
Filing Dt:
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07/21/2000
|
Title:
|
FLEXIBLE IMPLEMENTATION OF A SYSTEM MANAGEMENT MODE (SMM) IN A PROCESSOR
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|
Patent #:
|
|
Issue Dt:
|
05/14/2002
|
Application #:
|
09621156
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Filing Dt:
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07/21/2000
|
Title:
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METHOD OF POROUS DIELECTRIC FORMATION WITH ANODIC TEMPLATE
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|
Patent #:
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|
Issue Dt:
|
12/17/2002
|
Application #:
|
09621290
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Filing Dt:
|
07/20/2000
|
Title:
|
ARGON IMPLANTATION AFTER SILICIDATION FOR IMPROVED FLOATING-BODY EFFECTS
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|
Patent #:
|
|
Issue Dt:
|
06/08/2004
|
Application #:
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09621931
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Filing Dt:
|
07/24/2000
|
Title:
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A SYSTEM AND METHOD FOR SELECTING BETWEEN A VOLTAGE SPECIFIED BY A PROCESSOR AND AN ALTERNATE VOLTAGE TO BE SUPPLIED TO HE PROCESSOR
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|
Patent #:
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|
Issue Dt:
|
05/06/2003
|
Application #:
|
09624494
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Filing Dt:
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07/24/2000
|
Title:
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DYNAMIC PULSE WIDTH PROGRAMMING OF PROGRAMMABLE LOGIC DEVICES
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|
Patent #:
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|
Issue Dt:
|
03/16/2004
|
Application #:
|
09624656
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Filing Dt:
|
07/25/2000
|
Title:
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METHOD OF CONTROLLING SHEET RESISTANCE OF METAL SILICIDE REGIONS BY CONTROLLING THE SALICIDE STRIP TIME
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|
|
Patent #:
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|
Issue Dt:
|
10/23/2001
|
Application #:
|
09624841
|
Filing Dt:
|
07/25/2000
|
Title:
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INSTRUCTION QUEUE EVALUATING DEPENDENCY VECTOR IN PORTIONS DURING DIFFERENT CLOCK PHASES
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|
Patent #:
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|
Issue Dt:
|
09/23/2003
|
Application #:
|
09625140
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Filing Dt:
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07/25/2000
|
Title:
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METHOD AND APPARATUS FOR PERFORMING FINAL CRITICAL DIMENSION CONTROL
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|
Patent #:
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|
Issue Dt:
|
03/26/2002
|
Application #:
|
09625367
|
Filing Dt:
|
07/26/2000
|
Title:
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EDGE SEAL RING FOR COPPER DAMASCENE PROCESS AND METHOD FOR FABRICATION THEREOF
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|
Patent #:
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|
Issue Dt:
|
04/30/2002
|
Application #:
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09625587
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Filing Dt:
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07/26/2000
|
Title:
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Method and apparatus for monitoring material removal tool performance using endpoint time removal rate determination
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|
Patent #:
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|
Issue Dt:
|
10/08/2002
|
Application #:
|
09625620
|
Filing Dt:
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07/26/2000
|
Title:
|
APPARATUS AND METHOD FOR VERIFYING PROCESS INTEGRITY
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|
Patent #:
|
|
Issue Dt:
|
05/13/2003
|
Application #:
|
09625649
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Filing Dt:
|
07/26/2000
|
Title:
|
PHOTORESIST COMPOSITIONS WITH CYCLIC OLEFIN POLYMERS AND HYDROPHOBIC NON-STEROIDAL MULTI-ALICYCLIC ADDITIVES
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|
Patent #:
|
|
Issue Dt:
|
04/09/2002
|
Application #:
|
09626454
|
Filing Dt:
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07/26/2000
|
Title:
|
Method of forming capped copper interconnects with reduced hillocks
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|
Patent #:
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|
Issue Dt:
|
07/22/2003
|
Application #:
|
09626455
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Filing Dt:
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07/26/2000
|
Title:
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METHOD OF FORMING COPPER INTERCONNECT CAPPING LAYERS WITH IMPROVED INTERFACE AND ADHESION
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|
Patent #:
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|
Issue Dt:
|
02/04/2003
|
Application #:
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09626615
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Filing Dt:
|
07/27/2000
|
Title:
|
SYSTEM AND METHOD FOR CONTROLLING ACCESS TO A PRIVILEGE-PARTITIONED ADDRESS SPACE WITH A FIXED SET OF ATTRIBUTES
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|
Patent #:
|
|
Issue Dt:
|
05/21/2002
|
Application #:
|
09626668
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Filing Dt:
|
07/27/2000
|
Title:
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METHOD FOR FORMING VERTICAL PROFILE OF POLYSILICON GATE ELECTRODES
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|
Patent #:
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|
Issue Dt:
|
07/22/2003
|
Application #:
|
09627436
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Filing Dt:
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07/28/2000
|
Title:
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DETERMINATION OF FLUX COVERAGE
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|
Patent #:
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|
Issue Dt:
|
01/08/2002
|
Application #:
|
09627599
|
Filing Dt:
|
07/28/2000
|
Title:
|
Low-power DC voltage generator system
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|
|
Patent #:
|
|
Issue Dt:
|
05/20/2003
|
Application #:
|
09627874
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Filing Dt:
|
07/28/2000
|
Title:
|
METHOD AND APPARATUS FOR MONITORING CONSUMABLE PERFORMANCE
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|
Patent #:
|
|
Issue Dt:
|
04/16/2002
|
Application #:
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09628382
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Filing Dt:
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08/01/2000
|
Title:
|
METHOD FOR MAKING RAISED SOURCE/DRAIN REGIONS USING LASER
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|
|
Patent #:
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|
Issue Dt:
|
07/30/2002
|
Application #:
|
09628822
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Filing Dt:
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07/31/2000
|
Title:
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REDUCTION OF VIA ETCH CHARGING DAMAGE THROUGH THE USE OF A CONDUCTING HARD MASK
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|
|
Patent #:
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|
Issue Dt:
|
04/30/2002
|
Application #:
|
09629883
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Filing Dt:
|
08/01/2000
|
Title:
|
PREVENTION OF DOPANT OUT-DIFFUSION DURING SILICIDATION AND JUNCTION FORMATION
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|
|
Patent #:
|
|
Issue Dt:
|
05/07/2002
|
Application #:
|
09632499
|
Filing Dt:
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08/03/2000
|
Title:
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Method and system for package orientation checking for laser mark operations
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|
|
Patent #:
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|
Issue Dt:
|
08/06/2002
|
Application #:
|
09633208
|
Filing Dt:
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08/07/2000
|
Title:
|
MULTIPLE ACTIVE LAYER STRUCTURE AND A METHOD OF MAKING SUCH A STRUCTURE
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|
|
Patent #:
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|
Issue Dt:
|
02/19/2002
|
Application #:
|
09633620
|
Filing Dt:
|
08/07/2000
|
Title:
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Electroplating multi-trace circuit board substrates using single tie bar
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|
|
Patent #:
|
|
Issue Dt:
|
10/15/2002
|
Application #:
|
09633960
|
Filing Dt:
|
08/08/2000
|
Title:
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SILICON WAFER INCLUDING BOTH BULK AND SOI REGIONS AND METHOD FOR FORMING SAME ON A BULK SILICON WAFER
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|
Patent #:
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|
Issue Dt:
|
04/30/2002
|
Application #:
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09634990
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Filing Dt:
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08/08/2000
|
Title:
|
Shallow trench isolation formation with two source/drain masks and simplified planarization mask
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|
Patent #:
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|
Issue Dt:
|
08/20/2002
|
Application #:
|
09636239
|
Filing Dt:
|
08/10/2000
|
Title:
|
SEMICONDUCTOR-ON-INSULATOR TRANSISTOR WITH RECESSED SOURCE AND DRAIN
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|
|
Patent #:
|
|
Issue Dt:
|
12/25/2001
|
Application #:
|
09636516
|
Filing Dt:
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08/10/2000
|
Title:
|
Slurry for chemical mechanical polishing of copper
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|
Patent #:
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|
Issue Dt:
|
11/08/2005
|
Application #:
|
09637015
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Filing Dt:
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08/14/2000
|
Title:
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APPARATUS AND METHOD FOR IDENTIFYING DATA PACKET AT WIRE RATE ON A NETWORK SWITCH PORT
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|
Patent #:
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|
Issue Dt:
|
03/16/2004
|
Application #:
|
09637100
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Filing Dt:
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08/10/2000
|
Title:
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LOT SPECIFIC PROCESS DESIGN METHODOLOGY
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|
Patent #:
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|
Issue Dt:
|
10/28/2003
|
Application #:
|
09638729
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Filing Dt:
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08/14/2000
|
Title:
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BALL GRID ARRAY MODULE
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|
Patent #:
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|
Issue Dt:
|
05/21/2002
|
Application #:
|
09639784
|
Filing Dt:
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08/16/2000
|
Title:
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RESIST COMPOSITIONS CONTAINING BULKY ANHYDRIDE ADDITIVES
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|
Patent #:
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|
Issue Dt:
|
09/30/2003
|
Application #:
|
09639785
|
Filing Dt:
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08/16/2000
|
Title:
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RESIST COMPOSITIONS CONTAINING LACTONE ADDITIVES
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|
Patent #:
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|
Issue Dt:
|
05/21/2002
|
Application #:
|
09639799
|
Filing Dt:
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08/17/2000
|
Title:
|
METHOD OF SELECTIVELY CONTROLLING CONTACT RESISTANCE BY CONTROLLING IMPURITY CONCENTRATION AND SILICIDE THICKNESS
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|
Patent #:
|
|
Issue Dt:
|
11/20/2001
|
Application #:
|
09639812
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Filing Dt:
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08/17/2000
|
Title:
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Method and apparatus for improved planarity metallization by electroplating and CMP
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|
Patent #:
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|
Issue Dt:
|
02/11/2003
|
Application #:
|
09640081
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Filing Dt:
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08/17/2000
|
Title:
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AVOIDING FLUORINE CONTAMINATION OF COPPER INTERCONNECTS
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|
Patent #:
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|
Issue Dt:
|
09/03/2002
|
Application #:
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09640177
|
Filing Dt:
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08/17/2000
|
Title:
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LASER TAILORING RETROGRADE CHANNEL PROFILE IN SURFACES
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|
Patent #:
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|
Issue Dt:
|
01/01/2002
|
Application #:
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09641205
|
Filing Dt:
|
08/18/2000
|
Title:
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MANUFACTURIMG A DRAM CELL HAVING AN ANNULAR SIGNAL TRANSFER REGION
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|
Patent #:
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|
Issue Dt:
|
05/07/2002
|
Application #:
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09641436
|
Filing Dt:
|
08/18/2000
|
Title:
|
Method of forming junction-leakage free metal salicide in a semiconductor wafer with ultra-low silicon consumption
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|
Patent #:
|
|
Issue Dt:
|
04/09/2002
|
Application #:
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09641727
|
Filing Dt:
|
08/21/2000
|
Title:
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LOW RESISTANCE COMPOSITE CONTACT STRUCTURE UTILIZING A REACTION BARRIER LAYER UNDER A METAL LAYER
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|
Patent #:
|
|
Issue Dt:
|
03/19/2002
|
Application #:
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09641834
|
Filing Dt:
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08/18/2000
|
Title:
|
METHOD OF FORMING BARRIER LAYERS FOR DAMASCENE INTERCONNECTS
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|
Patent #:
|
|
Issue Dt:
|
04/09/2002
|
Application #:
|
09642831
|
Filing Dt:
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08/22/2000
|
Title:
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DETECTION OF FLUX RESIDUE
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|
Patent #:
|
|
Issue Dt:
|
07/10/2001
|
Application #:
|
09642832
|
Filing Dt:
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08/22/2000
|
Title:
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Determination of flux prior to package assembly
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|
Patent #:
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|
Issue Dt:
|
09/02/2003
|
Application #:
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09643072
|
Filing Dt:
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08/21/2000
|
Title:
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VERTICAL CACHE CONFIGURATION
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|
Patent #:
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|
Issue Dt:
|
11/06/2001
|
Application #:
|
09643343
|
Filing Dt:
|
08/22/2000
|
Title:
|
Y-gate formation using damascene processing
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|
Patent #:
|
|
Issue Dt:
|
06/11/2002
|
Application #:
|
09643611
|
Filing Dt:
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08/22/2000
|
Title:
|
T OR T/Y GATE FORMATION USING TRIM ETCH PROCESSING
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|
Patent #:
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|
Issue Dt:
|
03/25/2003
|
Application #:
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09645499
|
Filing Dt:
|
08/25/2000
|
Title:
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SALICIDE DEVICE WITH BORDERLESS CONTACT BACKGROUND OF THE INVENTION
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|
|
Patent #:
|
|
Issue Dt:
|
02/18/2003
|
Application #:
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09645923
|
Filing Dt:
|
08/24/2000
|
Title:
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METHOD AND SYSTEM TO REDUCE SWITCHING SIGNAL NOISE ON A DEVICE AND A DEVICE AS RESULT THEREOF
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|
|
Patent #:
|
|
Issue Dt:
|
11/06/2001
|
Application #:
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09648862
|
Filing Dt:
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08/25/2000
|
Title:
|
Multilayer ceramic substrate with anchored pad
|
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|
Patent #:
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|
Issue Dt:
|
02/11/2003
|
Application #:
|
09649733
|
Filing Dt:
|
08/28/2000
|
Title:
|
ANALOG-TO-DIGITAL CONVERTER
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|
Patent #:
|
|
Issue Dt:
|
04/08/2003
|
Application #:
|
09650011
|
Filing Dt:
|
08/29/2000
|
Title:
|
DUAL-PORT DRAM ARCHITECTURE SYSTEM
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|
Patent #:
|
|
Issue Dt:
|
11/25/2003
|
Application #:
|
09650153
|
Filing Dt:
|
08/29/2000
|
Title:
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METHOD TO DETERMINE RETRIES FOR PARALLEL ECC CORRECTION IN A PIPELINE
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|
Patent #:
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|
Issue Dt:
|
04/29/2003
|
Application #:
|
09650399
|
Filing Dt:
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08/29/2000
|
Title:
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DISTRIBUTED STATIC TIMING ANALYSIS
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|
Patent #:
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|
Issue Dt:
|
08/12/2003
|
Application #:
|
09650538
|
Filing Dt:
|
08/30/2000
|
Title:
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CVD PLASMA PROCESS TO FILL CONTACT HOLE IN DAMASCENE PROCESS
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|
|
Patent #:
|
|
Issue Dt:
|
11/26/2002
|
Application #:
|
09651464
|
Filing Dt:
|
08/30/2000
|
Title:
|
CONTRACT METHODOLOGY FOR CONCURRENT HIERARCHICAL DESIGN
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|
|
Patent #:
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|
Issue Dt:
|
09/10/2002
|
Application #:
|
09651893
|
Filing Dt:
|
08/30/2000
|
Title:
|
INTEGRATED CIRCUIT PACKAGE INCORPORATING CAMOUFLAGED PROGRAMMABLE ELEMENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/09/2002
|
Application #:
|
09652596
|
Filing Dt:
|
08/30/2000
|
Title:
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CAPACITOR LAMINATE FOR USE IN PRINTED CIRCUIT BOARD AND AS AN INTERCONNECTOR
|
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|
Patent #:
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|
Issue Dt:
|
07/06/2004
|
Application #:
|
09652647
|
Filing Dt:
|
08/31/2000
|
Title:
|
SYSTEM AND METHOD FOR MONITOING AND CONTROLLING A POWER-MANAGEABLE RESOURCE BASED UPON ACTIVITIES OF A PLURALITY OF DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/02/2002
|
Application #:
|
09652754
|
Filing Dt:
|
08/31/2000
|
Title:
|
METHOD OF FORMING MULTILEVEL INTERCONNECT STRUCTURE CONTAINING AIR GAPS INCLUDING UTILIZING BOTH SACRIFICIAL AND PLACEHOLDER MATERIAL
|
|
|
Patent #:
|
|
Issue Dt:
|
10/29/2002
|
Application #:
|
09653435
|
Filing Dt:
|
09/01/2000
|
Title:
|
RESIST REMOVAL MONITORING BY RAMAN SPECTROSCOPY
|
|
|
Patent #:
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|
Issue Dt:
|
02/18/2003
|
Application #:
|
09654963
|
Filing Dt:
|
09/05/2000
|
Title:
|
COPPER ETCHING COMPOSITIONS AND PRODUCTS DERIVED THEREFROM
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|
|
Patent #:
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|
Issue Dt:
|
05/14/2002
|
Application #:
|
09655700
|
Filing Dt:
|
09/06/2000
|
Title:
|
FILLING AN INTERCONNECT OPENING WITH DIFFERENT TYPES OF ALLOYS TO ENHANCE INTERCONNECT RELIABILITY
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|
|
Patent #:
|
|
Issue Dt:
|
10/29/2002
|
Application #:
|
09656437
|
Filing Dt:
|
09/06/2000
|
Title:
|
H2 DIFFUSION BARRIER FORMATION BY NITROGEN INCORPORATION IN OXIDE LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2003
|
Application #:
|
09657194
|
Filing Dt:
|
09/07/2000
|
Title:
|
ELECTRICAL COUPLING OF A STIFFENER TO A CHIP CARRIER
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Patent #:
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Issue Dt:
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01/28/2003
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Application #:
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09657315
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Filing Dt:
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09/07/2000
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Title:
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HIGH-VOLTAGE HIGH-SPEED SOI MOSFET
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Patent #:
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Issue Dt:
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04/09/2002
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Application #:
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09660396
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Filing Dt:
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09/12/2000
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Title:
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PASSIVATION OF SEMICONDUCTOR DEVICE SURFACES USING AN IODINE/ETHANOL SOLUTION
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Patent #:
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Issue Dt:
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04/29/2003
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Application #:
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09660723
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Filing Dt:
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09/13/2000
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Title:
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DRY ISOTROPIC REMOVAL OF INORGANIC ANTI-REFLECTIVE COATING AFTER POLY GATE ETCHING
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Patent #:
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Issue Dt:
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04/02/2002
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Application #:
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09660724
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Filing Dt:
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09/13/2000
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Title:
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Isotropic resistor protect etch to aid in residue removal
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Patent #:
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Issue Dt:
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12/10/2002
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Application #:
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09660866
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Filing Dt:
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09/13/2000
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Title:
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INTEGRATED SEMICONDUCTOR PACKAGE
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Patent #:
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Issue Dt:
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04/16/2002
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Application #:
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09661041
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Filing Dt:
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09/14/2000
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Title:
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FABRICATION OF METAL OXIDE STRUCTURE FOR A GATE DIELECTRIC OF A FIELD EFFECT TRANSISTOR
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Patent #:
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Issue Dt:
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05/13/2003
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Application #:
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09661694
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Filing Dt:
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09/14/2000
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Title:
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METHOD AND APPARATUS FOR PARSING EVENT LOGS TO DETERMINE TOOL OPERABILITY
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Patent #:
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Issue Dt:
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10/01/2002
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Application #:
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09662016
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Filing Dt:
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09/14/2000
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Title:
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MEASUREMENT METHOD OF ZERNIKE COMA ABERRATION COEFFICIENT
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Patent #:
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Issue Dt:
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06/17/2003
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Application #:
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09664238
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Filing Dt:
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09/18/2000
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Title:
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METHOD OF FORMING CONDUCTIVE INTERCONNECTIONS ON AN INTEGRATED CIRCUIT DEVICE
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Patent #:
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Issue Dt:
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05/14/2002
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Application #:
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09664714
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Filing Dt:
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09/19/2000
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Title:
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PASSIVATION OF SIDEWALL SPACERS USING OZONATED WATER
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Patent #:
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Issue Dt:
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02/05/2002
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Application #:
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09664863
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Filing Dt:
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09/19/2000
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Title:
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Barrier materials for metal interconnect in a semiconductor device
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Patent #:
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Issue Dt:
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12/11/2001
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Application #:
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09666088
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Filing Dt:
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09/21/2000
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Title:
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Self-aligned damascene gate formation with low gate resistance
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Patent #:
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Issue Dt:
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04/09/2002
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Application #:
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09667573
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Filing Dt:
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09/22/2000
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Title:
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ACTIVE MASK EXPOSURE COMPENSATION OF UNDERLYING NITRIDE THICKNESS VARIATION TO REDUCE CRITICAL DIMENSION (CD) VARIATION
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Patent #:
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Issue Dt:
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02/04/2003
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Application #:
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09667600
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Filing Dt:
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09/22/2000
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Title:
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METHOD OF INHIBITING LATERAL DIFFUSION BETWEEN ADJACENT WELLS BY INTRODUCING CARBON OR FLUORINE IONS INTO BOTTOM OF STI GROOVE
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Patent #:
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Issue Dt:
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02/05/2002
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Application #:
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09667601
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Filing Dt:
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09/22/2000
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Title:
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Removable spacer technology using ion implantation for forming asymmetric MOS transistors
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Patent #:
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Issue Dt:
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01/08/2002
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Application #:
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09667602
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Filing Dt:
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09/22/2000
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Title:
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Use of knocked-on oxygen atoms for reduction of transient enhanced diffusion
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Patent #:
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Issue Dt:
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07/23/2002
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Application #:
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09667685
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Filing Dt:
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09/22/2000
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Title:
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RETROGRADE WELL STRUCTURE FORMATION BY NITROGEN IMPLANTATION
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Patent #:
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Issue Dt:
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12/02/2003
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Application #:
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09668142
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Filing Dt:
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09/25/2000
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Title:
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GROOVED POLISHING PADS AND METHODS OF USE
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Patent #:
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Issue Dt:
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12/02/2003
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Application #:
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09669117
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Filing Dt:
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09/25/2000
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Title:
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COMPILABLE ADDRESS MAGNITUDE COMPARATOR FOR MEMORY ARRAY SELF-TESTING
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Patent #:
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Issue Dt:
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07/01/2003
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Application #:
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09670728
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Filing Dt:
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09/27/2000
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Title:
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MULTIPOLE ELECTROSTATIC E-BEAM DEFLECTOR
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Patent #:
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Issue Dt:
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01/21/2003
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Application #:
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09670741
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Filing Dt:
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09/27/2000
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Title:
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PROCESS FOR PROTECTING ARRAY TOP OXIDE
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Patent #:
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Issue Dt:
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02/18/2003
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Application #:
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09670968
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Filing Dt:
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09/27/2000
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Title:
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FABRICATION OF A METALIZED BLIND VIA
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