|
|
Patent #:
|
|
Issue Dt:
|
02/11/2003
|
Application #:
|
09671944
|
Filing Dt:
|
09/27/2000
|
Title:
|
SUPERCONDUCTOR BARRIER LAYER FOR INTEGRATED CIRCUIT INTERCONNECTS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/21/2003
|
Application #:
|
09675246
|
Filing Dt:
|
09/29/2000
|
Title:
|
SEMICONDUCTOR FUSES AND ANTIFUSES IN VERTICAL DRAMS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/21/2004
|
Application #:
|
09675435
|
Filing Dt:
|
09/29/2000
|
Title:
|
EXTENDIBLE PROCESS FOR IMPROVED TOP OXIDE LAYER FOR DRAM ARRAY AND THE GATE INTERCONNECTS WHILE PROVIDING SELF-ALIGNED GATE CONTACTS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/29/2003
|
Application #:
|
09675634
|
Filing Dt:
|
09/29/2000
|
Title:
|
SYSTEM AND METHOD FOR FAST INTERCONNECT DELAY ESTIMATION THROUGH ITERATIVE REFINEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
02/25/2003
|
Application #:
|
09675840
|
Filing Dt:
|
09/29/2000
|
Title:
|
PREPARATION OF STRAINED SI/SIGE ON INSULATOR BY HYDROGEN INDUCED LAYER TRANSFER TECHNIQUE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/16/2003
|
Application #:
|
09676882
|
Filing Dt:
|
09/29/2000
|
Title:
|
METHOD OF FILM DEPOSITION, AND FABRICATION OF STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/23/2003
|
Application #:
|
09676883
|
Filing Dt:
|
09/29/2000
|
Title:
|
SYSTEM AND METHOD FOR SEGMENTATION OF IMAGES OF OBJECTS THAT ARE OCCLUDED BY A SEMI-TRANSPARENT MATERIAL
|
|
|
Patent #:
|
|
Issue Dt:
|
08/21/2001
|
Application #:
|
09677955
|
Filing Dt:
|
10/02/2000
|
Title:
|
Method for detecting sloped contact holes using a critical-dimension waveform
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2003
|
Application #:
|
09678315
|
Filing Dt:
|
10/03/2000
|
Title:
|
SILICON-ON-INSULATOR (SOI) TRENCH PHOTODIODE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/16/2002
|
Application #:
|
09678633
|
Filing Dt:
|
10/03/2000
|
Title:
|
ENDPOINT DETECTION BY CHEMICAL REACTION
|
|
|
Patent #:
|
|
Issue Dt:
|
12/31/2002
|
Application #:
|
09678946
|
Filing Dt:
|
10/03/2000
|
Title:
|
ATOMIC LAYER BARRIER LAYER FOR INTEGRATED CIRCUIT INTERCONNECTS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/29/2002
|
Application #:
|
09679124
|
Filing Dt:
|
10/04/2000
|
Title:
|
Super low-power generator system for embedded applications
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2002
|
Application #:
|
09679369
|
Filing Dt:
|
10/05/2000
|
Title:
|
Enhanced electroless deposition of dielectric precursor materials for use in in-laid gate MOS transistors
|
|
|
Patent #:
|
|
Issue Dt:
|
09/17/2002
|
Application #:
|
09679370
|
Filing Dt:
|
10/05/2000
|
Title:
|
DOUBLE SILICIDE FORMATION IN POLYSILICON GATE WITHOUT SILICIDE IN SOURCE/DRAIN EXTENSIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/19/2002
|
Application #:
|
09679373
|
Filing Dt:
|
10/05/2000
|
Title:
|
NITROGEN OXIDE PLASMA TREATMENT FOR REDUCED NICKEL SILICIDE BRIDGING
|
|
|
Patent #:
|
|
Issue Dt:
|
05/07/2002
|
Application #:
|
09679374
|
Filing Dt:
|
10/05/2000
|
Title:
|
NH3/N2-PLASMA TREATMENT FOR REDUCED NICKEL SILICIDE BRIDGING
|
|
|
Patent #:
|
|
Issue Dt:
|
04/08/2003
|
Application #:
|
09679375
|
Filing Dt:
|
10/05/2000
|
Title:
|
COMPOSITE SILICON NITRIDE SIDEWALL SPACERS FOR REDUCED NICKEL SILICIDE BRIDGING
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2002
|
Application #:
|
09679738
|
Filing Dt:
|
10/05/2000
|
Title:
|
METHOD FOR FORMING A TIN LAYER ON TOP OF A METAL SILICIDE LAYER IN A SEMICONDUCTOR STRUCTURE AND STRUCTURE FORMED
|
|
|
Patent #:
|
|
Issue Dt:
|
10/09/2001
|
Application #:
|
09679872
|
Filing Dt:
|
10/05/2000
|
Title:
|
Electrolytic deposition of dielectric precursor materials for use in in-laid gate MOS transistors
|
|
|
Patent #:
|
|
Issue Dt:
|
02/18/2003
|
Application #:
|
09679880
|
Filing Dt:
|
10/05/2000
|
Title:
|
HDP TREATMENT FOR REDUCED NICKEL SILICIDE BRIDGING
|
|
|
Patent #:
|
|
Issue Dt:
|
07/01/2003
|
Application #:
|
09680819
|
Filing Dt:
|
10/05/2000
|
Title:
|
METHOD AND APPARATUS FOR SIGNAL INTEGRITY VERIFICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
04/08/2003
|
Application #:
|
09681541
|
Filing Dt:
|
04/25/2001
|
Title:
|
LIGHT CONTROLLED SILICON ON INSULATOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/27/2002
|
Application #:
|
09682016
|
Filing Dt:
|
07/10/2001
|
Title:
|
SELF-ALIGNED SIGE NPN WITH IMPROVED ESD ROBUSTNESS USING WIDE EMITTER POLYSILICON EXTENSION
|
|
|
Patent #:
|
|
Issue Dt:
|
08/06/2002
|
Application #:
|
09682638
|
Filing Dt:
|
10/01/2001
|
Title:
|
EMBEDDED CAM TEST STRUCTURE FOR FULLY TESTING ALL MATCHLINES
|
|
|
Patent #:
|
|
Issue Dt:
|
11/18/2003
|
Application #:
|
09682707
|
Filing Dt:
|
10/09/2001
|
Publication #:
|
|
Pub Dt:
|
04/10/2003
| | | | |
Title:
|
GENERATION OF REFINED SWITCHING WINDOWS IN STATIC TIMING ANALYSIS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/22/2002
|
Application #:
|
09682868
|
Filing Dt:
|
10/26/2001
|
Title:
|
ACTIVE WELL SCHEMES FOR SOI TECHNOLOGY
|
|
|
Patent #:
|
|
Issue Dt:
|
12/21/2004
|
Application #:
|
09683091
|
Filing Dt:
|
11/16/2001
|
Publication #:
|
|
Pub Dt:
|
05/22/2003
| | | | |
Title:
|
ON-CHIP LOGIC ANALYZER
|
|
|
Patent #:
|
|
Issue Dt:
|
08/13/2002
|
Application #:
|
09683105
|
Filing Dt:
|
11/19/2001
|
Title:
|
DOUBLE-GATE LOW POWER SOI ACTIVE CLAMP NETWORK FOR SINGLE POWER SUPPLY AND MULTIPLE POWER SUPPLY APPLICATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/05/2004
|
Application #:
|
09683328
|
Filing Dt:
|
12/14/2001
|
Publication #:
|
|
Pub Dt:
|
06/19/2003
| | | | |
Title:
|
IMPLANTED ASYMMETRIC DOPED POLYSILICON GATE FINFET
|
|
|
Patent #:
|
|
Issue Dt:
|
08/10/2004
|
Application #:
|
09683486
|
Filing Dt:
|
01/07/2002
|
Publication #:
|
|
Pub Dt:
|
07/10/2003
| | | | |
Title:
|
FIN-BASED DOUBLE POLY DYNAMIC THRESHOLD CMOS FET WITH SPACER GATE AND METHOD OF FABRICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
12/30/2003
|
Application #:
|
09683498
|
Filing Dt:
|
01/09/2002
|
Publication #:
|
|
Pub Dt:
|
07/10/2003
| | | | |
Title:
|
SILICON GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR WITH CARBON INCORPORATION
|
|
|
Patent #:
|
|
Issue Dt:
|
06/24/2003
|
Application #:
|
09683626
|
Filing Dt:
|
01/28/2002
|
Title:
|
SELF-ALIGNED DOG-BONE STRUCTURE FOR FINFET APPLICATIONS AND METHODS TO FABRICATE THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
09/23/2003
|
Application #:
|
09683656
|
Filing Dt:
|
01/30/2002
|
Publication #:
|
|
Pub Dt:
|
07/31/2003
| | | | |
Title:
|
HIGH MOBILITY TRANSISTORS IN SOI AND METHOD FOR FORMING
|
|
|
Patent #:
|
|
Issue Dt:
|
04/01/2008
|
Application #:
|
09683677
|
Filing Dt:
|
02/01/2002
|
Publication #:
|
|
Pub Dt:
|
08/07/2003
| | | | |
Title:
|
METHOD OF SWITCHING EXTERNAL MODELS IN AN AUTOMATED SYSTEM-ON-CHIP INTEGRATED CIRCUIT DESIGN VERIFICATION SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
09/16/2003
|
Application #:
|
09683808
|
Filing Dt:
|
02/19/2002
|
Publication #:
|
|
Pub Dt:
|
08/21/2003
| | | | |
Title:
|
REDUNDANT ANTIFUSE SEGMENTS FOR IMPROVED PROGRAMMING EFFICIENCY
|
|
|
Patent #:
|
|
Issue Dt:
|
02/11/2003
|
Application #:
|
09683809
|
Filing Dt:
|
02/19/2002
|
Title:
|
EMBEDDED ONE-TIME PROGRAMMABLE NON-VOLATILE MEMORY USING PROMPT SHIFT DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/20/2004
|
Application #:
|
09683831
|
Filing Dt:
|
02/21/2002
|
Publication #:
|
|
Pub Dt:
|
08/21/2003
| | | | |
Title:
|
TWIN-CELL FLASH MEMORY STRUCTURE AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
06/01/2004
|
Application #:
|
09683983
|
Filing Dt:
|
03/08/2002
|
Publication #:
|
|
Pub Dt:
|
09/11/2003
| | | | |
Title:
|
OPTIMIZED BLOCKING IMPURITY PLACEMENT FOR SIGE HBTS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/10/2008
|
Application #:
|
09683985
|
Filing Dt:
|
03/08/2002
|
Publication #:
|
|
Pub Dt:
|
09/11/2003
| | | | |
Title:
|
METHOD OF FORMING LOW CAPACITANCE ESD ROBUST DIODES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/01/2003
|
Application #:
|
09683986
|
Filing Dt:
|
03/08/2002
|
Title:
|
SELF-ALIGNED SILICON GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR DEVICE WITH ELECTROSTATIC DISCHARGE CREVICE COVER FOR SALICIDE DISPLACEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
08/31/2004
|
Application #:
|
09684463
|
Filing Dt:
|
10/06/2000
|
Title:
|
INSULATIVE CAP FOR LASER FUSING
|
|
|
Patent #:
|
|
Issue Dt:
|
09/23/2003
|
Application #:
|
09684849
|
Filing Dt:
|
10/06/2000
|
Title:
|
KERF CIRCUIT FOR MODELING OF BEOL CAPACITANCES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/30/2002
|
Application #:
|
09686476
|
Filing Dt:
|
10/10/2000
|
Title:
|
SEMICONDUCTOR WITH LATERALLY NON-UNIFORM CHANNEL DOPING PROFILE AND MANUFACTURING METHOD THEREFOR
|
|
|
Patent #:
|
|
Issue Dt:
|
05/27/2003
|
Application #:
|
09686720
|
Filing Dt:
|
10/10/2000
|
Title:
|
SYSTEM AND METHOD FOR THE COORDINATED SIMPLIFICATION OF SURFACE AND WIRE-FRAME DESCRIPTIONS OF A GEOMETRIC MODEL
|
|
|
Patent #:
|
|
Issue Dt:
|
03/02/2004
|
Application #:
|
09686742
|
Filing Dt:
|
10/11/2000
|
Title:
|
SEMICONDUCTOR STRUCTURE HAVING IN-SITU FORMED UNIT RESISTORS AND METHOD FOR FABRICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
10/29/2002
|
Application #:
|
09688928
|
Filing Dt:
|
10/17/2000
|
Title:
|
SEMICONDUCTOR DEVICE COMPRISING COPPER INTERCONNECTS WITH REDUCED IN-LINE COPPER DIFFUSION
|
|
|
Patent #:
|
|
Issue Dt:
|
02/26/2002
|
Application #:
|
09689096
|
Filing Dt:
|
10/12/2000
|
Title:
|
Embedded dram on silicon-on-insulator substrate
|
|
|
Patent #:
|
|
Issue Dt:
|
02/26/2002
|
Application #:
|
09689660
|
Filing Dt:
|
10/13/2000
|
Title:
|
Semiconductor device having ultra-sharp P-N junction and method of manufacturing the same
|
|
|
Patent #:
|
|
Issue Dt:
|
11/06/2001
|
Application #:
|
09690073
|
Filing Dt:
|
10/16/2000
|
Title:
|
Field effect transistor with spacers that are removable with preservation of the gate dielectric
|
|
|
Patent #:
|
|
Issue Dt:
|
04/29/2003
|
Application #:
|
09690674
|
Filing Dt:
|
10/17/2000
|
Title:
|
SOI HYBRID STRUCTURE WITH SELECTIVE EPITAXIAL GROWTH OF SILICON
|
|
|
Patent #:
|
|
Issue Dt:
|
04/29/2003
|
Application #:
|
09690704
|
Filing Dt:
|
10/16/2000
|
Title:
|
CHEMICAL-MECHANICAL POLISHING PAD CONDITIONING SYSTEM AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
03/04/2003
|
Application #:
|
09691181
|
Filing Dt:
|
10/19/2000
|
Title:
|
METAL GATE WITH CVD AMORPHOUS SILICON LAYER FOR CMOS DEVICES AND METHOD OF MAKING WITH A REPLACEMENT GATE PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/21/2002
|
Application #:
|
09691224
|
Filing Dt:
|
10/19/2000
|
Title:
|
METAL GATE WITH PVD AMORPHOUS SILICON LAYER FOR CMOS DEVICES AND METHOD OF MAKING WITH A REPLACEMENT GATE PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/2003
|
Application #:
|
09691226
|
Filing Dt:
|
10/19/2000
|
Title:
|
METAL GATE WITH PVD AMORPHOUS SILICON LAYER HAVING IMPLANTED DOPANTS FOR CMOS DEVICES AND METHOD OF MAKING WITH A REPLACEMENT GATE PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/04/2003
|
Application #:
|
09691227
|
Filing Dt:
|
10/19/2000
|
Title:
|
METAL GATE WITH PVD AMORPHOUS SILICON LAYER AND BARRIER LAYER FOR CMOS DEVICES AND METHOD OF MAKING WITH A REPLACEMENT GATE PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/02/2001
|
Application #:
|
09691228
|
Filing Dt:
|
10/19/2000
|
Title:
|
High dielectric constant materials as gate dielectrics
|
|
|
Patent #:
|
|
Issue Dt:
|
01/16/2007
|
Application #:
|
09691353
|
Filing Dt:
|
10/18/2000
|
Title:
|
METHOD OF FABRICATING SEMICONDUCTOR SIDE WALL FIN
|
|
|
Patent #:
|
|
Issue Dt:
|
05/11/2004
|
Application #:
|
09691377
|
Filing Dt:
|
10/18/2000
|
Title:
|
INDIRECT ADDRESSING METHOD AND DEVICE INCORPORATING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
01/07/2003
|
Application #:
|
09693047
|
Filing Dt:
|
10/21/2000
|
Title:
|
COMPACT DUAL-PORT DRAM ARCHITECTURE SYSTEM AND METHOD FOR MAKING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
09/16/2003
|
Application #:
|
09693292
|
Filing Dt:
|
10/19/2000
|
Title:
|
APPARATUS TO EVALUATE HOT CARRIER INJECTION PERFORMANCE DEGRADATION AND METHOD THEREFOR
|
|
|
Patent #:
|
|
Issue Dt:
|
09/17/2002
|
Application #:
|
09693815
|
Filing Dt:
|
10/23/2000
|
Title:
|
MULTIMEDIA SEARCH AND INDEXING FOR AUTOMATIC SELECTION OF SCENES AND/OR SOUNDS RECORDED IN A MEDIA FOR REPLAY BY SETTING AUDIO CLIP LEVELS FOR FREQUENCY RANGES OF INTEREST IN THE MEDIA
|
|
|
Patent #:
|
|
Issue Dt:
|
04/23/2002
|
Application #:
|
09693926
|
Filing Dt:
|
10/23/2000
|
Title:
|
MULTIMEDIA SEARCH AND INDEXING FOR AUTOMATIC SELECTION OF SCENES AND/OR SOUNDS RECORDED IN A MEDIA FOR REPLAY FOR ANALYZING
|
|
|
Patent #:
|
|
Issue Dt:
|
07/02/2002
|
Application #:
|
09693966
|
Filing Dt:
|
10/23/2000
|
Title:
|
MULTIMEDIA SEARCH AND INDEXING FOR AUTOMATIC SELECTION OF SCENES AND/OR SOUNDS RECORDED IN A MEDIA FOR REPLAY USING AUDIO CUES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/16/2001
|
Application #:
|
09694139
|
Filing Dt:
|
10/23/2000
|
Title:
|
Method and apparatus for embedded process control framework in tool systems
|
|
|
Patent #:
|
|
Issue Dt:
|
12/25/2001
|
Application #:
|
09696049
|
Filing Dt:
|
10/26/2000
|
Title:
|
Pattern-block flux deposition
|
|
|
Patent #:
|
|
Issue Dt:
|
08/27/2002
|
Application #:
|
09696054
|
Filing Dt:
|
10/25/2000
|
Title:
|
CASCODE BARREL READ
|
|
|
Patent #:
|
|
Issue Dt:
|
09/17/2002
|
Application #:
|
09699651
|
Filing Dt:
|
10/30/2000
|
Title:
|
INCREASED DAMPING OF MAGNETIZATION IN MAGNETIC MATERIALS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/10/2002
|
Application #:
|
09699900
|
Filing Dt:
|
10/30/2000
|
Title:
|
DUAL DAMASCENE PROCESSING FOR SEMICONDUCTOR CHIP INTERCONNECTS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/2003
|
Application #:
|
09699977
|
Filing Dt:
|
10/30/2000
|
Title:
|
A METHOD FOR MANUFACTURING A BUILT-UP CIRCUIT BOARD
|
|
|
Patent #:
|
|
Issue Dt:
|
03/19/2002
|
Application #:
|
09702220
|
Filing Dt:
|
10/30/2000
|
Title:
|
PREDECODING MULTIPLE INSTRUCTIONS AS ONE COMBINED INSTRUCTION AND DETECTING BRANCH TO ONE OF THE INSTRUCTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/24/2002
|
Application #:
|
09702406
|
Filing Dt:
|
10/31/2000
|
Title:
|
APPARATUS AND METHOD FOR ANTIFUSE WITH ELECTROSTATIC ASSIST
|
|
|
Patent #:
|
|
Issue Dt:
|
07/29/2003
|
Application #:
|
09703062
|
Filing Dt:
|
10/31/2000
|
Title:
|
THIN FILM ATTACHMENT TO LAMINATE USING A DENDRITIC INTERCONNECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
08/27/2002
|
Application #:
|
09703092
|
Filing Dt:
|
10/31/2000
|
Title:
|
THIN RESIST WITH TRANSITION METAL HARD MASK FOR VIA ETCH APPLICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
04/30/2002
|
Application #:
|
09703512
|
Filing Dt:
|
10/30/2000
|
Title:
|
TRANSISTOR WITH ELECTRICALLY INDUCED SOURCE/DRAIN EXTENSIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/07/2002
|
Application #:
|
09703513
|
Filing Dt:
|
10/31/2000
|
Title:
|
Antireflective coating used in the fabrication of microcircuit structures in 0.18 micron and smaller technologies
|
|
|
Patent #:
|
|
Issue Dt:
|
07/09/2002
|
Application #:
|
09705121
|
Filing Dt:
|
11/01/2000
|
Title:
|
VOID ELIMINATING SEED LAYER AND CONDUCTOR CORE INTEGRATED CIRCUIT INTERCONNECTS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/17/2001
|
Application #:
|
09706492
|
Filing Dt:
|
11/03/2000
|
Title:
|
Method for forming dual workfunction high-performance support mosfets in EDRAM arrays
|
|
|
Patent #:
|
|
Issue Dt:
|
04/08/2003
|
Application #:
|
09706498
|
Filing Dt:
|
11/03/2000
|
Title:
|
POLISHED HARD MASK PROCESS FOR CONDUCTOR LAYER PATTERNING
|
|
|
Patent #:
|
|
Issue Dt:
|
07/15/2003
|
Application #:
|
09707214
|
Filing Dt:
|
11/06/2000
|
Title:
|
SELF-ALIGNED/MASKLESS REVERSE ETCH PROCESS USING AN INORGANIC FILM
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2001
|
Application #:
|
09708104
|
Filing Dt:
|
11/03/2000
|
Title:
|
Chemical resist thickness reduction process
|
|
|
Patent #:
|
|
Issue Dt:
|
04/15/2003
|
Application #:
|
09708142
|
Filing Dt:
|
11/08/2000
|
Title:
|
METHOD AND SYSTEM FOR IMPROVING THE PERFORMANCE ON SOI MEMORY ARRAYS IN AN SRAM ARCHITECTURE SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
09/24/2002
|
Application #:
|
09708216
|
Filing Dt:
|
11/07/2000
|
Title:
|
PROCESSOR CONFIGURED TO PREDECODE RELATIVE CONTROL TRANSFER INSTRUCTIONS AND REPLACE DISPLACEMENTS THEREIN WITH A TARGET ADDRESS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/10/2006
|
Application #:
|
09708494
|
Filing Dt:
|
11/09/2000
|
Title:
|
SYSTEM-ON-A-CHIP STRUCTURE HAVING A MULTIPLE CHANNEL BUS BRIDGE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/28/2002
|
Application #:
|
09711328
|
Filing Dt:
|
11/13/2000
|
Title:
|
Self-aligned double gate silicon-on-insulator (SOI) device
|
|
|
Patent #:
|
|
Issue Dt:
|
08/06/2002
|
Application #:
|
09711401
|
Filing Dt:
|
11/13/2000
|
Title:
|
METHOD OF MAKING HIGH PERFORMANCE TRANSISTOR WITH A REDUCED WIDTH GATE ELECTRODE AND DEVICE COMPRISING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
11/12/2002
|
Application #:
|
09712320
|
Filing Dt:
|
11/14/2000
|
Title:
|
SOI DEVICE WITH SELF-ALIGNED SELECTIVE DAMAGE IMPLANT, AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
05/04/2004
|
Application #:
|
09712391
|
Filing Dt:
|
11/14/2000
|
Title:
|
INCREASING AN ELECTRICAL RESISTANCE OF A RESISTOR BY OXIDATION OR NITRIDIZATION
|
|
|
Patent #:
|
|
Issue Dt:
|
04/22/2003
|
Application #:
|
09712646
|
Filing Dt:
|
11/14/2000
|
Title:
|
METHOD AND APPARATUS FOR SIMULTANEOUS ONLINE ACCESS OF VOLUME-MANAGED DATA STORAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/23/2002
|
Application #:
|
09712995
|
Filing Dt:
|
11/15/2000
|
Title:
|
METHOD FOR FORMING FIELD EFFECT TRANSISTOR WITH SILICIDES OF DIFFERENT THICKNESS AND OF DIFFERENT MATERIALS FOR THE SOURCE/DRAIN AND THE GATE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/15/2003
|
Application #:
|
09713313
|
Filing Dt:
|
11/16/2000
|
Title:
|
METHOD OF PROMOTING VOID FREE COPPER INTERCONNECTS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/10/2005
|
Application #:
|
09713830
|
Filing Dt:
|
11/15/2000
|
Title:
|
FET WITH T-SHAPED GATE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/17/2006
|
Application #:
|
09714024
|
Filing Dt:
|
11/15/2000
|
Title:
|
CLIENT SIDE, WEB-BASED SPREADSHEET
|
|
|
Patent #:
|
|
Issue Dt:
|
11/09/2004
|
Application #:
|
09714373
|
Filing Dt:
|
11/16/2000
|
Title:
|
COMPLIANT LAMINATE CONNECTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
06/04/2002
|
Application #:
|
09714504
|
Filing Dt:
|
11/16/2000
|
Title:
|
COPPER INTERCONNECTION STRUCTURE INCORPORATING A METAL SEED LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
03/30/2004
|
Application #:
|
09715184
|
Filing Dt:
|
11/20/2000
|
Title:
|
POLISHING PADS WITH POLYMER FILLED FIBROUS WEB, AND METHODS FOR FABRICATING AND USING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
06/10/2003
|
Application #:
|
09715559
|
Filing Dt:
|
11/17/2000
|
Title:
|
CHIP INTERCONNECT WIRING STRUCTURE WITH LOW DIELECTRIC CONSTANT INSULATOR AND METHODS FOR FABRICATING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
03/19/2002
|
Application #:
|
09716215
|
Filing Dt:
|
11/21/2000
|
Title:
|
Bright field image reversal for contact hole patterning
|
|
|
Patent #:
|
|
Issue Dt:
|
05/28/2002
|
Application #:
|
09716749
|
Filing Dt:
|
11/20/2000
|
Title:
|
TRENCH-DEFINED SILICON GERMANIUM ESD DIODE NETWORK
|
|
|
Patent #:
|
|
Issue Dt:
|
09/28/2004
|
Application #:
|
09716915
|
Filing Dt:
|
11/20/2000
|
Title:
|
METHOD AND SYSTEM FOR DETECTING A HARD FAILURE IN A MEMORY ARRAY
|
|
|
Patent #:
|
|
Issue Dt:
|
08/31/2004
|
Application #:
|
09716916
|
Filing Dt:
|
11/20/2000
|
Title:
|
FAULT TOLERANT MEMORY SYSTEM UTILIZING MEMORY ARRAYS WITH HARD ERROR DETECTION
|
|