|
|
Patent #:
|
|
Issue Dt:
|
01/27/2015
|
Application #:
|
14151998
|
Filing Dt:
|
01/10/2014
|
Publication #:
|
|
Pub Dt:
|
05/08/2014
| | | | |
Title:
|
EDGE SELECTION TECHNIQUES FOR CORRECTING CLOCK DUTY CYCLE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/15/2016
|
Application #:
|
14152345
|
Filing Dt:
|
01/10/2014
|
Publication #:
|
|
Pub Dt:
|
07/16/2015
| | | | |
Title:
|
CONVERTING AN XY TCAM TO A VALUE TCAM
|
|
|
Patent #:
|
|
Issue Dt:
|
08/04/2015
|
Application #:
|
14152847
|
Filing Dt:
|
01/10/2014
|
Publication #:
|
|
Pub Dt:
|
07/16/2015
| | | | |
Title:
|
BOUNDARY LATCH AND LOGIC PLACEMENT TO SATISFY TIMING CONSTRAINTS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/01/2015
|
Application #:
|
14152907
|
Filing Dt:
|
01/10/2014
|
Publication #:
|
|
Pub Dt:
|
05/08/2014
| | | | |
Title:
|
ELECTROSTATIC DISCHARGE (ESD) PROTECTION USING LOW VISCOSITY ESD DISSIPATING ADHESIVE SUBSTANTIALLY FREE OF AGGLOMERATES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/03/2015
|
Application #:
|
14153145
|
Filing Dt:
|
01/13/2014
|
Publication #:
|
|
Pub Dt:
|
05/08/2014
| | | | |
Title:
|
METHOD AND STRUCTURE OF FORMING BACKSIDE THROUGH SILICON VIA CONNECTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/04/2016
|
Application #:
|
14153728
|
Filing Dt:
|
01/13/2014
|
Publication #:
|
|
Pub Dt:
|
05/08/2014
| | | | |
Title:
|
UNIFORMLY DISTRIBUTED SELF-ASSEMBLED CONE-SHAPED PILLARS FOR HIGH EFFICIENCY SOLAR CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/03/2015
|
Application #:
|
14154202
|
Filing Dt:
|
01/14/2014
|
Publication #:
|
|
Pub Dt:
|
05/08/2014
| | | | |
Title:
|
METHOD AND STRUCTURE FOR FORMING ON-CHIP HIGH QUALITY CAPACITORS WITH ETSOI TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/17/2015
|
Application #:
|
14154247
|
Filing Dt:
|
01/14/2014
|
Publication #:
|
|
Pub Dt:
|
03/26/2015
| | | | |
Title:
|
SPEED OF LIGHT BASED OSCILLATOR FREQUENCY
|
|
|
Patent #:
|
|
Issue Dt:
|
06/23/2015
|
Application #:
|
14154305
|
Filing Dt:
|
01/14/2014
|
Publication #:
|
|
Pub Dt:
|
05/08/2014
| | | | |
Title:
|
INTERCONNECT WITH TITANIUM-OXIDE DIFFUSION BARRIER
|
|
|
Patent #:
|
|
Issue Dt:
|
05/10/2016
|
Application #:
|
14154438
|
Filing Dt:
|
01/14/2014
|
Publication #:
|
|
Pub Dt:
|
05/08/2014
| | | | |
Title:
|
STRUCTURE AND METHOD TO IMPROVE ETSOI MOSFETS WITH BACK GATE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/27/2016
|
Application #:
|
14154505
|
Filing Dt:
|
01/14/2014
|
Publication #:
|
|
Pub Dt:
|
07/16/2015
| | | | |
Title:
|
NON-PLANAR FIELD EFFECT TRANSISTOR TEST STRUCTURE AND LATERAL DIELECTRIC BREAKDOWN TESTING METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
08/11/2015
|
Application #:
|
14154538
|
Filing Dt:
|
01/14/2014
|
Publication #:
|
|
Pub Dt:
|
03/12/2015
| | | | |
Title:
|
SEMICONDUCTOR-ON-INSULATOR DEVICE INCLUDING STAND-ALONE WELL IMPLANT TO PROVIDE JUNCTION BUTTING
|
|
|
Patent #:
|
|
Issue Dt:
|
08/25/2015
|
Application #:
|
14155499
|
Filing Dt:
|
01/15/2014
|
Publication #:
|
|
Pub Dt:
|
07/16/2015
| | | | |
Title:
|
METHODS OF FORMING ISOLATED GERMANIUM-CONTAINING FINS FOR A FINFET SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/08/2016
|
Application #:
|
14155504
|
Filing Dt:
|
01/15/2014
|
Publication #:
|
|
Pub Dt:
|
07/16/2015
| | | | |
Title:
|
DECOUPLING MEASUREMENT OF LAYER THICKNESSES OF A PLURALITY OF LAYERS OF A CIRCUIT STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/17/2015
|
Application #:
|
14155650
|
Filing Dt:
|
01/15/2014
|
Publication #:
|
|
Pub Dt:
|
05/08/2014
| | | | |
Title:
|
ENABLING ACCESS TO A SUBSET OF DATA
|
|
|
Patent #:
|
|
Issue Dt:
|
02/09/2016
|
Application #:
|
14155886
|
Filing Dt:
|
01/15/2014
|
Publication #:
|
|
Pub Dt:
|
07/16/2015
| | | | |
Title:
|
METHOD AND DEVICE FOR AN INTEGRATED TRENCH CAPACITOR
|
|
|
Patent #:
|
|
Issue Dt:
|
07/01/2014
|
Application #:
|
14155972
|
Filing Dt:
|
01/15/2014
|
Publication #:
|
|
Pub Dt:
|
05/08/2014
| | | | |
Title:
|
SEMICONDUCTOR NANOSTRUCTURES, SEMICONDUCTOR DEVICES, AND METHODS OF MAKING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
09/16/2014
|
Application #:
|
14156006
|
Filing Dt:
|
01/15/2014
|
Publication #:
|
|
Pub Dt:
|
05/08/2014
| | | | |
Title:
|
SEMICONDUCTOR NANOSTRUCTURES, SEMICONDUCTOR DEVICES, AND METHODS OF MAKING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
07/07/2015
|
Application #:
|
14156018
|
Filing Dt:
|
01/15/2014
|
Publication #:
|
|
Pub Dt:
|
07/16/2015
| | | | |
Title:
|
MOS TRANSISTOR OPERATED AS OTP CELL WITH GATE DIELECTRIC OPERATING AS AN E-FUSE ELEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
01/12/2016
|
Application #:
|
14156210
|
Filing Dt:
|
01/15/2014
|
Publication #:
|
|
Pub Dt:
|
07/16/2015
| | | | |
Title:
|
MAGNETIC TUNNEL JUNCTION BETWEEN METAL LAYERS OF A SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/30/2016
|
Application #:
|
14156489
|
Filing Dt:
|
01/16/2014
|
Publication #:
|
|
Pub Dt:
|
07/16/2015
| | | | |
Title:
|
LOCAL THINNING OF SEMICONDUCTOR FINS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/06/2017
|
Application #:
|
14156565
|
Filing Dt:
|
01/16/2014
|
Publication #:
|
|
Pub Dt:
|
07/16/2015
| | | | |
Title:
|
MODIFIED TUNNELING FIELD EFFECT TRANSISTORS AND FABRICATION METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/13/2015
|
Application #:
|
14156745
|
Filing Dt:
|
01/16/2014
|
Publication #:
|
|
Pub Dt:
|
07/16/2015
| | | | |
Title:
|
METHOD TO FORM WRAP-AROUND CONTACT FOR FINFET
|
|
|
Patent #:
|
|
Issue Dt:
|
02/10/2015
|
Application #:
|
14157098
|
Filing Dt:
|
01/16/2014
|
Publication #:
|
|
Pub Dt:
|
05/15/2014
| | | | |
Title:
|
METHODS FOR FABRICATION OF AN AIR GAP-CONTAINING INTERCONNECT STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/29/2016
|
Application #:
|
14157755
|
Filing Dt:
|
01/17/2014
|
Publication #:
|
|
Pub Dt:
|
06/05/2014
| | | | |
Title:
|
ELECTRONIC COMPONENTS ON TRENCHED SUBSTRATES AND METHOD OF FORMING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
07/19/2016
|
Application #:
|
14157962
|
Filing Dt:
|
01/17/2014
|
Publication #:
|
|
Pub Dt:
|
07/23/2015
| | | | |
Title:
|
INTEGRATED MICRO-INVERTER AND THIN FILM SOLAR MODULE AND MANUFACTURING PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/23/2016
|
Application #:
|
14158904
|
Filing Dt:
|
01/20/2014
|
Publication #:
|
|
Pub Dt:
|
05/15/2014
| | | | |
Title:
|
METHODS FOR SELECTIVE REVERSE MASK PLANARIZATION AND INTERCONNECT STRUCTURES FORMED THEREBY
|
|
|
Patent #:
|
|
Issue Dt:
|
10/20/2015
|
Application #:
|
14158917
|
Filing Dt:
|
01/20/2014
|
Publication #:
|
|
Pub Dt:
|
07/23/2015
| | | | |
Title:
|
SEMICONDUCTOR DEVICE INCLUDING ENHANCED VARIABILITY
|
|
|
Patent #:
|
|
Issue Dt:
|
02/14/2017
|
Application #:
|
14159027
|
Filing Dt:
|
01/20/2014
|
Publication #:
|
|
Pub Dt:
|
05/15/2014
| | | | |
Title:
|
Structure and Method to Form Passive Devices in ETSOI Process Flow
|
|
|
Patent #:
|
|
Issue Dt:
|
03/01/2016
|
Application #:
|
14160846
|
Filing Dt:
|
01/22/2014
|
Publication #:
|
|
Pub Dt:
|
04/30/2015
| | | | |
Title:
|
APPARATUS AND METHOD TO RECOVER A DATA SIGNAL
|
|
|
Patent #:
|
|
Issue Dt:
|
08/11/2015
|
Application #:
|
14160909
|
Filing Dt:
|
01/22/2014
|
Publication #:
|
|
Pub Dt:
|
05/14/2015
| | | | |
Title:
|
THICK AND THIN DATA VOLUME MANAGEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
08/11/2015
|
Application #:
|
14160918
|
Filing Dt:
|
01/22/2014
|
Publication #:
|
|
Pub Dt:
|
07/23/2015
| | | | |
Title:
|
IDENTIFYING AND MITIGATING ELECTROMIGRATION FAILURES IN SIGNAL NETS OF AN INTEGRATED CIRCUIT CHIP DESIGN
|
|
|
Patent #:
|
|
Issue Dt:
|
11/03/2015
|
Application #:
|
14160927
|
Filing Dt:
|
01/22/2014
|
Publication #:
|
|
Pub Dt:
|
05/14/2015
| | | | |
Title:
|
THICK AND THIN DATA VOLUME MANAGEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
10/13/2015
|
Application #:
|
14161063
|
Filing Dt:
|
01/22/2014
|
Publication #:
|
|
Pub Dt:
|
05/15/2014
| | | | |
Title:
|
CROSS-COUPLING-BASED DESIGN USING DIFFUSION CONTACT STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
08/02/2016
|
Application #:
|
14161228
|
Filing Dt:
|
01/22/2014
|
Publication #:
|
|
Pub Dt:
|
07/23/2015
| | | | |
Title:
|
THROUGH PRINTED CIRCUIT BOARD (PCB) VIAS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/25/2016
|
Application #:
|
14161309
|
Filing Dt:
|
01/22/2014
|
Publication #:
|
|
Pub Dt:
|
07/23/2015
| | | | |
Title:
|
STRUCTURE AND METHOD TO DETERMINE THROUGH SILICON VIA BUILD INTEGRITY
|
|
|
Patent #:
|
|
Issue Dt:
|
06/23/2015
|
Application #:
|
14161721
|
Filing Dt:
|
01/23/2014
|
Title:
|
BI-LAYER GATE CAP FOR SELF-ALIGNED CONTACT FORMATION
|
|
|
Patent #:
|
|
Issue Dt:
|
09/29/2015
|
Application #:
|
14161724
|
Filing Dt:
|
01/23/2014
|
Publication #:
|
|
Pub Dt:
|
07/23/2015
| | | | |
Title:
|
GATE CONTACT WITH VERTICAL ISOLATION FROM SOURCE-DRAIN
|
|
|
Patent #:
|
|
Issue Dt:
|
12/23/2014
|
Application #:
|
14162256
|
Filing Dt:
|
01/23/2014
|
Publication #:
|
|
Pub Dt:
|
05/15/2014
| | | | |
Title:
|
SELF-ALIGNED EMITTER-BASE IN ADVANCED BiCMOS TECHNOLOGY
|
|
|
Patent #:
|
|
Issue Dt:
|
12/29/2015
|
Application #:
|
14162403
|
Filing Dt:
|
01/23/2014
|
Publication #:
|
|
Pub Dt:
|
07/23/2015
| | | | |
Title:
|
SEMICONDUCTOR FINS ON A TRENCH ISOLATION REGION IN A BULK SEMICONDUCTOR SUBSTRATE AND A METHOD OF FORMING THE SEMICONDUCTOR FINS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/13/2015
|
Application #:
|
14162841
|
Filing Dt:
|
01/24/2014
|
Publication #:
|
|
Pub Dt:
|
07/30/2015
| | | | |
Title:
|
STRUCTURE AND METHOD OF FORMING SILICIDE ON FINS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/25/2017
|
Application #:
|
14162904
|
Filing Dt:
|
01/24/2014
|
Publication #:
|
|
Pub Dt:
|
07/30/2015
| | | | |
Title:
|
GATE STRUCTURE CUT AFTER FORMATION OF EPITAXIAL ACTIVE REGIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/24/2018
|
Application #:
|
14162948
|
Filing Dt:
|
01/24/2014
|
Publication #:
|
|
Pub Dt:
|
07/30/2015
| | | | |
Title:
|
MULTIWIDTH FINFET WITH CHANNEL CLADDING
|
|
|
Patent #:
|
|
Issue Dt:
|
03/22/2016
|
Application #:
|
14163511
|
Filing Dt:
|
01/24/2014
|
Publication #:
|
|
Pub Dt:
|
07/30/2015
| | | | |
Title:
|
METHOD AND APPARATUS FOR MODIFIED CELL ARCHITECTURE AND THE RESULTING DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/08/2015
|
Application #:
|
14163687
|
Filing Dt:
|
01/24/2014
|
Publication #:
|
|
Pub Dt:
|
07/30/2015
| | | | |
Title:
|
REPLACEMENT LOW-K SPACER
|
|
|
Patent #:
|
|
Issue Dt:
|
01/26/2016
|
Application #:
|
14164310
|
Filing Dt:
|
01/27/2014
|
Publication #:
|
|
Pub Dt:
|
05/22/2014
| | | | |
Title:
|
INTEGRATED CIRCUIT WITH A THIN BODY FIELD EFFECT TRANSISTOR AND CAPACITOR
|
|
|
Patent #:
|
|
Issue Dt:
|
07/19/2016
|
Application #:
|
14164582
|
Filing Dt:
|
01/27/2014
|
Publication #:
|
|
Pub Dt:
|
07/30/2015
| | | | |
Title:
|
METHODS FOR FABRICATING FINFET INTEGRATED CIRCUITS WITH SIMULTANEOUS FORMATION OF LOCAL CONTACT OPENINGS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/01/2015
|
Application #:
|
14164687
|
Filing Dt:
|
01/27/2014
|
Publication #:
|
|
Pub Dt:
|
07/31/2014
| | | | |
Title:
|
LEVEL-ESTIMATION IN MULTI-LEVEL CELL MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
05/10/2016
|
Application #:
|
14165039
|
Filing Dt:
|
01/27/2014
|
Publication #:
|
|
Pub Dt:
|
07/30/2015
| | | | |
Title:
|
E-FUSE STRUCTURE WITH METHODS OF FUSING THE SAME AND MONITORING MATERIAL LEAKAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/23/2016
|
Application #:
|
14165209
|
Filing Dt:
|
01/27/2014
|
Publication #:
|
|
Pub Dt:
|
07/30/2015
| | | | |
Title:
|
SEMICONDUCTOR DEVICE WITH FEROOELECTRIC HAFNIUM OXIDE AND METHOD FOR FORMING SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/27/2016
|
Application #:
|
14165607
|
Filing Dt:
|
01/28/2014
|
Publication #:
|
|
Pub Dt:
|
01/22/2015
| | | | |
Title:
|
SEGMENTED THIN FILM SOLAR CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/22/2015
|
Application #:
|
14165621
|
Filing Dt:
|
01/28/2014
|
Publication #:
|
|
Pub Dt:
|
01/08/2015
| | | | |
Title:
|
BALL GRID ARRAY CONFIGURATION FOR RELIABLE TESTING
|
|
|
Patent #:
|
|
Issue Dt:
|
10/06/2015
|
Application #:
|
14165633
|
Filing Dt:
|
01/28/2014
|
Publication #:
|
|
Pub Dt:
|
04/23/2015
| | | | |
Title:
|
STORAGE AND RETRIEVAL OF HIGH IMPORTANCE PAGES IN AN ACTIVE MEMORY SHARING ENVIRONMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
02/23/2016
|
Application #:
|
14165762
|
Filing Dt:
|
01/28/2014
|
Publication #:
|
|
Pub Dt:
|
11/27/2014
| | | | |
Title:
|
VALIDATION OF CACHE LOCKING USING INSTRUCTION FETCH AND EXECUTION
|
|
|
Patent #:
|
|
Issue Dt:
|
04/04/2017
|
Application #:
|
14166044
|
Filing Dt:
|
01/28/2014
|
Publication #:
|
|
Pub Dt:
|
07/30/2015
| | | | |
Title:
|
METHOD, COMPUTER SYSTEM AND COMPUTER-READABLE STORAGE MEDIUM FOR CREATING A LAYOUT OF AN INTEGRATED CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
03/07/2017
|
Application #:
|
14166078
|
Filing Dt:
|
01/28/2014
|
Publication #:
|
|
Pub Dt:
|
04/23/2015
| | | | |
Title:
|
PROXIMITY BASED DUAL AUTHENTICATION FOR A WIRELESS NETWORK
|
|
|
Patent #:
|
|
Issue Dt:
|
03/10/2015
|
Application #:
|
14166219
|
Filing Dt:
|
01/28/2014
|
Publication #:
|
|
Pub Dt:
|
05/29/2014
| | | | |
Title:
|
LOCALLY ISOLATED PROTECTED BULK FINFET SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/27/2015
|
Application #:
|
14166274
|
Filing Dt:
|
01/28/2014
|
Publication #:
|
|
Pub Dt:
|
06/05/2014
| | | | |
Title:
|
DUAL-DAMASCENE PROCESS TO FABRICATE THICK WIRE STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/03/2015
|
Application #:
|
14166660
|
Filing Dt:
|
01/28/2014
|
Publication #:
|
|
Pub Dt:
|
07/30/2015
| | | | |
Title:
|
INTEGRATED CIRCUITS WITH METAL-INSULATOR-SEMICONDUCTOR (MIS) CONTACT STRUCTURES AND METHODS FOR FABRICATING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
01/19/2016
|
Application #:
|
14167499
|
Filing Dt:
|
01/29/2014
|
Publication #:
|
|
Pub Dt:
|
05/29/2014
| | | | |
Title:
|
JUNCTION FIELD EFFECT TRANSISTOR WITH AN EPITAXIALLY GROWN GATE STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/22/2016
|
Application #:
|
14167778
|
Filing Dt:
|
01/29/2014
|
Publication #:
|
|
Pub Dt:
|
07/30/2015
| | | | |
Title:
|
IINTEGRATED CIRCUITS WITH DUAL SILICIDE CONTACTS AND METHODS FOR FABRICATING SAME
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14168112
|
Filing Dt:
|
01/30/2014
|
Publication #:
|
|
Pub Dt:
|
07/30/2015
| | | | |
Title:
|
REPLACEMENT METAL GATE INCLUDING DIELECTRIC GATE MATERIAL
|
|
|
Patent #:
|
|
Issue Dt:
|
12/29/2015
|
Application #:
|
14168133
|
Filing Dt:
|
01/30/2014
|
Publication #:
|
|
Pub Dt:
|
07/30/2015
| | | | |
Title:
|
OPTICAL MODEL EMPLOYING PHASE TRANSMISSION VALUES FOR SUB-RESOLUTION ASSIST FEATURES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/30/2015
|
Application #:
|
14168208
|
Filing Dt:
|
01/30/2014
|
Publication #:
|
|
Pub Dt:
|
05/29/2014
| | | | |
Title:
|
INTEGRATED CIRCUIT WITH A THIN BODY FIELD EFFECT TRANSISTOR AND CAPACITOR
|
|
|
Patent #:
|
|
Issue Dt:
|
11/24/2015
|
Application #:
|
14168396
|
Filing Dt:
|
01/30/2014
|
Publication #:
|
|
Pub Dt:
|
07/30/2015
| | | | |
Title:
|
MASK STRUCTURES AND METHODS OF MANUFACTURING
|
|
|
Patent #:
|
|
Issue Dt:
|
03/03/2015
|
Application #:
|
14168471
|
Filing Dt:
|
01/30/2014
|
Publication #:
|
|
Pub Dt:
|
05/29/2014
| | | | |
Title:
|
FIXED CURVATURE FORCE LOADING OF MECHANICALLY SPALLED FILMS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/21/2015
|
Application #:
|
14169318
|
Filing Dt:
|
01/31/2014
|
Publication #:
|
|
Pub Dt:
|
08/06/2015
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURES WITH PAIR(S) OF VERTICAL FIELD EFFECT TRANSISTORS, EACH PAIR HAVING A SHARED SOURCE/DRAIN REGION AND METHODS OF FORMING THE STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/06/2015
|
Application #:
|
14169606
|
Filing Dt:
|
01/31/2014
|
Publication #:
|
|
Pub Dt:
|
05/29/2014
| | | | |
Title:
|
BOND PAD CONFIGURATIONS FOR CONTROLLING SEMICONDUCTOR CHIP PACKAGE INTERACTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/01/2016
|
Application #:
|
14170205
|
Filing Dt:
|
01/31/2014
|
Publication #:
|
|
Pub Dt:
|
04/09/2015
| | | | |
Title:
|
Moving Checkpoint-Based High-Availability Log and Data Directly From a Producer Cache to a Consumer Cache
|
|
|
Patent #:
|
|
Issue Dt:
|
03/03/2015
|
Application #:
|
14170708
|
Filing Dt:
|
02/03/2014
|
Publication #:
|
|
Pub Dt:
|
06/26/2014
| | | | |
Title:
|
TRANSPARENT CONDUCTIVE ELECTRODE STACK CONTAINING CARBON-CONTAINING MATERIAL
|
|
|
Patent #:
|
|
Issue Dt:
|
11/29/2016
|
Application #:
|
14171874
|
Filing Dt:
|
02/04/2014
|
Publication #:
|
|
Pub Dt:
|
08/06/2015
| | | | |
Title:
|
METHOD AND APPARATUS FOR DETECTING FOREIGN MATERIAL ON A CHUCK
|
|
|
Patent #:
|
|
Issue Dt:
|
03/22/2016
|
Application #:
|
14171899
|
Filing Dt:
|
02/04/2014
|
Publication #:
|
|
Pub Dt:
|
03/19/2015
| | | | |
Title:
|
ACCELERATING THE MICROPROCESSOR CORE WAKEUP BY PREDICTIVELY EXECUTING A SUBSET OF THE POWER-UP SEQUENCE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/28/2015
|
Application #:
|
14172058
|
Filing Dt:
|
02/04/2014
|
Publication #:
|
|
Pub Dt:
|
08/06/2015
| | | | |
Title:
|
METHODS OF FORMING GATE STRUCTURES FOR SEMICONDUCTOR DEVICES USING A REPLACEMENT GATE TECHNIQUE AND THE RESULTING DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
08/26/2014
|
Application #:
|
14172135
|
Filing Dt:
|
02/04/2014
|
Publication #:
|
|
Pub Dt:
|
08/14/2014
| | | | |
Title:
|
METHODS OF FORMING A SEMICONDUCTOR DEVICE BY PERFORMING A WET ACID ETCHING PROCESS WHILE PREVENTING OR REDUCING LOSS OF ACTIVE AREA AND/OR ISOLATION REGIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/15/2015
|
Application #:
|
14172323
|
Filing Dt:
|
02/04/2014
|
Publication #:
|
|
Pub Dt:
|
08/06/2015
| | | | |
Title:
|
ETCHING OF UNDER BUMP METTALLIZATION LAYER AND RESULTING DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/21/2016
|
Application #:
|
14172550
|
Filing Dt:
|
02/04/2014
|
Publication #:
|
|
Pub Dt:
|
08/06/2015
| | | | |
Title:
|
TRANSMITTER SERIALIZER LATENCY TRIM
|
|
|
Patent #:
|
|
Issue Dt:
|
10/18/2016
|
Application #:
|
14172618
|
Filing Dt:
|
02/04/2014
|
Publication #:
|
|
Pub Dt:
|
08/06/2015
| | | | |
Title:
|
RECEIVER DESERIALIZER LATENCY TRIM
|
|
|
Patent #:
|
|
Issue Dt:
|
12/08/2015
|
Application #:
|
14172922
|
Filing Dt:
|
02/05/2014
|
Publication #:
|
|
Pub Dt:
|
06/05/2014
| | | | |
Title:
|
AUTOMATIC IDENTIFICATION OF INFORMATION USEFUL FOR GENERATION-BASED FUNCTIONAL VERIFICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
11/17/2015
|
Application #:
|
14173296
|
Filing Dt:
|
02/05/2014
|
Publication #:
|
|
Pub Dt:
|
06/05/2014
| | | | |
Title:
|
SHALLOW TRENCH ISOLATION STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/21/2015
|
Application #:
|
14173995
|
Filing Dt:
|
02/06/2014
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
SEMICONDUCTOR DEVICE INCLUDING A RESISTOR AND METHOD FOR THE FORMATION THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
10/21/2014
|
Application #:
|
14174868
|
Filing Dt:
|
02/07/2014
|
Publication #:
|
|
Pub Dt:
|
06/05/2014
| | | | |
Title:
|
DISLOCATION ENGINEERING USING A SCANNED LASER
|
|
|
Patent #:
|
|
Issue Dt:
|
10/21/2014
|
Application #:
|
14174869
|
Filing Dt:
|
02/07/2014
|
Publication #:
|
|
Pub Dt:
|
06/05/2014
| | | | |
Title:
|
DISLOCATION ENGINEERING USING A SCANNED LASER
|
|
|
Patent #:
|
|
Issue Dt:
|
11/03/2015
|
Application #:
|
14174887
|
Filing Dt:
|
02/07/2014
|
Publication #:
|
|
Pub Dt:
|
06/05/2014
| | | | |
Title:
|
PLATED TRENCH CAPACITOR STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/21/2016
|
Application #:
|
14175113
|
Filing Dt:
|
02/07/2014
|
Publication #:
|
|
Pub Dt:
|
08/13/2015
| | | | |
Title:
|
METHODS OF FORMING A NON-PLANAR ULTRA-THIN BODY SEMICONDUCTOR DEVICE AND THE RESULTING DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
08/02/2016
|
Application #:
|
14175116
|
Filing Dt:
|
02/07/2014
|
Publication #:
|
|
Pub Dt:
|
07/10/2014
| | | | |
Title:
|
A COAXIAL PROBE STRUCTURE OF ELONGATED ELECTRICAL CONDUCTORS PROJECTING FROM A SUPPORT STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/11/2018
|
Application #:
|
14175215
|
Filing Dt:
|
02/07/2014
|
Publication #:
|
|
Pub Dt:
|
08/13/2015
| | | | |
Title:
|
SEMICONDUCTOR DEVICE WITH FINS INCLUDING SIDEWALL RECESSES
|
|
|
Patent #:
|
|
Issue Dt:
|
11/03/2015
|
Application #:
|
14175288
|
Filing Dt:
|
02/07/2014
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
HK/MG PROCESS FLOWS FOR P-TYPE SEMICONDUCTOR DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/25/2016
|
Application #:
|
14175587
|
Filing Dt:
|
02/07/2014
|
Publication #:
|
|
Pub Dt:
|
06/05/2014
| | | | |
Title:
|
METHOD OF FORMING SUBSTRATE CONTACT FOR SEMICONDUCTOR ON INSULATOR (SOI) SUBSTRATE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/07/2016
|
Application #:
|
14175827
|
Filing Dt:
|
02/07/2014
|
Publication #:
|
|
Pub Dt:
|
08/13/2015
| | | | |
Title:
|
FINFET WITH MULTILAYER FINS FOR MULTI-VALUE LOGIC (MVL) APPLICATIONS AND METHOD OF FORMING
|
|
|
Patent #:
|
|
Issue Dt:
|
04/19/2016
|
Application #:
|
14176208
|
Filing Dt:
|
02/10/2014
|
Publication #:
|
|
Pub Dt:
|
01/15/2015
| | | | |
Title:
|
COMPLEX CIRCUIT ELEMENT AND CAPACITOR UTILIZING CMOS COMPATIBLE ANTIFERROELECTRIC HIGH-K MATERIALS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/23/2014
|
Application #:
|
14176460
|
Filing Dt:
|
02/10/2014
|
Publication #:
|
|
Pub Dt:
|
06/05/2014
| | | | |
Title:
|
TAPERED VIA AND MIM CAPACITOR
|
|
|
Patent #:
|
|
Issue Dt:
|
10/27/2015
|
Application #:
|
14176526
|
Filing Dt:
|
02/10/2014
|
Title:
|
TOUGHNESS, ADHESION AND SMOOTH METAL LINES OF POROUS LOW K DIELECTRIC INTERCONNECT STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2015
|
Application #:
|
14176552
|
Filing Dt:
|
02/10/2014
|
Title:
|
SILICON WAVEGUIDE ON BULK SILICON SUBSTRATE AND METHODS OF FORMING
|
|
|
Patent #:
|
|
Issue Dt:
|
10/13/2015
|
Application #:
|
14176697
|
Filing Dt:
|
02/10/2014
|
Publication #:
|
|
Pub Dt:
|
08/13/2015
| | | | |
Title:
|
METHODS FOR ETCHING COPPER DURING THE FABRICATION OF INTEGRATED CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/22/2015
|
Application #:
|
14176767
|
Filing Dt:
|
02/10/2014
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
FINFET DEVICES HAVING A BODY CONTACT AND METHODS OF FORMING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
05/10/2016
|
Application #:
|
14177260
|
Filing Dt:
|
02/11/2014
|
Publication #:
|
|
Pub Dt:
|
08/13/2015
| | | | |
Title:
|
OPTIMIZATION OF A LASER ANNEAL BEAM PATH FOR MAXIMIZING CHIP YIELD
|
|
|
Patent #:
|
|
Issue Dt:
|
07/28/2015
|
Application #:
|
14177481
|
Filing Dt:
|
02/11/2014
|
Publication #:
|
|
Pub Dt:
|
08/13/2015
| | | | |
Title:
|
SELF-ALIGNED LINER FORMED ON METAL SEMICONDUCTOR ALLOY CONTACTS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/12/2016
|
Application #:
|
14177530
|
Filing Dt:
|
02/11/2014
|
Publication #:
|
|
Pub Dt:
|
06/05/2014
| | | | |
Title:
|
Method and Structure to Improve the Conductivity of Narrow Copper Filled Vias
|
|
|
Patent #:
|
|
Issue Dt:
|
11/24/2015
|
Application #:
|
14177800
|
Filing Dt:
|
02/11/2014
|
Publication #:
|
|
Pub Dt:
|
08/13/2015
| | | | |
Title:
|
INTEGRATED CIRCUITS WITH RELAXED SILICON / GERMANIUM FINS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/18/2016
|
Application #:
|
14178955
|
Filing Dt:
|
02/12/2014
|
Publication #:
|
|
Pub Dt:
|
08/13/2015
| | | | |
Title:
|
STRESS BALANCING OF CIRCUITS
|
|