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Reel/Frame:	049490/0001			Pages:	892
		Recorded:	11/29/2018
Conveyance:	SECURITY AGREEMENT

Total properties: 13706
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Patent #:	9231072	Issue Dt:	01/05/2016	Application #:	14179121	Filing Dt:	02/12/2014
Publication #:	US20150228748	Pub Dt:	08/13/2015
Title:	MULTI-COMPOSITION GATE DIELECTRIC FIELD EFFECT TRANSISTORS

Patent #:	8809828	Issue Dt:	08/19/2014	Application #:	14179707	Filing Dt:	02/13/2014
Publication #:	US20140166967	Pub Dt:	06/19/2014
Title:	SMALL FOOTPRINT PHASE CHANGE MEMORY CELL

Patent #:	9411332	Issue Dt:	08/09/2016	Application #:	14180560	Filing Dt:	02/14/2014
Publication #:	US20150234378	Pub Dt:	08/20/2015
Title:	AUTOMATED MECHANICAL HANDLING SYSTEMS FOR INTEGRATED CIRCUIT FABRICATION, SYSTEM COMPUTERS PROGRAMMED FOR USE THEREIN, AND METHODS OF HANDLING A WAFER CARRIER HAVING AN INLET PORT AND AN OUTLET PORT

Patent #:	9343420	Issue Dt:	05/17/2016	Application #:	14181616	Filing Dt:	02/14/2014
Publication #:	US20150235979	Pub Dt:	08/20/2015
Title:	UNIVERSAL SOLDER JOINTS FOR 3D PACKAGING

Patent #:	9236477	Issue Dt:	01/12/2016	Application #:	14181832	Filing Dt:	02/17/2014
Publication #:	US20150236147	Pub Dt:	08/20/2015
Title:	GRAPHENE TRANSISTOR WITH A SUBLITHOGRAPHIC CHANNEL WIDTH

Patent #:	8790980	Issue Dt:	07/29/2014	Application #:	14182242	Filing Dt:	02/17/2014
Publication #:	US20140159113	Pub Dt:	06/12/2014
Title:	IMPLANT DAMAGE CONTROL BY IN-SITU C DOPING DURING SIGE EPITAXY FOR DEVICE APPLICATIONS

Patent #:	9472570	Issue Dt:	10/18/2016	Application #:	14182459	Filing Dt:	02/18/2014
Publication #:	US20150236040	Pub Dt:	08/20/2015
Title:	DIODE BIASED BODY CONTACTED TRANSISTOR

Patent #:	9201027	Issue Dt:	12/01/2015	Application #:	14184058	Filing Dt:	02/19/2014
Publication #:	US20150233844	Pub Dt:	08/20/2015
Title:	EVALUATING SEMICONDUCTOR WAFERS FOR PITCH WALKING AND/OR EPITAXIAL MERGE

Patent #:	9269809	Issue Dt:	02/23/2016	Application #:	14184826	Filing Dt:	02/20/2014
Publication #:	US20140264641	Pub Dt:	09/18/2014
Title:	METHODS FOR FORMING PROTECTION LAYERS ON SIDEWALLS OF CONTACT ETCH STOP LAYERS

Patent #:	9236437	Issue Dt:	01/12/2016	Application #:	14184830	Filing Dt:	02/20/2014
Publication #:	US20150236106	Pub Dt:	08/20/2015
Title:	METHOD FOR CREATING SELF-ALIGNED TRANSISTOR CONTACTS

Patent #:	9262569	Issue Dt:	02/16/2016	Application #:	14185079	Filing Dt:	02/20/2014
Publication #:	US20150234969	Pub Dt:	08/20/2015
Title:	BALANCING SENSITIVITIES WITH RESPECT TO TIMING CLOSURE FOR INTEGRATED CIRCUITS

Patent #:	9257329	Issue Dt:	02/09/2016	Application #:	14185398	Filing Dt:	02/20/2014
Publication #:	US20150235896	Pub Dt:	08/20/2015
Title:	METHODS FOR FABRICATING INTEGRATED CIRCUITS INCLUDING DENSIFYING INTERLEVEL DIELECTRIC LAYERS

Patent #:	9310674	Issue Dt:	04/12/2016	Application #:	14185440	Filing Dt:	02/20/2014
Publication #:	US20150234269	Pub Dt:	08/20/2015
Title:	MASK THAT PROVIDES IMPROVED FOCUS CONTROL USING ORTHOGONAL EDGES

Patent #:	9305800	Issue Dt:	04/05/2016	Application #:	14185491	Filing Dt:	02/20/2014
Publication #:	US20150235839	Pub Dt:	08/20/2015
Title:	METHODS FOR FABRICATING INTEGRATED CIRCUITS USING DIRECTED SELF-ASSEMBLY INCLUDING LITHOGRAPHICALLY-PRINTABLE ASSIST FEATURES

Patent #:	9395622	Issue Dt:	07/19/2016	Application #:	14185506	Filing Dt:	02/20/2014
Publication #:	US20150234970	Pub Dt:	08/20/2015
Title:	SYNTHESIZING LOW MASK ERROR ENHANCEMENT FACTOR LITHOGRAPHY SOLUTIONS

Patent #:	9171765	Issue Dt:	10/27/2015	Application #:	14186012	Filing Dt:	02/21/2014
Publication #:	US20150243568	Pub Dt:	08/27/2015
Title:	INLINE RESIDUAL LAYER DETECTION AND CHARACTERIZATION POST VIA POST ETCH USING CD-SEM

Patent #:	9659840	Issue Dt:	05/23/2017	Application #:	14186360	Filing Dt:	02/21/2014
Publication #:	US20150243582	Pub Dt:	08/27/2015
Title:	NEW PROCESS FLOW FOR A COMBINED CA AND TSV OXIDE DEPOSITION

Patent #:	9287131	Issue Dt:	03/15/2016	Application #:	14186396	Filing Dt:	02/21/2014
Publication #:	US20150243515	Pub Dt:	08/27/2015
Title:	METHODS OF PATTERNING LINE-TYPE FEATURES USING A MULTIPLE PATTERNING PROCESS THAT ENABLES THE USE OF TIGHTER CONTACT ENCLOSURE SPACING RULES

Patent #:	9105650	Issue Dt:	08/11/2015	Application #:	14186512	Filing Dt:	02/21/2014
Publication #:	US20140170829	Pub Dt:	06/19/2014
Title:	LATERAL BIPOLAR TRANSISTOR AND CMOS HYBRID TECHNOLOGY

Patent #:	9105614	Issue Dt:	08/11/2015	Application #:	14187392	Filing Dt:	02/24/2014
Publication #:	US20140167176	Pub Dt:	06/19/2014
Title:	LOCAL INTERCONNECTS COMPATIBLE WITH REPLACEMENT GATE STRUCTURES

Patent #:	9576952	Issue Dt:	02/21/2017	Application #:	14188778	Filing Dt:	02/25/2014
Publication #:	US20150243658	Pub Dt:	08/27/2015
Title:	INTEGRATED CIRCUITS WITH VARYING GATE STRUCTURES AND FABRICATION METHODS

Patent #:	9362180	Issue Dt:	06/07/2016	Application #:	14189085	Filing Dt:	02/25/2014
Publication #:	US20150243563	Pub Dt:	08/27/2015
Title:	INTEGRATED CIRCUIT HAVING MULTIPLE THRESHOLD VOLTAGES

Patent #:	8803284	Issue Dt:	08/12/2014	Application #:	14189108	Filing Dt:	02/25/2014
Publication #:	US20140167219	Pub Dt:	06/19/2014
Title:	Thick On-Chip High-Performance Wiring Structures

Patent #:	9208275	Issue Dt:	12/08/2015	Application #:	14189465	Filing Dt:	02/25/2014
Publication #:	US20150242555	Pub Dt:	08/27/2015
Title:	METHODS FOR FABRICATING INTEGRATED CIRCUITS INCLUDING GENERATING PHOTOMASKS FOR DIRECTED SELF-ASSEMBLY

Patent #:	10546856	Issue Dt:	01/28/2020	Application #:	14189509	Filing Dt:	02/25/2014
Publication #:	US20150243660	Pub Dt:	08/27/2015
Title:	CMOS STRUCTURE HAVING LOW RESISTANCE CONTACTS AND FABRICATION METHOD

Patent #:	9059190	Issue Dt:	06/16/2015	Application #:	14189682	Filing Dt:	02/25/2014
Publication #:	US20140191235	Pub Dt:	07/10/2014
Title:	MEASURING CURRENT AND RESISTANCE USING COMBINED DIODES/RESISTOR STRUCTURE TO MONITOR INTEGRATED CIRCUIT MANUFACTURING PROCESS VARIATIONS

Patent #:	8866257	Issue Dt:	10/21/2014	Application #:	14190514	Filing Dt:	02/26/2014
Publication #:	US20140177373	Pub Dt:	06/26/2014
Title:	SYSTEM INVOLVING ELECTRICALLY REPROGRAMMABLE FUSES

Patent #:	9190465	Issue Dt:	11/17/2015	Application #:	14190611	Filing Dt:	02/26/2014
Publication #:	US20140175549	Pub Dt:	06/26/2014
Title:	FINFET DEVICE

Patent #:	9171125	Issue Dt:	10/27/2015	Application #:	14190723	Filing Dt:	02/26/2014
Publication #:	US20150242560	Pub Dt:	08/27/2015
Title:	LIMITING SKEW BETWEEN DIFFERENT DEVICE TYPES TO MEET PERFORMANCE REQUIREMENTS OF AN INTEGRATED CIRCUIT

Patent #:	8809967	Issue Dt:	08/19/2014	Application #:	14191626	Filing Dt:	02/27/2014
Publication #:	US20140175550	Pub Dt:	06/26/2014
Title:	DEVICE STRUCTURES COMPATIBLE WITH FIN-TYPE FIELD-EFFECT TRANSISTOR TECHNOLOGIES

Patent #:	9221241	Issue Dt:	12/29/2015	Application #:	14191759	Filing Dt:	02/27/2014
Publication #:	US20140174670	Pub Dt:	06/26/2014
Title:	APPARATUS AND METHOD FOR REMOVING A CMP PAD FROM A PLATEN

Patent #:	9177931	Issue Dt:	11/03/2015	Application #:	14191857	Filing Dt:	02/27/2014
Publication #:	US20150243618	Pub Dt:	08/27/2015
Title:	REDUCING THERMAL ENERGY TRANSFER DURING CHIP-JOIN PROCESSING

Patent #:	9490361	Issue Dt:	11/08/2016	Application #:	14192158	Filing Dt:	02/27/2014
Publication #:	US20140175539	Pub Dt:	06/26/2014
Title:	CANYON GATE TRANSISTOR AND METHODS FOR ITS FABRICATION

Patent #:	9040411	Issue Dt:	05/26/2015	Application #:	14194036	Filing Dt:	02/28/2014
Publication #:	US20140179119	Pub Dt:	06/26/2014
Title:	ADVANCED LOW K CAP FILM FORMATION PROCESS FOR NANO ELECTRONIC DEVICES

Patent #:	9230989	Issue Dt:	01/05/2016	Application #:	14194762	Filing Dt:	03/02/2014
Publication #:	US20140175374	Pub Dt:	06/26/2014
Title:	HYBRID CMOS NANOWIRE MESH DEVICE AND FINFET DEVICE

Patent #:	9053981	Issue Dt:	06/09/2015	Application #:	14194766	Filing Dt:	03/02/2014
Publication #:	US20140175375	Pub Dt:	06/26/2014
Title:	HYBRID CMOS NANOWIRE MESH DEVICE AND PDSOI DEVICE

Patent #:	9147730	Issue Dt:	09/29/2015	Application #:	14195344	Filing Dt:	03/03/2014
Publication #:	US20150249127	Pub Dt:	09/03/2015
Title:	METHODS OF FORMING FINS FOR FINFET SEMICONDUCTOR DEVICES AND SELECTIVELY REMOVING SOME OF THE FINS BY PERFORMING A CYCLICAL FIN CUTTING PROCESS

Patent #:	9536877	Issue Dt:	01/03/2017	Application #:	14195484	Filing Dt:	03/03/2014
Publication #:	US20150249036	Pub Dt:	09/03/2015
Title:	METHODS OF FORMING DIFFERENT SPACER STRUCTURES ON INTEGRATED CIRCUIT PRODUCTS HAVING DIFFERING GATE PITCH DIMENSIONS AND THE RESULTING PRODUCTS

Patent #:	NONE	Issue Dt:		Application #:	14195884	Filing Dt:	03/04/2014
Publication #:	US20150255456	Pub Dt:	09/10/2015
Title:	REPLACEMENT FIN ISOLATION IN A SEMICONDUCTOR DEVICE

Patent #:	9330971	Issue Dt:	05/03/2016	Application #:	14195932	Filing Dt:	03/04/2014
Publication #:	US20150255335	Pub Dt:	09/10/2015
Title:	METHOD FOR FABRICATING INTEGRATED CIRCUITS INCLUDING CONTACTS FOR METAL RESISTORS

Patent #:	9171800	Issue Dt:	10/27/2015	Application #:	14195952	Filing Dt:	03/04/2014
Publication #:	US20150255393	Pub Dt:	09/10/2015
Title:	ELECTRICAL FUSE WITH BOTTOM CONTACTS

Patent #:	9343130	Issue Dt:	05/17/2016	Application #:	14196835	Filing Dt:	03/04/2014
Publication #:	US20140185371	Pub Dt:	07/03/2014
Title:	ANTIFERROMAGNETIC STORAGE DEVICE

Patent #:	9209037	Issue Dt:	12/08/2015	Application #:	14196931	Filing Dt:	03/04/2014
Publication #:	US20150255299	Pub Dt:	09/10/2015
Title:	METHODS FOR FABRICATING INTEGRATED CIRCUITS INCLUDING SELECTIVELY FORMING AND REMOVING FIN STRUCTURES

Patent #:	8872274	Issue Dt:	10/28/2014	Application #:	14197762	Filing Dt:	03/05/2014
Publication #:	US20140183637	Pub Dt:	07/03/2014
Title:	STRUCTURE FOR SELF-ALIGNED SILICIDE CONTACTS TO AN UPSIDE-DOWN FET BY EPITAXIAL SOURCE AND DRAIN

Patent #:	9478509	Issue Dt:	10/25/2016	Application #:	14198711	Filing Dt:	03/06/2014
Publication #:	US20150255410	Pub Dt:	09/10/2015
Title:	MECHANICALLY ANCHORED BACKSIDE C4 PAD

Patent #:	9171935	Issue Dt:	10/27/2015	Application #:	14200104	Filing Dt:	03/07/2014
Publication #:	US20150255569	Pub Dt:	09/10/2015
Title:	FINFET FORMATION WITH LATE FIN REVEAL

Patent #:	9312145	Issue Dt:	04/12/2016	Application #:	14200197	Filing Dt:	03/07/2014
Publication #:	US20150255277	Pub Dt:	09/10/2015
Title:	CONFORMAL NITRIDATION OF ONE OR MORE FIN-TYPE TRANSISTOR LAYERS

Patent #:	9269683	Issue Dt:	02/23/2016	Application #:	14200613	Filing Dt:	03/07/2014
Publication #:	US20140187034	Pub Dt:	07/03/2014
Title:	INTEGRATED CIRCUIT CHIP WITH PYRAMID OR CONE-SHAPED CONDUCTIVE PADS FOR FLEXIBLE C4 CONNECTIONS AND A METHOD OF FORMING THE INTEGRATED CIRCUIT CHIP

Patent #:	9412822	Issue Dt:	08/09/2016	Application #:	14200737	Filing Dt:	03/07/2014
Publication #:	US20150255542	Pub Dt:	09/10/2015
Title:	METHODS OF FORMING STRESSED CHANNEL REGIONS FOR A FINFET SEMICONDUCTOR DEVICE AND THE RESULTING DEVICE

Patent #:	9082698	Issue Dt:	07/14/2015	Application #:	14201122	Filing Dt:	03/07/2014
Title:	METHODS TO IMPROVE FINFET SEMICONDUCTOR DEVICE BEHAVIOR USING CO-IMPLANTATION UNDER THE CHANNEL REGION

Patent #:	9236299	Issue Dt:	01/12/2016	Application #:	14201255	Filing Dt:	03/07/2014
Publication #:	US20150255339	Pub Dt:	09/10/2015
Title:	METHODS OF FORMING A METAL CAP LAYER ON COPPER-BASED CONDUCTIVE STRUCTURES ON AN INTEGRATED CIRCUIT DEVICE

Patent #:	9214385	Issue Dt:	12/15/2015	Application #:	14202067	Filing Dt:	03/10/2014
Publication #:	US20140183757	Pub Dt:	07/03/2014
Title:	SEMICONDUCTOR DEVICE INCLUDING PASSIVATION LAYER ENCAPSULANT

Patent #:	9123785	Issue Dt:	09/01/2015	Application #:	14202268	Filing Dt:	03/10/2014
Publication #:	US20150255340	Pub Dt:	09/10/2015
Title:	METHOD TO ETCH CU/TA/TAN SELECTIVELY USING DILUTE AQUEOUS HF/HCL SOLUTION

Patent #:	9224091	Issue Dt:	12/29/2015	Application #:	14202590	Filing Dt:	03/10/2014
Publication #:	US20150254553	Pub Dt:	09/10/2015
Title:	LEARNING ARTIFICIAL NEURAL NETWORK USING TERNARY CONTENT ADDRESSABLE MEMORY (TCAM)

Patent #:	9076688	Issue Dt:	07/07/2015	Application #:	14202675	Filing Dt:	03/10/2014
Title:	SCATTEROMETRY FOR NESTED AND ISOLATED STRUCTURES

Patent #:	8987083	Issue Dt:	03/24/2015	Application #:	14202985	Filing Dt:	03/10/2014
Title:	UNIFORM GATE HEIGHT FOR SEMICONDUCTOR STRUCTURE WITH N AND P TYPE FINS

Patent #:	9436081	Issue Dt:	09/06/2016	Application #:	14205569	Filing Dt:	03/12/2014
Publication #:	US20150261084	Pub Dt:	09/17/2015
Title:	METHODS OF MODIFYING MASKING RETICLES TO REMOVE FORBIDDEN PITCH REGIONS THEREOF

Patent #:	9184288	Issue Dt:	11/10/2015	Application #:	14207822	Filing Dt:	03/13/2014
Publication #:	US20150263169	Pub Dt:	09/17/2015
Title:	SEMICONDUCTOR STRUCTURES WITH BRIDGING FILMS AND METHODS OF FABRICATION

Patent #:	9224811	Issue Dt:	12/29/2015	Application #:	14215398	Filing Dt:	03/17/2014
Publication #:	US20150263088	Pub Dt:	09/17/2015
Title:	STACKED SEMICONDUCTOR DEVICE

Patent #:	9190418	Issue Dt:	11/17/2015	Application #:	14217572	Filing Dt:	03/18/2014
Publication #:	US20150270284	Pub Dt:	09/24/2015
Title:	JUNCTION BUTTING IN SOI TRANSISTOR WITH EMBEDDED SOURCE/DRAIN

Patent #:	9666717	Issue Dt:	05/30/2017	Application #:	14217691	Filing Dt:	03/18/2014
Publication #:	US20150270400	Pub Dt:	09/24/2015
Title:	SPLIT WELL ZERO THRESHOLD VOLTAGE FIELD EFFECT TRANSISTOR FOR INTEGRATED CIRCUITS

Patent #:	10854472	Issue Dt:	12/01/2020	Application #:	14219039	Filing Dt:	03/19/2014
Publication #:	US20150270142	Pub Dt:	09/24/2015
Title:	METHOD FOR FORMING A METAL GATE INCLUDING DE-OXIDATION OF AN OXIDIZED SURFACE OF THE METAL GATE UTILIZING A REDUCING AGENT

Patent #:	9443772	Issue Dt:	09/13/2016	Application #:	14219193	Filing Dt:	03/19/2014
Publication #:	US20150270178	Pub Dt:	09/24/2015
Title:	DIFFUSION-CONTROLLED SEMICONDUCTOR CONTACT CREATION

Patent #:	9553028	Issue Dt:	01/24/2017	Application #:	14219365	Filing Dt:	03/19/2014
Publication #:	US20150270176	Pub Dt:	09/24/2015
Title:	METHODS OF FORMING REDUCED RESISTANCE LOCAL INTERCONNECT STRUCTURES AND THE RESULTING DEVICES

Patent #:	9841773	Issue Dt:	12/12/2017	Application #:	14219460	Filing Dt:	03/19/2014
Publication #:	US20140316605	Pub Dt:	10/23/2014
Title:	Cooling System Management

Patent #:	8963255	Issue Dt:	02/24/2015	Application #:	14219910	Filing Dt:	03/19/2014
Publication #:	US20140203298	Pub Dt:	07/24/2014
Title:	STRAINED SILICON CARBIDE CHANNEL FOR ELECTRON MOBILITY OF NMOS

Patent #:	9064972	Issue Dt:	06/23/2015	Application #:	14220437	Filing Dt:	03/20/2014
Publication #:	US20140206160	Pub Dt:	07/24/2014
Title:	Method of Forming A Gated Diode Structure for Eliminating RIE Damage From Cap Removal

Patent #:	9048171	Issue Dt:	06/02/2015	Application #:	14220475	Filing Dt:	03/20/2014
Publication #:	US20140203405	Pub Dt:	07/24/2014
Title:	METHOD TO DYNAMICALLY TUNE PRECISION RESISTANCE

Patent #:	9178495	Issue Dt:	11/03/2015	Application #:	14221859	Filing Dt:	03/21/2014
Publication #:	US20150270828	Pub Dt:	09/24/2015
Title:	ESTABLISHING A THERMAL PROFILE ACROSS A SEMICONDUCTOR CHIP

Patent #:	8828862	Issue Dt:	09/09/2014	Application #:	14222931	Filing Dt:	03/24/2014
Publication #:	US20140203453	Pub Dt:	07/24/2014
Title:	AIR-DIELECTRIC FOR SUBTRACTIVE ETCH LINE AND VIA METALLIZATION

Patent #:	9236315	Issue Dt:	01/12/2016	Application #:	14222999	Filing Dt:	03/24/2014
Publication #:	US20140203280	Pub Dt:	07/24/2014
Title:	ELECTRICAL TEST STRUCTURE FOR DEVICES EMPLOYING HIGH-K DIELECTRICS OR METAL GATES

Patent #:	9263580	Issue Dt:	02/16/2016	Application #:	14223373	Filing Dt:	03/24/2014
Publication #:	US20150270398	Pub Dt:	09/24/2015
Title:	METHODS OF FORMING ISOLATED CHANNEL REGIONS FOR A FINFET SEMICONDUCTOR DEVICE AND THE RESULTING DEVICE

Patent #:	9064890	Issue Dt:	06/23/2015	Application #:	14223545	Filing Dt:	03/24/2014
Title:	METHODS OF FORMING ISOLATION MATERIAL ON FINFET SEMICONDUCTOR DEVICES AND THE RESULTING DEVICES

Patent #:	9236345	Issue Dt:	01/12/2016	Application #:	14223592	Filing Dt:	03/24/2014
Publication #:	US20150270222	Pub Dt:	09/24/2015
Title:	OXIDE MEDIATED EPITAXIAL NICKEL DISILICIDE ALLOY CONTACT FORMATION

Patent #:	9436845	Issue Dt:	09/06/2016	Application #:	14224099	Filing Dt:	03/25/2014
Publication #:	US20150278551	Pub Dt:	10/01/2015
Title:	PHYSICALLY UNCLONABLE FUSE USING A NOR TYPE MEMORY ARRAY

Patent #:	9323008	Issue Dt:	04/26/2016	Application #:	14224210	Filing Dt:	03/25/2014
Publication #:	US20150277064	Pub Dt:	10/01/2015
Title:	OPTOELECTRONIC STRUCTURES HAVING MULTI-LEVEL OPTICAL WAVEGUIDES AND METHODS OF FORMING THE STRUCTURES

Patent #:	9105718	Issue Dt:	08/11/2015	Application #:	14224384	Filing Dt:	03/25/2014
Publication #:	US20140203359	Pub Dt:	07/24/2014
Title:	BUTTED SOI JUNCTION ISOLATION STRUCTURES AND DEVICES AND METHOD OF FABRICATION

Patent #:	9378093	Issue Dt:	06/28/2016	Application #:	14224431	Filing Dt:	03/25/2014
Publication #:	US20140325262	Pub Dt:	10/30/2014
Title:	CONTROLLING DATA STORAGE IN AN ARRAY OF STORAGE DEVICES

Patent #:	9460963	Issue Dt:	10/04/2016	Application #:	14225529	Filing Dt:	03/26/2014
Publication #:	US20150279738	Pub Dt:	10/01/2015
Title:	SELF-ALIGNED CONTACTS AND METHODS OF FABRICATION

Patent #:	9324854	Issue Dt:	04/26/2016	Application #:	14226176	Filing Dt:	03/26/2014
Publication #:	US20140203339	Pub Dt:	07/24/2014
Title:	SEMICONDUCTOR DEVICE COMPRISING SELF-ALIGNED CONTACT ELEMENTS AND A REPLACEMENT GATE ELECTRODE STRUCTURE

Patent #:	9142651	Issue Dt:	09/22/2015	Application #:	14226488	Filing Dt:	03/26/2014
Publication #:	US20150279963	Pub Dt:	10/01/2015
Title:	METHODS OF FORMING A FINFET SEMICONDUCTOR DEVICE SO AS TO REDUCE PUNCH-THROUGH LEAKAGE CURRENTS AND THE RESULTING DEVICE

Patent #:	8946010	Issue Dt:	02/03/2015	Application #:	14226746	Filing Dt:	03/26/2014
Publication #:	US20140206181	Pub Dt:	07/24/2014
Title:	THREE DIMENSIONAL FET DEVICES HAVING DIFFERENT DEVICE WIDTHS

Patent #:	9586291	Issue Dt:	03/07/2017	Application #:	14226953	Filing Dt:	03/27/2014
Publication #:	US20150035173	Pub Dt:	02/05/2015
Title:	ADHESIVES FOR BONDING HANDLER WAFERS TO DEVICE WAFERS AND ENABLING MID-WAVELENGTH INFRARED LASER ABLATION RELEASE

Patent #:	9105742	Issue Dt:	08/11/2015	Application #:	14227267	Filing Dt:	03/27/2014
Title:	DUAL EPITAXIAL PROCESS INCLUDING SPACER ADJUSTMENT

Patent #:	8850127	Issue Dt:	09/30/2014	Application #:	14227398	Filing Dt:	03/27/2014
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100

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Assignor

GLOBALFOUNDRIES INC.

Exec Dt:

11/27/2018

Assignee

WILMINGTON TRUST, NATIONAL ASSOCIATION

1100 NORTH MARKET STREET

WILMINGTON, DELAWARE 19801

Correspondence name and address
	CT CORPORATION
	4400 EASTON COMMONS WAY
	SUITE 125
	COLUMBUS, OH 43219

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