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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:049490/0001   Pages: 892
Recorded: 11/29/2018
Conveyance: SECURITY AGREEMENT
1
Patent #:
Issue Dt:
12/20/2016
Application #:
14242529
Filing Dt:
04/01/2014
Publication #:
Pub Dt:
10/01/2015
Title:
METHODS OF REMOVING PORTIONS OF FINS BY PREFORMING A SELECTIVELY ETCHABLE MATERIAL IN THE SUBSTRATE
2
Patent #:
Issue Dt:
10/11/2016
Application #:
14243238
Filing Dt:
04/02/2014
Publication #:
Pub Dt:
07/31/2014
Title:
NEAR-INFRARED ABSORBING FILM COMPOSITIONS
3
Patent #:
Issue Dt:
08/09/2016
Application #:
14243295
Filing Dt:
04/02/2014
Publication #:
Pub Dt:
10/08/2015
Title:
ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT WITH A FAIL-SAFE MECHANISM
4
Patent #:
Issue Dt:
02/02/2016
Application #:
14243491
Filing Dt:
04/02/2014
Publication #:
Pub Dt:
10/08/2015
Title:
OVERLAY MARK DEPENDENT DUMMY FILL TO MITIGATE GATE HEIGHT VARIATION
5
Patent #:
Issue Dt:
10/11/2016
Application #:
14244261
Filing Dt:
04/03/2014
Publication #:
Pub Dt:
10/08/2015
Title:
PROCESSES FOR PREPARING INTEGRATED CIRCUITS WITH IMPROVED SOURCE/DRAIN CONTACT STRUCTURES AND INTEGRATED CIRCUITS PREPARED ACCORDING TO SUCH PROCESSES
6
Patent #:
Issue Dt:
05/26/2015
Application #:
14244611
Filing Dt:
04/03/2014
Publication #:
Pub Dt:
08/07/2014
Title:
METHODS FOR FABRICATING INTEGRATED CIRCUITS HAVING GATE TO ACTIVE AND GATE TO GATE INTERCONNECTS
7
Patent #:
Issue Dt:
04/12/2016
Application #:
14244651
Filing Dt:
04/03/2014
Publication #:
Pub Dt:
10/08/2015
Title:
METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH IMPROVED IMPLANTATION PROCESSES
8
Patent #:
Issue Dt:
07/26/2016
Application #:
14245656
Filing Dt:
04/04/2014
Publication #:
Pub Dt:
10/08/2015
Title:
MULTIPLE THRESHOLD VOLTAGE SEMICONDUCTOR DEVICE
9
Patent #:
Issue Dt:
02/28/2017
Application #:
14245868
Filing Dt:
04/04/2014
Publication #:
Pub Dt:
10/08/2015
Title:
METHODS OF GENERATING CIRCUIT LAYOUTS USING SELF-ALLIGNED DOUBLE PATTERNING (SADP) TECHNIQUES
10
Patent #:
Issue Dt:
05/31/2016
Application #:
14246041
Filing Dt:
04/05/2014
Publication #:
Pub Dt:
08/07/2014
Title:
COMPOSITE FILTRATION MEMBRANES AND METHODS OF PREPARATION THEREOF
11
Patent #:
Issue Dt:
10/18/2016
Application #:
14246197
Filing Dt:
04/07/2014
Publication #:
Pub Dt:
10/08/2015
Title:
METHODS OF CROSS-COUPLING LINE SEGMENTS ON A WAFER
12
Patent #:
Issue Dt:
10/31/2017
Application #:
14246376
Filing Dt:
04/07/2014
Publication #:
Pub Dt:
10/23/2014
Title:
POWER NOISE HISTOGRAM OF A COMPUTER SYSTEM
13
Patent #:
Issue Dt:
12/01/2015
Application #:
14246476
Filing Dt:
04/07/2014
Publication #:
Pub Dt:
10/08/2015
Title:
TRANSISTOR CONTACTS SELF-ALIGNED IN TWO DIMENSIONS
14
Patent #:
Issue Dt:
07/21/2015
Application #:
14246546
Filing Dt:
04/07/2014
Publication #:
Pub Dt:
08/07/2014
Title:
STRESS ENGINEERED MULTI-LAYERS FOR INTEGRATION OF CMOS AND Si NANOPHOTONICS
15
Patent #:
Issue Dt:
04/11/2017
Application #:
14246983
Filing Dt:
04/07/2014
Publication #:
Pub Dt:
10/08/2015
Title:
INTEGRATED CIRCUITS AND METHODS OF FABRICATION THEREOF
16
Patent #:
Issue Dt:
11/17/2015
Application #:
14248373
Filing Dt:
04/09/2014
Publication #:
Pub Dt:
10/15/2015
Title:
SOLDER BUMP REFLOW BY INDUCTION HEATING
17
Patent #:
Issue Dt:
06/13/2017
Application #:
14248814
Filing Dt:
04/09/2014
Publication #:
Pub Dt:
10/30/2014
Title:
DISTRIBUTION OF ENCRYPTED INFORMATION IN MULTIPLE LOCATIONS
18
Patent #:
Issue Dt:
12/23/2014
Application #:
14249615
Filing Dt:
04/10/2014
Publication #:
Pub Dt:
08/07/2014
Title:
SYSTEMS AND METHODS FOR MANAGING COMPUTING SYSTEMS UTILIZING AUGMENTED REALITY
19
Patent #:
Issue Dt:
12/22/2015
Application #:
14249619
Filing Dt:
04/10/2014
Publication #:
Pub Dt:
08/07/2014
Title:
SYSTEMS AND METHODS FOR MANAGING COMPUTING SYSTEMS UTILIZING AUGMENTED REALITY
20
Patent #:
Issue Dt:
07/28/2015
Application #:
14249765
Filing Dt:
04/10/2014
Publication #:
Pub Dt:
08/07/2014
Title:
Automatic Generation of Wire Tag Lists for a Metal Stack
21
Patent #:
Issue Dt:
01/06/2015
Application #:
14249893
Filing Dt:
04/10/2014
Publication #:
Pub Dt:
10/23/2014
Title:
DATA WRITING METHOD AND PROGRAM FOR TAPE DRIVE
22
Patent #:
Issue Dt:
11/10/2015
Application #:
14250064
Filing Dt:
04/10/2014
Publication #:
Pub Dt:
10/15/2015
Title:
METHODS OF FORMING FINFET DEVICES IN DIFFERENT REGIONS OF AN INTEGRATED CIRCUIT PRODUCT
23
Patent #:
Issue Dt:
07/12/2016
Application #:
14250425
Filing Dt:
04/11/2014
Publication #:
Pub Dt:
05/21/2015
Title:
COOLING APPARATUS WITH DYNAMIC LOAD ADJUSTMENT
24
Patent #:
Issue Dt:
07/28/2015
Application #:
14250725
Filing Dt:
04/11/2014
Title:
INTEGRATED CIRCUIT STRUCTURE WITH BULK SILICON FINFET AND METHODS OF FORMING
25
Patent #:
Issue Dt:
07/21/2015
Application #:
14250727
Filing Dt:
04/11/2014
Publication #:
Pub Dt:
10/30/2014
Title:
TAPE HEAD WITH THERMAL TAPE-HEAD DISTANCE SENSOR
26
Patent #:
Issue Dt:
12/22/2015
Application #:
14251386
Filing Dt:
04/11/2014
Publication #:
Pub Dt:
02/05/2015
Title:
INCREASED EFFICIENCY OF DATA PAYLOADS TO DATA ARRAYS ACCESSED THROUGH REGISTERS IN A DISTRIBUTED VIRTUAL BRIDGE
27
Patent #:
Issue Dt:
11/29/2016
Application #:
14251402
Filing Dt:
04/11/2014
Publication #:
Pub Dt:
10/15/2015
Title:
STAGGERED ELECTRICAL FRAME STRUCTURES FOR FRAME AREA REDUCTION
28
Patent #:
Issue Dt:
06/14/2016
Application #:
14252447
Filing Dt:
04/14/2014
Publication #:
Pub Dt:
10/15/2015
Title:
DEFECT-FREE RELAXED COVERING LAYER ON SEMICONDUCTOR SUBSTRATE WITH LATTICE MISMATCH
29
Patent #:
Issue Dt:
07/12/2016
Application #:
14253852
Filing Dt:
04/15/2014
Publication #:
Pub Dt:
04/16/2015
Title:
APPARATUS AND METHODS FOR AUTOMATICALLY REFLECTING CHANGES TO A COMPUTING SOLUTION IN AN IMAGE FOR THE COMPUTING SOLUTION
30
Patent #:
Issue Dt:
11/24/2015
Application #:
14253906
Filing Dt:
04/16/2014
Publication #:
Pub Dt:
10/22/2015
Title:
METHODS FOR FABRICATING INTEGRATED CIRCUITS INCLUDING FLUORINE INCORPORATION
31
Patent #:
Issue Dt:
11/24/2015
Application #:
14254710
Filing Dt:
04/16/2014
Publication #:
Pub Dt:
10/22/2015
Title:
TENSILE NITRIDE PROFILE SHAPER ETCH TO PROVIDE VOID FREE GAPFILL
32
Patent #:
Issue Dt:
03/29/2016
Application #:
14254866
Filing Dt:
04/16/2014
Publication #:
Pub Dt:
10/22/2015
Title:
METHODS FOR THE PRODUCTION OF INTEGRATED CIRCUITS COMPRISING EPITAXIALLY GROWN REPLACEMENT STRUCTURES
33
Patent #:
Issue Dt:
02/07/2017
Application #:
14254939
Filing Dt:
04/17/2014
Publication #:
Pub Dt:
08/14/2014
Title:
CHANGING EFFECTIVE WORK FUNCTION USING ION IMPLANTATION DURING DUAL WORK FUNCTION METAL GATE INTEGRATION
34
Patent #:
Issue Dt:
04/07/2015
Application #:
14255037
Filing Dt:
04/17/2014
Publication #:
Pub Dt:
08/14/2014
Title:
ELONGATED VIA STRUCTURES
35
Patent #:
Issue Dt:
11/18/2014
Application #:
14255067
Filing Dt:
04/17/2014
Publication #:
Pub Dt:
08/14/2014
Title:
METHOD OF FORMING A THROUGH-SILICON VIA UTILIZING A METAL CONTACT PAD IN A BACK-END-OF-LINE WIRING LEVEL TO FILL THE THROUGH-SILICON VIA
36
Patent #:
Issue Dt:
11/08/2016
Application #:
14255497
Filing Dt:
04/17/2014
Publication #:
Pub Dt:
12/04/2014
Title:
SELECTIVE PURGING OF A LOG STRUCTURE
37
Patent #:
Issue Dt:
01/19/2016
Application #:
14257143
Filing Dt:
04/21/2014
Publication #:
Pub Dt:
10/22/2015
Title:
PRECISION TRENCH CAPACITOR
38
Patent #:
Issue Dt:
10/04/2016
Application #:
14257236
Filing Dt:
04/21/2014
Publication #:
Pub Dt:
10/30/2014
Title:
PARALLEL DATA PROCESSING
39
Patent #:
Issue Dt:
05/10/2016
Application #:
14257395
Filing Dt:
04/21/2014
Publication #:
Pub Dt:
10/22/2015
Title:
SEMICONDUCTOR MEMORY DEVICE EMPLOYING A FERROMAGNETIC GATE
40
Patent #:
Issue Dt:
10/11/2016
Application #:
14257464
Filing Dt:
04/21/2014
Publication #:
Pub Dt:
10/22/2015
Title:
RECONFIGURABLE BRANCH LINE COUPLER
41
Patent #:
Issue Dt:
01/13/2015
Application #:
14258063
Filing Dt:
04/22/2014
Publication #:
Pub Dt:
08/07/2014
Title:
FINFET STRUCTURE AND METHOD TO ADJUST THRESHOLD VOLTAGE IN A FINFET STRUCTURE
42
Patent #:
NONE
Issue Dt:
Application #:
14258279
Filing Dt:
04/22/2014
Publication #:
Pub Dt:
10/22/2015
Title:
SELF-ALIGNED CONTACT OPENINGS OVER FINS OF A SEMICONDUCTOR DEVICE
43
Patent #:
Issue Dt:
01/12/2016
Application #:
14259179
Filing Dt:
04/23/2014
Publication #:
Pub Dt:
10/29/2015
Title:
FIELD EFFECT TRANSISTOR (FINFET) DEVICE WITH A PLANAR BLOCK AREA TO ENABLE VARIALBLE FIN PITCH AND WIDTH
44
Patent #:
Issue Dt:
08/16/2016
Application #:
14259726
Filing Dt:
04/23/2014
Publication #:
Pub Dt:
10/29/2015
Title:
SOURCE/DRAIN PROFILE ENGINEERING FOR ENHANCED P-MOSFET
45
Patent #:
Issue Dt:
11/03/2015
Application #:
14260399
Filing Dt:
04/24/2014
Publication #:
Pub Dt:
10/29/2015
Title:
CONTACT AND SOLDER BALL INTERCONNECT
46
Patent #:
Issue Dt:
11/24/2015
Application #:
14260913
Filing Dt:
04/24/2014
Publication #:
Pub Dt:
08/21/2014
Title:
INTEGRATED CIRCUITS WITH IMPROVED GATE UNIFORMITY AND METHODS FOR FABRICATING SAME
47
Patent #:
Issue Dt:
12/27/2016
Application #:
14261021
Filing Dt:
04/24/2014
Publication #:
Pub Dt:
10/29/2015
Title:
INTEGRATED CIRCUITS WITH RESISTOR STRUCTURES FORMED FROM GATE METAL AND METHODS FOR FABRICATING SAME
48
Patent #:
Issue Dt:
02/16/2016
Application #:
14261559
Filing Dt:
04/25/2014
Publication #:
Pub Dt:
10/29/2015
Title:
ALTERNATIVE GATE DIELECTRIC FILMS FOR SILICON GERMANIUM AND GERMANIUM CHANNEL MATERIALS
49
Patent #:
Issue Dt:
04/12/2016
Application #:
14261632
Filing Dt:
04/25/2014
Publication #:
Pub Dt:
10/29/2015
Title:
NET-VOLTAGE-AWARE OPTICAL PROXIMITY CORRECTION (OPC)
50
Patent #:
Issue Dt:
05/24/2016
Application #:
14261687
Filing Dt:
04/25/2014
Publication #:
Pub Dt:
08/21/2014
Title:
TEST PAD STRUCTURE FOR REUSE OF INTERCONNECT LEVEL MASKS
51
Patent #:
Issue Dt:
05/02/2017
Application #:
14261823
Filing Dt:
04/25/2014
Publication #:
Pub Dt:
10/29/2015
Title:
SELF-ALIGNED GATE CONTACT FORMATION
52
Patent #:
Issue Dt:
08/15/2017
Application #:
14262882
Filing Dt:
04/28/2014
Publication #:
Pub Dt:
10/29/2015
Title:
FABRICATING FIELD EFFECT TRANSISTOR(S) WITH STRESSED CHANNEL REGION(S) AND LOW-RESISTANCE SOURCE/DRAIN REGIONS
53
Patent #:
Issue Dt:
06/16/2015
Application #:
14263067
Filing Dt:
04/28/2014
Publication #:
Pub Dt:
08/21/2014
Title:
Methodology and Apparatus for Tuning Driving Current of Semiconductor Transistors
54
Patent #:
Issue Dt:
10/25/2016
Application #:
14263329
Filing Dt:
04/28/2014
Publication #:
Pub Dt:
10/29/2015
Title:
MEASURING SETUP AND HOLD TIMES USING A VIRTUAL DELAY
55
Patent #:
Issue Dt:
07/05/2016
Application #:
14263340
Filing Dt:
04/28/2014
Publication #:
Pub Dt:
10/29/2015
Title:
MASK ERROR COMPENSATION BY OPTICAL MODELING CALIBRATION
56
Patent #:
Issue Dt:
12/30/2014
Application #:
14264125
Filing Dt:
04/29/2014
Publication #:
Pub Dt:
08/21/2014
Title:
JUNCTION FIELD EFFECT TRANSISTOR STRUCTURE WITH P-TYPE SILICON GERMANIUM OR SILICON GERMANIUM CARBIDE GATE(S) AND METHOD OF FORMING THE STRUCTURE
57
Patent #:
Issue Dt:
08/25/2015
Application #:
14264163
Filing Dt:
04/29/2014
Title:
METHODS AND STRUCTURES FOR BACK END OF LINE INTEGRATION
58
Patent #:
Issue Dt:
07/21/2015
Application #:
14264179
Filing Dt:
04/29/2014
Title:
FABRICATING FIN-TYPE FIELD EFFECT TRANSISTOR WITH PUNCH-THROUGH STOP REGION
59
Patent #:
Issue Dt:
06/30/2020
Application #:
14264240
Filing Dt:
04/29/2014
Publication #:
Pub Dt:
10/29/2015
Title:
MULTIPLE FIN FINFET WITH LOW-RESISTANCE GATE STRUCTURE
60
Patent #:
Issue Dt:
01/27/2015
Application #:
14265401
Filing Dt:
04/30/2014
Publication #:
Pub Dt:
08/21/2014
Title:
FINFETS AND FIN ISOLATION STRUCTURES
61
Patent #:
Issue Dt:
04/26/2016
Application #:
14265409
Filing Dt:
04/30/2014
Publication #:
Pub Dt:
11/05/2015
Title:
Method For Defining A Default State of a Charge Trap Based Memory Cell
62
Patent #:
Issue Dt:
09/15/2015
Application #:
14265410
Filing Dt:
04/30/2014
Title:
LOW ENERGY ION IMPLANTATION OF A JUNCTION BUTTING REGION
63
Patent #:
Issue Dt:
07/05/2016
Application #:
14265536
Filing Dt:
04/30/2014
Publication #:
Pub Dt:
11/05/2015
Title:
SPACER TO PREVENT SOURCE-DRAIN CONTACT ENCROACHMENT
64
Patent #:
Issue Dt:
02/21/2017
Application #:
14265623
Filing Dt:
04/30/2014
Publication #:
Pub Dt:
08/21/2014
Title:
METHODS AND APPARATUS FOR DETECTION OF GASEOUS CORROSIVE CONTAMINANTS
65
Patent #:
Issue Dt:
08/11/2015
Application #:
14266455
Filing Dt:
04/30/2014
Publication #:
Pub Dt:
12/04/2014
Title:
RUNTIME DYNAMIC PERFORMANCE SKEW ELIMINATION
66
Patent #:
Issue Dt:
09/01/2015
Application #:
14267010
Filing Dt:
05/01/2014
Title:
METHODS OF FORMING ALTERNATIVE MATERIAL FINS WITH REDUCED DEFECT DENSITY FOR A FINFET SEMICONDUCTOR DEVICE
67
Patent #:
Issue Dt:
04/12/2016
Application #:
14267216
Filing Dt:
05/01/2014
Publication #:
Pub Dt:
11/05/2015
Title:
METHODS OF FORMING EPITAXIAL SEMICONDUCTOR MATERIAL IN TRENCHES LOCATED ABOVE THE SOURCE AND DRAIN REGIONS OF A SEMICONDUCTOR DEVICE
68
Patent #:
Issue Dt:
10/17/2017
Application #:
14267541
Filing Dt:
05/01/2014
Publication #:
Pub Dt:
11/05/2015
Title:
Non-Planar Semiconductor Device with Multiple-Head Epitaxial Structure on Fin
69
Patent #:
Issue Dt:
09/29/2015
Application #:
14267555
Filing Dt:
05/01/2014
Title:
METHODS OF FORMING REPLACEMENT SPACER STRUCTURES ON SEMICONDUCTOR DEVICES
70
Patent #:
Issue Dt:
12/08/2015
Application #:
14267959
Filing Dt:
05/02/2014
Publication #:
Pub Dt:
11/05/2015
Title:
METHODS FOR FABRICATING INTEGRATED CIRCUITS USING SELF-ALIGNED QUADRUPLE PATTERNING
71
Patent #:
Issue Dt:
10/04/2016
Application #:
14268277
Filing Dt:
05/02/2014
Publication #:
Pub Dt:
11/05/2015
Title:
MEMORY TESTER DESIGN FOR SOFT ERROR RATE (SER) FAILURE ANALYSIS
72
Patent #:
Issue Dt:
02/16/2016
Application #:
14268415
Filing Dt:
05/02/2014
Publication #:
Pub Dt:
11/05/2015
Title:
METHODS FOR REMOVING SELECTED FINS THAT ARE FORMED FOR FINFET SEMICONDUCTOR DEVICES
73
Patent #:
Issue Dt:
06/23/2015
Application #:
14268478
Filing Dt:
05/02/2014
Title:
METHODS OF FORMING GATE STRUCTURES BY A GATE-CUT-LAST PROCESS AND THE RESULTING STRUCTURES
74
Patent #:
Issue Dt:
10/11/2016
Application #:
14268579
Filing Dt:
05/02/2014
Publication #:
Pub Dt:
11/05/2015
Title:
METHODS OF FORMING A SEMICONDUCTOR DEVICE WITH A SPACER ETCH BLOCK CAP AND THE RESULTING DEVICE
75
Patent #:
Issue Dt:
08/14/2018
Application #:
14269566
Filing Dt:
05/05/2014
Publication #:
Pub Dt:
11/05/2015
Title:
SEMICONDUCTOR DEVICE CONFIGURED FOR AVOIDING ELECTRICAL SHORTING
76
Patent #:
Issue Dt:
05/10/2016
Application #:
14269599
Filing Dt:
05/05/2014
Publication #:
Pub Dt:
11/05/2015
Title:
LOW LEAKAGE, HIGH FREQUENCY DEVICES
77
Patent #:
Issue Dt:
10/18/2016
Application #:
14270824
Filing Dt:
05/06/2014
Publication #:
Pub Dt:
11/12/2015
Title:
METHODS OF FABRICATING INTEGRATED CIRCUITS
78
Patent #:
Issue Dt:
10/18/2016
Application #:
14270833
Filing Dt:
05/06/2014
Publication #:
Pub Dt:
11/12/2015
Title:
FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE INCLUDING A SET OF MERGED FINS FORMED ADJACENT A SET OF UNMERGED FINS
79
Patent #:
Issue Dt:
11/08/2016
Application #:
14270941
Filing Dt:
05/06/2014
Publication #:
Pub Dt:
08/28/2014
Title:
SEMICONDUCTOR DEVICE COMPRISING A STACKED DIE CONFIGURATION INCLUDING AN INTEGRATED PELTIER ELEMENT
80
Patent #:
Issue Dt:
02/02/2016
Application #:
14271515
Filing Dt:
05/07/2014
Publication #:
Pub Dt:
11/12/2015
Title:
METAL-INSULATOR-METAL BACK END OF LINE CAPACITOR STRUCTURES
81
Patent #:
Issue Dt:
07/05/2016
Application #:
14272691
Filing Dt:
05/08/2014
Publication #:
Pub Dt:
11/12/2015
Title:
Sublithographic Kelvin Structure Patterned With DSA
82
Patent #:
Issue Dt:
11/03/2015
Application #:
14272787
Filing Dt:
05/08/2014
Publication #:
Pub Dt:
11/12/2015
Title:
METHODS FOR FABRICATING INTEGRATED CIRCUITS INCLUDING BARRIER LAYERS FOR INTERCONNECT STRUCTURES
83
Patent #:
Issue Dt:
03/29/2016
Application #:
14272916
Filing Dt:
05/08/2014
Publication #:
Pub Dt:
11/12/2015
Title:
INTEGRATED CIRCUITS HAVING MAGNETIC TUNNEL JUNCTIONS (MTJ) AND METHODS FOR FABRICATING THE SAME
84
Patent #:
Issue Dt:
11/08/2016
Application #:
14272952
Filing Dt:
05/08/2014
Publication #:
Pub Dt:
11/12/2015
Title:
INTEGRATED CIRCUITS HAVING IMPROVED GATE STRUCTURES AND METHODS FOR FABRICATING SAME
85
Patent #:
Issue Dt:
08/04/2015
Application #:
14273247
Filing Dt:
05/08/2014
Title:
PERFORMANCE SCREEN RING OSCILLATOR FORMED FROM MULTI-DIMENSIONAL PAIRINGS OF SCAN CHAINS
86
Patent #:
Issue Dt:
05/19/2015
Application #:
14273975
Filing Dt:
05/09/2014
Publication #:
Pub Dt:
11/13/2014
Title:
FORMING SEMICONDUCTOR CHIP CONNECTIONS
87
Patent #:
Issue Dt:
07/12/2016
Application #:
14274042
Filing Dt:
05/09/2014
Publication #:
Pub Dt:
11/12/2015
Title:
METHOD OF INSPECTING A SEMICONDUCTOR SUBSTRATE
88
Patent #:
Issue Dt:
03/22/2016
Application #:
14274406
Filing Dt:
05/09/2014
Publication #:
Pub Dt:
11/12/2015
Title:
METHODS OF FORMING SEMICONDUCTOR DEVICES INCLUDING AN ELECTRICALLY-DECOUPLED FIN
89
Patent #:
Issue Dt:
06/16/2015
Application #:
14274962
Filing Dt:
05/12/2014
Publication #:
Pub Dt:
09/04/2014
Title:
DOPING OF COPPER WIRING STRUCTURES IN BACK END OF LINE PROCESSING
90
Patent #:
Issue Dt:
12/29/2015
Application #:
14275448
Filing Dt:
05/12/2014
Publication #:
Pub Dt:
11/12/2015
Title:
INTEGRATED CIRCUITS WITH METAL-TITANIUM OXIDE CONTACTS AND FABRICATION METHODS
91
Patent #:
Issue Dt:
04/14/2015
Application #:
14275688
Filing Dt:
05/12/2014
Publication #:
Pub Dt:
09/04/2014
Title:
RETICLE DEFECT CORRECTION BY SECOND EXPOSURE
92
Patent #:
Issue Dt:
08/02/2016
Application #:
14276025
Filing Dt:
05/13/2014
Publication #:
Pub Dt:
11/19/2015
Title:
Stacked Memory Device Control
93
Patent #:
Issue Dt:
05/10/2016
Application #:
14276360
Filing Dt:
05/13/2014
Publication #:
Pub Dt:
11/06/2014
Title:
INTERCONNECT STRUCTURE AND METHOD OF MAKING SAME
94
Patent #:
Issue Dt:
03/01/2016
Application #:
14278689
Filing Dt:
05/15/2014
Publication #:
Pub Dt:
11/19/2015
Title:
WAVEGUIDE DEVICES WITH SUPPORTING ANCHORS
95
Patent #:
Issue Dt:
10/13/2015
Application #:
14278974
Filing Dt:
05/15/2014
Title:
REDUCING COLOR CONFLICTS IN TRIPLE PATTERNING LITHOGRAPHY
96
Patent #:
Issue Dt:
03/29/2016
Application #:
14280998
Filing Dt:
05/19/2014
Publication #:
Pub Dt:
11/19/2015
Title:
METHOD FOR MAKING SEMICONDUCTOR DEVICE WITH DIFFERENT FIN SETS
97
Patent #:
Issue Dt:
05/16/2017
Application #:
14281021
Filing Dt:
05/19/2014
Publication #:
Pub Dt:
11/19/2015
Title:
METHOD FOR MAKING SEMICONDUCTOR DEVICE WITH FILLED GATE LINE END RECESSES
98
Patent #:
Issue Dt:
10/07/2014
Application #:
14281192
Filing Dt:
05/19/2014
Publication #:
Pub Dt:
09/11/2014
Title:
SELF ALIGNED FIN-TYPE PROGRAMMABLE MEMORY CELL
99
Patent #:
Issue Dt:
09/22/2015
Application #:
14281726
Filing Dt:
05/19/2014
Title:
DOUBLE/MULTIPLE FIN STRUCTURE FOR FINFET DEVICES
100
Patent #:
Issue Dt:
05/01/2018
Application #:
14282089
Filing Dt:
05/20/2014
Publication #:
Pub Dt:
11/26/2015
Title:
MERGED GATE AND SOURCE/DRAIN CONTACTS IN A SEMICONDUCTOR DEVICE
Assignor
1
Exec Dt:
11/27/2018
Assignee
1
1100 NORTH MARKET STREET
WILMINGTON, DELAWARE 19801
Correspondence name and address
CT CORPORATION
4400 EASTON COMMONS WAY
SUITE 125
COLUMBUS, OH 43219

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