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12/20/2016
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10/01/2015
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10/11/2016
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07/31/2014
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08/09/2016
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14243295
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04/02/2014
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10/08/2015
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02/02/2016
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14243491
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04/02/2014
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10/08/2015
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10/11/2016
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14244261
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04/03/2014
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10/08/2015
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05/26/2015
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04/03/2014
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08/07/2014
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04/12/2016
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14244651
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04/03/2014
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10/08/2015
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07/26/2016
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04/04/2014
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10/08/2015
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MULTIPLE THRESHOLD VOLTAGE SEMICONDUCTOR DEVICE
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02/28/2017
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04/04/2014
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10/08/2015
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05/31/2016
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04/05/2014
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08/07/2014
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10/18/2016
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04/07/2014
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10/08/2015
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10/31/2017
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04/07/2014
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10/23/2014
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12/01/2015
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14246476
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04/07/2014
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10/08/2015
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TRANSISTOR CONTACTS SELF-ALIGNED IN TWO DIMENSIONS
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07/21/2015
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14246546
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04/07/2014
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08/07/2014
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STRESS ENGINEERED MULTI-LAYERS FOR INTEGRATION OF CMOS AND Si NANOPHOTONICS
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04/11/2017
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04/07/2014
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10/08/2015
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INTEGRATED CIRCUITS AND METHODS OF FABRICATION THEREOF
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11/17/2015
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04/09/2014
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10/15/2015
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SOLDER BUMP REFLOW BY INDUCTION HEATING
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06/13/2017
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04/09/2014
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10/30/2014
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DISTRIBUTION OF ENCRYPTED INFORMATION IN MULTIPLE LOCATIONS
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12/23/2014
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14249615
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04/10/2014
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08/07/2014
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12/22/2015
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14249619
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04/10/2014
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08/07/2014
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SYSTEMS AND METHODS FOR MANAGING COMPUTING SYSTEMS UTILIZING AUGMENTED REALITY
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07/28/2015
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14249765
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04/10/2014
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08/07/2014
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Automatic Generation of Wire Tag Lists for a Metal Stack
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01/06/2015
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14249893
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04/10/2014
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10/23/2014
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DATA WRITING METHOD AND PROGRAM FOR TAPE DRIVE
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11/10/2015
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14250064
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04/10/2014
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10/15/2015
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07/12/2016
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14250425
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04/11/2014
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05/21/2015
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COOLING APPARATUS WITH DYNAMIC LOAD ADJUSTMENT
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07/28/2015
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14250725
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04/11/2014
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07/21/2015
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14250727
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04/11/2014
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10/30/2014
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TAPE HEAD WITH THERMAL TAPE-HEAD DISTANCE SENSOR
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12/22/2015
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14251386
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04/11/2014
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02/05/2015
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INCREASED EFFICIENCY OF DATA PAYLOADS TO DATA ARRAYS ACCESSED THROUGH REGISTERS IN A DISTRIBUTED VIRTUAL BRIDGE
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11/29/2016
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14251402
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04/11/2014
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10/15/2015
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STAGGERED ELECTRICAL FRAME STRUCTURES FOR FRAME AREA REDUCTION
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06/14/2016
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14252447
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04/14/2014
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10/15/2015
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DEFECT-FREE RELAXED COVERING LAYER ON SEMICONDUCTOR SUBSTRATE WITH LATTICE MISMATCH
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07/12/2016
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14253852
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04/15/2014
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04/16/2015
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11/24/2015
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14253906
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04/16/2014
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10/22/2015
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11/24/2015
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14254710
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04/16/2014
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10/22/2015
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TENSILE NITRIDE PROFILE SHAPER ETCH TO PROVIDE VOID FREE GAPFILL
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03/29/2016
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14254866
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04/16/2014
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10/22/2015
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METHODS FOR THE PRODUCTION OF INTEGRATED CIRCUITS COMPRISING EPITAXIALLY GROWN REPLACEMENT STRUCTURES
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02/07/2017
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04/17/2014
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08/14/2014
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CHANGING EFFECTIVE WORK FUNCTION USING ION IMPLANTATION DURING DUAL WORK FUNCTION METAL GATE INTEGRATION
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04/07/2015
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04/17/2014
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08/14/2014
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ELONGATED VIA STRUCTURES
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11/18/2014
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04/17/2014
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08/14/2014
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11/08/2016
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04/17/2014
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12/04/2014
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01/19/2016
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04/21/2014
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10/22/2015
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PRECISION TRENCH CAPACITOR
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10/04/2016
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04/21/2014
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10/30/2014
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PARALLEL DATA PROCESSING
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05/10/2016
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04/21/2014
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10/22/2015
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10/11/2016
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04/21/2014
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10/22/2015
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01/13/2015
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04/22/2014
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08/07/2014
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FINFET STRUCTURE AND METHOD TO ADJUST THRESHOLD VOLTAGE IN A FINFET STRUCTURE
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04/22/2014
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10/22/2015
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SELF-ALIGNED CONTACT OPENINGS OVER FINS OF A SEMICONDUCTOR DEVICE
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01/12/2016
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04/23/2014
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10/29/2015
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08/16/2016
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04/23/2014
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10/29/2015
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SOURCE/DRAIN PROFILE ENGINEERING FOR ENHANCED P-MOSFET
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11/03/2015
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14260399
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04/24/2014
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10/29/2015
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CONTACT AND SOLDER BALL INTERCONNECT
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11/24/2015
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14260913
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04/24/2014
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08/21/2014
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INTEGRATED CIRCUITS WITH IMPROVED GATE UNIFORMITY AND METHODS FOR FABRICATING SAME
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12/27/2016
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14261021
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04/24/2014
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10/29/2015
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02/16/2016
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04/25/2014
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10/29/2015
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ALTERNATIVE GATE DIELECTRIC FILMS FOR SILICON GERMANIUM AND GERMANIUM CHANNEL MATERIALS
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04/12/2016
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14261632
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04/25/2014
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10/29/2015
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NET-VOLTAGE-AWARE OPTICAL PROXIMITY CORRECTION (OPC)
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05/24/2016
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14261687
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04/25/2014
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08/21/2014
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TEST PAD STRUCTURE FOR REUSE OF INTERCONNECT LEVEL MASKS
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05/02/2017
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14261823
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04/25/2014
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10/29/2015
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SELF-ALIGNED GATE CONTACT FORMATION
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08/15/2017
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04/28/2014
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10/29/2015
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FABRICATING FIELD EFFECT TRANSISTOR(S) WITH STRESSED CHANNEL REGION(S) AND LOW-RESISTANCE SOURCE/DRAIN REGIONS
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06/16/2015
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04/28/2014
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08/21/2014
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Methodology and Apparatus for Tuning Driving Current of Semiconductor Transistors
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10/25/2016
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14263329
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04/28/2014
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10/29/2015
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MEASURING SETUP AND HOLD TIMES USING A VIRTUAL DELAY
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07/05/2016
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14263340
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04/28/2014
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10/29/2015
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MASK ERROR COMPENSATION BY OPTICAL MODELING CALIBRATION
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12/30/2014
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14264125
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04/29/2014
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08/21/2014
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JUNCTION FIELD EFFECT TRANSISTOR STRUCTURE WITH P-TYPE SILICON GERMANIUM OR SILICON GERMANIUM CARBIDE GATE(S) AND METHOD OF FORMING THE STRUCTURE
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08/25/2015
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14264163
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04/29/2014
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METHODS AND STRUCTURES FOR BACK END OF LINE INTEGRATION
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07/21/2015
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14264179
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04/29/2014
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Title:
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FABRICATING FIN-TYPE FIELD EFFECT TRANSISTOR WITH PUNCH-THROUGH STOP REGION
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Patent #:
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Issue Dt:
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06/30/2020
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Application #:
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14264240
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Filing Dt:
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04/29/2014
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Publication #:
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Pub Dt:
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10/29/2015
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Title:
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MULTIPLE FIN FINFET WITH LOW-RESISTANCE GATE STRUCTURE
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Patent #:
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Issue Dt:
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01/27/2015
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Application #:
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14265401
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Filing Dt:
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04/30/2014
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Publication #:
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Pub Dt:
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08/21/2014
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Title:
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FINFETS AND FIN ISOLATION STRUCTURES
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Patent #:
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Issue Dt:
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04/26/2016
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Application #:
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14265409
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Filing Dt:
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04/30/2014
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Publication #:
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Pub Dt:
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11/05/2015
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Title:
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Method For Defining A Default State of a Charge Trap Based Memory Cell
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Patent #:
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Issue Dt:
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09/15/2015
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Application #:
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14265410
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Filing Dt:
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04/30/2014
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Title:
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LOW ENERGY ION IMPLANTATION OF A JUNCTION BUTTING REGION
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Patent #:
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Issue Dt:
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07/05/2016
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Application #:
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14265536
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Filing Dt:
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04/30/2014
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Publication #:
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Pub Dt:
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11/05/2015
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Title:
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SPACER TO PREVENT SOURCE-DRAIN CONTACT ENCROACHMENT
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Patent #:
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Issue Dt:
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02/21/2017
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Application #:
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14265623
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Filing Dt:
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04/30/2014
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Publication #:
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Pub Dt:
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08/21/2014
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Title:
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METHODS AND APPARATUS FOR DETECTION OF GASEOUS CORROSIVE CONTAMINANTS
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Patent #:
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Issue Dt:
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08/11/2015
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Application #:
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14266455
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Filing Dt:
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04/30/2014
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Publication #:
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Pub Dt:
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12/04/2014
| | | | |
Title:
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RUNTIME DYNAMIC PERFORMANCE SKEW ELIMINATION
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Patent #:
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Issue Dt:
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09/01/2015
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Application #:
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14267010
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Filing Dt:
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05/01/2014
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Title:
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METHODS OF FORMING ALTERNATIVE MATERIAL FINS WITH REDUCED DEFECT DENSITY FOR A FINFET SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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04/12/2016
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Application #:
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14267216
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Filing Dt:
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05/01/2014
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Publication #:
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Pub Dt:
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11/05/2015
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Title:
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METHODS OF FORMING EPITAXIAL SEMICONDUCTOR MATERIAL IN TRENCHES LOCATED ABOVE THE SOURCE AND DRAIN REGIONS OF A SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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10/17/2017
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Application #:
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14267541
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Filing Dt:
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05/01/2014
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Publication #:
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Pub Dt:
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11/05/2015
| | | | |
Title:
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Non-Planar Semiconductor Device with Multiple-Head Epitaxial Structure on Fin
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Patent #:
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Issue Dt:
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09/29/2015
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Application #:
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14267555
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Filing Dt:
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05/01/2014
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Title:
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METHODS OF FORMING REPLACEMENT SPACER STRUCTURES ON SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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12/08/2015
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Application #:
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14267959
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Filing Dt:
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05/02/2014
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Publication #:
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Pub Dt:
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11/05/2015
| | | | |
Title:
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METHODS FOR FABRICATING INTEGRATED CIRCUITS USING SELF-ALIGNED QUADRUPLE PATTERNING
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Patent #:
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Issue Dt:
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10/04/2016
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Application #:
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14268277
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Filing Dt:
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05/02/2014
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Publication #:
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Pub Dt:
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11/05/2015
| | | | |
Title:
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MEMORY TESTER DESIGN FOR SOFT ERROR RATE (SER) FAILURE ANALYSIS
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Patent #:
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Issue Dt:
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02/16/2016
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Application #:
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14268415
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Filing Dt:
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05/02/2014
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Publication #:
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Pub Dt:
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11/05/2015
| | | | |
Title:
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METHODS FOR REMOVING SELECTED FINS THAT ARE FORMED FOR FINFET SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
|
06/23/2015
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Application #:
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14268478
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Filing Dt:
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05/02/2014
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Title:
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METHODS OF FORMING GATE STRUCTURES BY A GATE-CUT-LAST PROCESS AND THE RESULTING STRUCTURES
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Patent #:
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Issue Dt:
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10/11/2016
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Application #:
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14268579
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Filing Dt:
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05/02/2014
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Publication #:
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Pub Dt:
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11/05/2015
| | | | |
Title:
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METHODS OF FORMING A SEMICONDUCTOR DEVICE WITH A SPACER ETCH BLOCK CAP AND THE RESULTING DEVICE
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Patent #:
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Issue Dt:
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08/14/2018
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Application #:
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14269566
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Filing Dt:
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05/05/2014
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Publication #:
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Pub Dt:
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11/05/2015
| | | | |
Title:
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SEMICONDUCTOR DEVICE CONFIGURED FOR AVOIDING ELECTRICAL SHORTING
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Patent #:
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Issue Dt:
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05/10/2016
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Application #:
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14269599
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Filing Dt:
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05/05/2014
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Publication #:
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Pub Dt:
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11/05/2015
| | | | |
Title:
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LOW LEAKAGE, HIGH FREQUENCY DEVICES
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Patent #:
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Issue Dt:
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10/18/2016
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Application #:
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14270824
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Filing Dt:
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05/06/2014
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Publication #:
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Pub Dt:
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11/12/2015
| | | | |
Title:
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METHODS OF FABRICATING INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
|
10/18/2016
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Application #:
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14270833
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Filing Dt:
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05/06/2014
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Publication #:
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Pub Dt:
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11/12/2015
| | | | |
Title:
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FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE INCLUDING A SET OF MERGED FINS FORMED ADJACENT A SET OF UNMERGED FINS
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Patent #:
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Issue Dt:
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11/08/2016
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Application #:
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14270941
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Filing Dt:
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05/06/2014
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Publication #:
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Pub Dt:
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08/28/2014
| | | | |
Title:
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SEMICONDUCTOR DEVICE COMPRISING A STACKED DIE CONFIGURATION INCLUDING AN INTEGRATED PELTIER ELEMENT
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Patent #:
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Issue Dt:
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02/02/2016
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Application #:
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14271515
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Filing Dt:
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05/07/2014
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Publication #:
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Pub Dt:
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11/12/2015
| | | | |
Title:
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METAL-INSULATOR-METAL BACK END OF LINE CAPACITOR STRUCTURES
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Patent #:
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Issue Dt:
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07/05/2016
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Application #:
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14272691
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Filing Dt:
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05/08/2014
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Publication #:
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Pub Dt:
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11/12/2015
| | | | |
Title:
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Sublithographic Kelvin Structure Patterned With DSA
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Patent #:
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Issue Dt:
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11/03/2015
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Application #:
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14272787
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Filing Dt:
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05/08/2014
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Publication #:
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Pub Dt:
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11/12/2015
| | | | |
Title:
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METHODS FOR FABRICATING INTEGRATED CIRCUITS INCLUDING BARRIER LAYERS FOR INTERCONNECT STRUCTURES
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Patent #:
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Issue Dt:
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03/29/2016
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Application #:
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14272916
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Filing Dt:
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05/08/2014
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Publication #:
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Pub Dt:
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11/12/2015
| | | | |
Title:
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INTEGRATED CIRCUITS HAVING MAGNETIC TUNNEL JUNCTIONS (MTJ) AND METHODS FOR FABRICATING THE SAME
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Patent #:
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Issue Dt:
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11/08/2016
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Application #:
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14272952
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Filing Dt:
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05/08/2014
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Publication #:
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Pub Dt:
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11/12/2015
| | | | |
Title:
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INTEGRATED CIRCUITS HAVING IMPROVED GATE STRUCTURES AND METHODS FOR FABRICATING SAME
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Patent #:
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Issue Dt:
|
08/04/2015
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Application #:
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14273247
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Filing Dt:
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05/08/2014
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Title:
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PERFORMANCE SCREEN RING OSCILLATOR FORMED FROM MULTI-DIMENSIONAL PAIRINGS OF SCAN CHAINS
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Patent #:
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Issue Dt:
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05/19/2015
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Application #:
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14273975
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Filing Dt:
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05/09/2014
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Publication #:
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Pub Dt:
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11/13/2014
| | | | |
Title:
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FORMING SEMICONDUCTOR CHIP CONNECTIONS
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Patent #:
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Issue Dt:
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07/12/2016
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Application #:
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14274042
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Filing Dt:
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05/09/2014
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Publication #:
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Pub Dt:
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11/12/2015
| | | | |
Title:
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METHOD OF INSPECTING A SEMICONDUCTOR SUBSTRATE
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Patent #:
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Issue Dt:
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03/22/2016
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Application #:
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14274406
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Filing Dt:
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05/09/2014
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Publication #:
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Pub Dt:
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11/12/2015
| | | | |
Title:
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METHODS OF FORMING SEMICONDUCTOR DEVICES INCLUDING AN ELECTRICALLY-DECOUPLED FIN
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Patent #:
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Issue Dt:
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06/16/2015
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Application #:
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14274962
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Filing Dt:
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05/12/2014
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Publication #:
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Pub Dt:
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09/04/2014
| | | | |
Title:
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DOPING OF COPPER WIRING STRUCTURES IN BACK END OF LINE PROCESSING
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Patent #:
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Issue Dt:
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12/29/2015
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Application #:
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14275448
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Filing Dt:
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05/12/2014
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Publication #:
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Pub Dt:
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11/12/2015
| | | | |
Title:
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INTEGRATED CIRCUITS WITH METAL-TITANIUM OXIDE CONTACTS AND FABRICATION METHODS
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Patent #:
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Issue Dt:
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04/14/2015
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Application #:
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14275688
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Filing Dt:
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05/12/2014
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Publication #:
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Pub Dt:
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09/04/2014
| | | | |
Title:
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RETICLE DEFECT CORRECTION BY SECOND EXPOSURE
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Patent #:
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Issue Dt:
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08/02/2016
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Application #:
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14276025
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Filing Dt:
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05/13/2014
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Publication #:
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Pub Dt:
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11/19/2015
| | | | |
Title:
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Stacked Memory Device Control
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Patent #:
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Issue Dt:
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05/10/2016
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Application #:
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14276360
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Filing Dt:
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05/13/2014
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Publication #:
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Pub Dt:
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11/06/2014
| | | | |
Title:
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INTERCONNECT STRUCTURE AND METHOD OF MAKING SAME
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Patent #:
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Issue Dt:
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03/01/2016
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Application #:
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14278689
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Filing Dt:
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05/15/2014
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Publication #:
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Pub Dt:
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11/19/2015
| | | | |
Title:
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WAVEGUIDE DEVICES WITH SUPPORTING ANCHORS
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Patent #:
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Issue Dt:
|
10/13/2015
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Application #:
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14278974
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Filing Dt:
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05/15/2014
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Title:
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REDUCING COLOR CONFLICTS IN TRIPLE PATTERNING LITHOGRAPHY
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Patent #:
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Issue Dt:
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03/29/2016
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Application #:
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14280998
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Filing Dt:
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05/19/2014
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Publication #:
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Pub Dt:
|
11/19/2015
| | | | |
Title:
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METHOD FOR MAKING SEMICONDUCTOR DEVICE WITH DIFFERENT FIN SETS
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Patent #:
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Issue Dt:
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05/16/2017
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Application #:
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14281021
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Filing Dt:
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05/19/2014
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Publication #:
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Pub Dt:
|
11/19/2015
| | | | |
Title:
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METHOD FOR MAKING SEMICONDUCTOR DEVICE WITH FILLED GATE LINE END RECESSES
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Patent #:
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Issue Dt:
|
10/07/2014
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Application #:
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14281192
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Filing Dt:
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05/19/2014
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Publication #:
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Pub Dt:
|
09/11/2014
| | | | |
Title:
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SELF ALIGNED FIN-TYPE PROGRAMMABLE MEMORY CELL
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Patent #:
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Issue Dt:
|
09/22/2015
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Application #:
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14281726
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Filing Dt:
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05/19/2014
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Title:
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DOUBLE/MULTIPLE FIN STRUCTURE FOR FINFET DEVICES
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Patent #:
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Issue Dt:
|
05/01/2018
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Application #:
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14282089
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Filing Dt:
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05/20/2014
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Publication #:
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Pub Dt:
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11/26/2015
| | | | |
Title:
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MERGED GATE AND SOURCE/DRAIN CONTACTS IN A SEMICONDUCTOR DEVICE
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