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05/31/2016
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14282143
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05/20/2014
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11/27/2014
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03/28/2017
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11/26/2015
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02/09/2016
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11/26/2015
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04/19/2016
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05/21/2014
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11/26/2015
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11/17/2015
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05/21/2014
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09/11/2014
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08/30/2016
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14283667
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05/21/2014
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11/26/2015
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04/21/2015
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05/21/2014
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09/11/2014
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07/05/2016
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05/21/2014
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11/26/2015
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07/07/2015
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05/22/2014
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09/11/2014
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01/03/2017
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05/22/2014
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11/26/2015
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06/27/2017
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11/26/2015
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03/14/2017
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11/26/2015
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RECONFIGURABLE BANDSTOP FILTER
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10/04/2016
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05/22/2014
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11/26/2015
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03/15/2016
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05/23/2014
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11/26/2015
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08/11/2015
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05/23/2014
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09/11/2014
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04/19/2016
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05/23/2014
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12/04/2014
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Temperature Triggering Ejector Mechanism for Lock Pin Soldering Type Component
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04/28/2015
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05/23/2014
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09/25/2014
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INTERLEVEL DIELECTRIC STACK FOR INTERCONNECT STRUCTURES
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12/01/2015
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05/23/2014
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11/26/2015
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03/31/2015
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05/23/2014
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09/11/2014
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05/03/2016
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05/23/2014
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11/26/2015
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01/12/2016
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05/23/2014
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11/26/2015
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05/26/2015
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05/23/2014
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09/11/2014
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Structure and Method of Fabricating a CZTS Photovoltaic Device by Electrodeposition
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07/19/2016
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05/27/2014
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12/04/2014
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FLUID-COOLED ELECTRONIC CIRCUIT DEVICE WITH COOLING FLUID CONDUITS HAVING OPTICAL TRANSMISSION MEDIUM
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07/07/2015
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05/27/2014
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09/18/2014
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12/22/2015
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05/27/2014
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09/25/2014
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05/26/2015
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05/27/2014
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09/18/2014
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07/11/2017
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05/27/2014
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12/03/2015
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06/09/2015
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05/28/2014
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09/18/2014
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08/30/2016
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05/28/2014
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12/03/2015
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04/26/2016
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05/28/2014
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12/03/2015
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10/25/2016
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05/29/2014
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01/22/2015
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08/23/2016
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05/29/2014
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12/03/2015
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10/27/2015
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05/30/2014
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11/13/2014
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11/10/2015
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05/30/2014
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12/04/2014
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04/25/2017
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05/30/2014
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01/01/2015
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07/14/2015
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05/30/2014
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11/27/2014
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10/13/2015
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06/02/2014
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09/18/2014
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08/04/2015
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06/02/2014
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12/11/2014
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11/15/2016
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06/02/2014
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12/03/2015
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ENCRYPTION ENGINE WITH TWIN CELL MEMORY ARRAY
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06/09/2015
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14293422
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06/02/2014
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09/18/2014
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EXTREME ULTRAVIOLET (EUV) MULTILAYER DEFECT COMPENSATION AND EUV MASKS
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05/09/2017
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06/02/2014
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01/29/2015
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09/27/2016
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06/03/2014
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12/03/2015
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07/12/2016
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06/03/2014
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04/02/2015
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12/15/2015
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06/03/2014
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12/03/2015
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10/27/2015
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06/03/2014
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12/04/2014
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03/08/2016
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06/04/2014
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12/10/2015
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05/12/2015
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06/04/2014
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12/18/2014
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TAPE HEAD WITH TAPE-BEARING SURFACE EXHIBITING AN ARRAY OF PROTRUDING TOPOGRAPHIC FEATURES
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02/02/2016
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06/04/2014
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12/10/2015
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03/22/2016
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06/05/2014
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12/18/2014
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02/09/2016
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06/05/2014
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12/18/2014
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08/09/2016
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06/05/2014
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12/10/2015
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08/02/2016
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06/05/2014
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12/10/2015
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04/14/2015
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06/05/2014
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01/01/2015
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09/27/2016
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06/05/2014
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12/11/2014
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07/05/2016
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06/06/2014
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12/10/2015
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BURIED SOURCE-DRAIN CONTACT FOR INTEGRATED CIRCUIT TRANSISTOR DEVICES AND METHOD OF MAKING SAME
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02/21/2017
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06/06/2014
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12/10/2015
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VERTICAL CAPACITORS WITH SPACED CONDUCTIVE LINES
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05/02/2017
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06/09/2014
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01/01/2015
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OPTICAL DEVICE
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04/19/2016
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06/10/2014
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Publication #:
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Pub Dt:
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12/10/2015
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Title:
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METHOD FOR MAKING A SEMICONDUCTOR DEVICE WHILE AVOIDING NODULES ON A GATE
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Patent #:
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Issue Dt:
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06/09/2015
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Application #:
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14300617
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Filing Dt:
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06/10/2014
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Publication #:
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Pub Dt:
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06/11/2015
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Title:
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DYNAMIC CASCODE-MANAGED HIGH-VOLTAGE WORD-LINE DRIVER CIRCUIT
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Patent #:
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Issue Dt:
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11/10/2015
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Application #:
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14300688
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Filing Dt:
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06/10/2014
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Publication #:
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Pub Dt:
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06/11/2015
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Title:
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MULTI-DIMENSIONAL PHYSICAL ARRANGEMENT TECHNIQUES USING BIN-PACKING WITH PER-BRANCH COMBINATION TRIES
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Patent #:
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Issue Dt:
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04/12/2016
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Application #:
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14300705
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Filing Dt:
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06/10/2014
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Publication #:
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Pub Dt:
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12/10/2015
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Title:
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CHEMICAL MECHANICAL POLISHING METHOD AND APPARATUS
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Patent #:
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Issue Dt:
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04/12/2016
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Application #:
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14300944
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Filing Dt:
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06/10/2014
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Publication #:
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Pub Dt:
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12/10/2015
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Title:
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BIPOLAR TRANSISTOR WITH EXTRINSIC BASE REGION AND METHODS OF FABRICATION
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Patent #:
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Issue Dt:
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01/26/2016
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Application #:
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14301395
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Filing Dt:
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06/11/2014
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Publication #:
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Pub Dt:
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09/25/2014
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Title:
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THROUGH SILICON VIA WAFER, CONTACTS AND DESIGN STRUCTURES
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Patent #:
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Issue Dt:
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06/28/2016
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Application #:
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14301623
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Filing Dt:
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06/11/2014
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Publication #:
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Pub Dt:
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10/02/2014
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Title:
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THERMAL GROUND PLANE FOR COOLING A COMPUTER
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Patent #:
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Issue Dt:
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04/12/2016
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Application #:
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14301748
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Filing Dt:
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06/11/2014
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Publication #:
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Pub Dt:
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12/17/2015
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Title:
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FORMING GATE AND SOURCE/DRAIN CONTACT OPENINGS BY PERFORMING A COMMON ETCH PATTERNING PROCESS
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Patent #:
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Issue Dt:
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04/25/2017
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Application #:
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14301864
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Filing Dt:
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06/11/2014
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Publication #:
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Pub Dt:
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12/17/2015
| | | | |
Title:
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METHODS OF FORMING A PROTECTION LAYER ON A SEMICONDUCTOR DEVICE AND THE RESULTING DEVICE
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Patent #:
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Issue Dt:
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06/28/2016
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Application #:
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14302585
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Filing Dt:
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06/12/2014
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Publication #:
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Pub Dt:
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12/17/2015
| | | | |
Title:
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STABLE NICKEL SILICIDE FORMATION WITH FLUORINE INCORPORATION AND RELATED IC STRUCTURE
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Patent #:
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Issue Dt:
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10/27/2015
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Application #:
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14302748
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Filing Dt:
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06/12/2014
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Publication #:
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Pub Dt:
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10/02/2014
| | | | |
Title:
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ON-CHIP CAPACITORS WITH A VARIABLE CAPACITANCE FOR A RADIOFREQUENCY INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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05/02/2017
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Application #:
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14302934
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Filing Dt:
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06/12/2014
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Publication #:
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Pub Dt:
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12/17/2015
| | | | |
Title:
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DETERMINING THERMAL PROFILES OF SEMICONDUCTOR STRUCTURES
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Patent #:
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Issue Dt:
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01/10/2017
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Application #:
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14303217
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Filing Dt:
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06/12/2014
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Publication #:
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Pub Dt:
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02/05/2015
| | | | |
Title:
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Deployment of Software Images with Distinct Configuration Logic
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Patent #:
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NONE
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Issue Dt:
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Application #:
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14303714
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Filing Dt:
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06/13/2014
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Publication #:
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Pub Dt:
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12/17/2015
| | | | |
Title:
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DECOUPLING CAPACITOR FOR SEMICONDUCTORS
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Patent #:
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Issue Dt:
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12/22/2015
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Application #:
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14303764
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Filing Dt:
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06/13/2014
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Publication #:
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Pub Dt:
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12/17/2015
| | | | |
Title:
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OPTIMIZATION OF INTEGRATED CIRCUITS FOR A RETICLE TRANSMISSION PROCESS WINDOW USING MULTIPLE FILL CELLS
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Patent #:
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Issue Dt:
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01/05/2016
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Application #:
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14304017
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Filing Dt:
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06/13/2014
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Publication #:
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Pub Dt:
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12/17/2015
| | | | |
Title:
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STRESS MEMORIZATION TECHNIQUES FOR TRANSISTOR DEVICES
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Patent #:
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Issue Dt:
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10/20/2015
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Application #:
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14304096
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Filing Dt:
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06/13/2014
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Title:
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METHODS OF FORMING A NANOWIRE DEVICE WITH A GATE-ALL-AROUND-CHANNEL CONFIGURATION AND THE RESULTING NANOWIRE DEVICE
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Patent #:
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Issue Dt:
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03/29/2016
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Application #:
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14304220
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Filing Dt:
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06/13/2014
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Publication #:
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Pub Dt:
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03/05/2015
| | | | |
Title:
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OPTIMIZING MEMORY BANDWIDTH CONSUMPTION USING DATA SPLITTING WITH SOFTWARE CACHING
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Patent #:
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Issue Dt:
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09/06/2016
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Application #:
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14304318
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Filing Dt:
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06/13/2014
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Publication #:
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Pub Dt:
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12/17/2015
| | | | |
Title:
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SILICON WAVEGUIDE STRUCTURE WITH ARBITRARY GEOMETRY ON BULK SILICON SUBSTRATE, RELATED SYSTEMS AND PROGRAM PRODUCTS
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Patent #:
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Issue Dt:
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01/09/2018
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Application #:
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14304564
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Filing Dt:
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06/13/2014
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Publication #:
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Pub Dt:
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12/17/2015
| | | | |
Title:
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SOLENOIDAL SERIES STACKED MULTIPATH INDUCTOR
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Patent #:
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Issue Dt:
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02/14/2017
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Application #:
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14304598
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Filing Dt:
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06/13/2014
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Publication #:
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Pub Dt:
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12/17/2015
| | | | |
Title:
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HIGH-Q MULTIPATH PARALLEL STACKED INDUCTOR
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Patent #:
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Issue Dt:
|
08/18/2015
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Application #:
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14305457
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Filing Dt:
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06/16/2014
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Title:
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METHODS OF FORMING REPLACEMENT GATE STRUCTURES ON SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
|
02/21/2017
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Application #:
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14305543
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Filing Dt:
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06/16/2014
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Publication #:
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Pub Dt:
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12/17/2015
| | | | |
Title:
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FINFET AND NANOWIRE SEMICONDUCTOR DEVICES WITH SUSPENDED CHANNEL REGIONS AND GATE STRUCTURES SURROUNDING THE SUSPENDED CHANNEL REGIONS
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Patent #:
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Issue Dt:
|
12/29/2015
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Application #:
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14305630
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Filing Dt:
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06/16/2014
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Publication #:
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Pub Dt:
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12/17/2015
| | | | |
Title:
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METHOD AND APPARATUS FOR BIT-LINE SENSING GATES ON AN SRAM CELL
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Patent #:
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Issue Dt:
|
06/21/2016
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Application #:
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14306294
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Filing Dt:
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06/17/2014
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Publication #:
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Pub Dt:
|
12/17/2015
| | | | |
Title:
|
NON-PLANAR CAPACITORS WITH FINELY TUNED CAPACITANCE VALUES AND METHODS OF FORMING THE NON-PLANAR CAPACITORS
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Patent #:
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Issue Dt:
|
05/24/2016
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Application #:
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14306373
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Filing Dt:
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06/17/2014
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Publication #:
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Pub Dt:
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12/17/2015
| | | | |
Title:
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SEMICONDUCTOR DEVICES WITH SEMICONDUCTOR BODIES HAVING INTERLEAVED HORIZONTAL PORTIONS AND METHOD OF FORMING THE DEVICES
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Patent #:
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Issue Dt:
|
02/23/2016
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Application #:
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14306598
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Filing Dt:
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06/17/2014
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Publication #:
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Pub Dt:
|
12/17/2015
| | | | |
Title:
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WAFER STRESS CONTROL WITH BACKSIDE PATTERNING
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Patent #:
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Issue Dt:
|
07/21/2015
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Application #:
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14306599
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Filing Dt:
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06/17/2014
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Publication #:
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Pub Dt:
|
01/01/2015
| | | | |
Title:
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PHASE-CHANGE MEMORY CELLS
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Patent #:
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Issue Dt:
|
04/12/2016
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Application #:
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14306715
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Filing Dt:
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06/17/2014
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Publication #:
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Pub Dt:
|
12/17/2015
| | | | |
Title:
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CORRECTING FOR STRESS INDUCED PATTERN SHIFTS IN SEMICONDUCTOR MANUFACTURING
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Patent #:
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Issue Dt:
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05/31/2016
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Application #:
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14306790
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Filing Dt:
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06/17/2014
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Publication #:
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Pub Dt:
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12/25/2014
| | | | |
Title:
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MANAGING A TRANSLATION LOOKASIDE BUFFER
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Patent #:
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Issue Dt:
|
09/22/2015
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Application #:
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14306864
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Filing Dt:
|
06/17/2014
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Title:
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CONTAINMENT STRUCTURE FOR EPITAXIAL GROWTH IN NON-PLANAR SEMICONDUCTOR STRUCTURE
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Patent #:
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Issue Dt:
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01/05/2016
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Application #:
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14306920
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Filing Dt:
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06/17/2014
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Publication #:
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Pub Dt:
|
12/17/2015
| | | | |
Title:
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UNIFORM GATE HEIGHT FOR MIXED-TYPE NON-PLANAR SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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05/23/2017
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Application #:
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14307011
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Filing Dt:
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06/17/2014
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Publication #:
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Pub Dt:
|
12/17/2015
| | | | |
Title:
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METHOD OF FORMING A REDUCED RESISTANCE FIN STRUCTURE
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Patent #:
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Issue Dt:
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12/27/2016
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Application #:
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14307078
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Filing Dt:
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06/17/2014
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Publication #:
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Pub Dt:
|
12/17/2015
| | | | |
Title:
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SEMICONDUCTOR STRUCTURE INCLUDING CAPACITORS HAVING DIFFERENT CAPACITOR DIELECTRICS AND METHOD FOR THE FORMATION THEREOF
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Patent #:
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Issue Dt:
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11/29/2016
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Application #:
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14307575
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Filing Dt:
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06/18/2014
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Publication #:
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Pub Dt:
|
12/24/2015
| | | | |
Title:
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REPLACEMENT GATE STRUCTURE FOR ENHANCING CONDUCTIVITY
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Patent #:
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Issue Dt:
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11/01/2016
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Application #:
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14307604
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Filing Dt:
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06/18/2014
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Publication #:
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Pub Dt:
|
12/24/2015
| | | | |
Title:
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BURIED SIGNAL TRANSMISSION LINE
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Patent #:
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Issue Dt:
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10/18/2016
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Application #:
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14307902
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Filing Dt:
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06/18/2014
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Publication #:
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Pub Dt:
|
12/24/2015
| | | | |
Title:
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METHODS OF FORMING A FINFET SEMICONDUCTOR DEVICE WITH A UNIQUE GATE CONFIGURATION, AND THE RESULTING FINFET DEVICE
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Patent #:
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Issue Dt:
|
07/12/2016
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Application #:
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14308045
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Filing Dt:
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06/18/2014
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Publication #:
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Pub Dt:
|
12/24/2015
| | | | |
Title:
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FINFETS HAVING STRAINED CHANNELS, AND METHODS OF FABRICATING FINFETS HAVING STRAINED CHANNELS
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Patent #:
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Issue Dt:
|
07/12/2016
|
Application #:
|
14308100
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Filing Dt:
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06/18/2014
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Publication #:
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Pub Dt:
|
05/28/2015
| | | | |
Title:
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WRITE AND READ COLLISION AVOIDANCE IN SINGLE PORT MEMORY DEVICES
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Patent #:
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Issue Dt:
|
11/08/2016
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Application #:
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14308138
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Filing Dt:
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06/18/2014
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Publication #:
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Pub Dt:
|
12/24/2015
| | | | |
Title:
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METHODS OF FORMING NANOWIRE DEVICES WITH DOPED EXTENSION REGIONS AND THE RESULTING DEVICES
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Patent #:
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Issue Dt:
|
08/30/2016
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Application #:
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14308257
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Filing Dt:
|
06/18/2014
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Publication #:
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Pub Dt:
|
12/24/2015
| | | | |
Title:
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METHODS OF FORMING NANOWIRE DEVICES WITH SPACERS AND THE RESULTING DEVICES
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Patent #:
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Issue Dt:
|
05/05/2015
|
Application #:
|
14308835
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Filing Dt:
|
06/19/2014
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Publication #:
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Pub Dt:
|
11/27/2014
| | | | |
Title:
|
DIELECTRIC RELIABILITY ASSESSMENT FOR ADVANCED SEMICONDUCTORS
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|
|
Patent #:
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Issue Dt:
|
04/10/2018
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Application #:
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14309096
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Filing Dt:
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06/19/2014
|
Publication #:
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|
Pub Dt:
|
12/24/2015
| | | | |
Title:
|
METHOD AND STRUCTURE FOR PROTECTING GATES DURING EPITAXIAL GROWTH
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|