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Patent #:
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Issue Dt:
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04/28/2015
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Application #:
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14309917
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Filing Dt:
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06/20/2014
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Publication #:
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Pub Dt:
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10/09/2014
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Title:
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HETEROJUNCTION III-V PHOTOVOLTAIC CELL FABRICATION
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Patent #:
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Issue Dt:
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12/13/2016
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Application #:
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14310097
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Filing Dt:
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06/20/2014
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Publication #:
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Pub Dt:
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12/25/2014
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Title:
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Detecting Full-System Idle State In Adaptive-Tick Kernels
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Patent #:
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Issue Dt:
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02/16/2016
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Application #:
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14310314
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Filing Dt:
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06/20/2014
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Publication #:
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Pub Dt:
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12/24/2015
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Title:
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MINIMIZING VOID FORMATION IN SEMICONDUCTOR VIAS AND TRENCHES
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Patent #:
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Issue Dt:
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07/12/2016
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Application #:
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14310460
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Filing Dt:
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06/20/2014
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Publication #:
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Pub Dt:
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12/24/2015
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Title:
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NON-VOLATILE RANDOM ACCESS MEMORY DEVICES WITH SHARED TRANSISTOR CONFIGURATION AND METHODS OF FORMING THE SAME
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Patent #:
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09/26/2017
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14310470
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Filing Dt:
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06/20/2014
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Publication #:
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Pub Dt:
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05/28/2015
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Title:
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SYNCHRONOUS SPLIT PAYMENT TRANSACTION MANAGEMENT
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Patent #:
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01/24/2017
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14311380
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Filing Dt:
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06/23/2014
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Publication #:
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Pub Dt:
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12/24/2015
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Title:
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CLEANABILITY ASSESSMENT OF SUBLIMATE FROM LITHOGRAPHY MATERIALS
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Patent #:
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Issue Dt:
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04/04/2017
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Application #:
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14311457
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Filing Dt:
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06/23/2014
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Publication #:
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Pub Dt:
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12/24/2015
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Title:
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INTEGRATED CIRCUITS INCLUDING MODIFIED LINERS AND METHODS FOR FABRICATING THE SAME
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Patent #:
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07/09/2019
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14311761
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06/23/2014
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Pub Dt:
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12/24/2015
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Title:
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METHODS AND SYSTEMS FOR CHEMICAL MECHANICAL PLANARIZATION ENDPOINT DETECTION USING AN ALTERNATING CURRENT REFERENCE SIGNAL
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Patent #:
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04/14/2015
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14312077
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06/23/2014
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Publication #:
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Pub Dt:
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10/09/2014
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Title:
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DRAM CELL BASED ON CONDUCTIVE NANOCHANNEL PLATE
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Patent #:
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05/10/2016
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14312085
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06/23/2014
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Publication #:
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Pub Dt:
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04/09/2015
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Title:
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PRIVACY ENHANCED SPATIAL ANALYTICS
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Patent #:
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11/22/2016
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14312418
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06/23/2014
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Publication #:
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12/24/2015
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Title:
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MULTI-CHANNEL GATE-ALL-AROUND FET
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Patent #:
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Issue Dt:
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05/26/2015
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Application #:
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14312467
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Filing Dt:
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06/23/2014
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Title:
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OPTICAL LATCH AND SYNAPTIC SWITCH
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Patent #:
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12/27/2016
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Application #:
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14314404
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06/25/2014
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Pub Dt:
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12/31/2015
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Title:
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JUNCTION OVERLAP CONTROL IN A SEMICONDUCTOR DEVICE USING A SACRIFICIAL SPACER LAYER
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Patent #:
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03/29/2016
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14314595
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06/25/2014
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Publication #:
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Pub Dt:
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12/31/2015
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Title:
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METHODS OF FORMING INTEGRATED CIRCUITS WITH A PLANARIZED PERMANET LAYER AND METHODS FOR FORMING FINFET DEVICES WITH A PLANARIZED PERMANENT LAYER
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10/03/2017
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14314670
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06/25/2014
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12/31/2015
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Title:
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TITANIUM SILICIDE FORMATION IN A NARROW SOURCE-DRAIN CONTACT
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Patent #:
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NONE
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14314693
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06/25/2014
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Publication #:
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Pub Dt:
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12/31/2015
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Title:
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METHOD AND APPARATUS FOR INLINE DEVICE CHARACTERIZATION AND TEMPERATURE PROFILING
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Issue Dt:
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12/20/2016
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Application #:
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14315362
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06/26/2014
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Pub Dt:
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12/31/2015
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Title:
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TRAPPING DISLOCATIONS IN HIGH-MOBILITY FINS BELOW ISOLATION LAYER
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Patent #:
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04/18/2017
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14315385
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06/26/2014
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Pub Dt:
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12/31/2015
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Title:
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JUNCTION BUTTING STRUCTURE USING NONUNIFORM TRENCH SHAPE
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Patent #:
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08/15/2017
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14315602
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06/26/2014
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Publication #:
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Pub Dt:
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12/31/2015
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Title:
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NON-PLANAR STRUCTURE WITH EXTENDED EXPOSED RAISED STRUCTURES AND SAME-LEVEL GATE AND SPACERS
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Patent #:
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12/08/2015
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Application #:
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14315885
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06/26/2014
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Publication #:
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Pub Dt:
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12/31/2015
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Title:
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THRESHOLD VOLTAGE CONTROL FOR MIXED-TYPE NON-PLANAR SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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07/19/2016
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14316915
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06/27/2014
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Publication #:
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Pub Dt:
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12/31/2015
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Title:
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TEST PATTERN FOR FEATURE CROSS-SECTIONING
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Patent #:
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Issue Dt:
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11/29/2016
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14316988
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06/27/2014
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Pub Dt:
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12/31/2015
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Title:
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SIDEWALL IMAGE TEMPLATES FOR DIRECTED SELF-ASSEMBLY MATERIALS
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Patent #:
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Issue Dt:
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06/16/2015
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14317013
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06/27/2014
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Publication #:
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Pub Dt:
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10/16/2014
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Title:
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METHODS FOR MODELING OF FINFET WIDTH QUANTIZATION
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Issue Dt:
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03/15/2016
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Application #:
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14317806
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06/27/2014
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Publication #:
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Pub Dt:
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12/31/2015
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Title:
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LOW POWER SENSE AMPLIFIER FOR STATIC RANDOM ACCESS MEMORY
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Patent #:
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11/15/2016
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Application #:
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14318822
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06/30/2014
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Pub Dt:
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12/31/2015
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Title:
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REMOVAL OF SEMICONDUCTOR GROWTH DEFECTS
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04/05/2016
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14318901
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06/30/2014
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Publication #:
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Pub Dt:
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12/31/2015
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Title:
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SEMICONDUCTOR CONTACTS AND METHODS OF FABRICATION
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05/31/2016
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14319303
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06/30/2014
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Pub Dt:
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05/28/2015
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Title:
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DYNAMIC VISUALIZATION FOR OPTIMIZATION PROCESSES
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Issue Dt:
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05/10/2016
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14319462
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06/30/2014
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Pub Dt:
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12/31/2015
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Title:
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MULTI-PHASE SOURCE/DRAIN/GATE SPACER-EPI FORMATION
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Patent #:
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Issue Dt:
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06/07/2016
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14319640
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06/30/2014
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Pub Dt:
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12/31/2015
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Title:
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UNIFORM EXPOSED RAISED STRUCTURES FOR NON-PLANAR SEMICONDUCTOR DEVICES
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08/15/2017
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14320841
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07/01/2014
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Pub Dt:
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01/01/2015
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Title:
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GENERATION-BASED MEMORY SYNCHRONIZATION IN A MULTIPROCESSOR SYSTEM WITH WEAKLY CONSISTENT MEMORY ACCESSES
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Patent #:
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NONE
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14320932
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07/01/2014
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01/07/2016
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Title:
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FINFET WITH CONFINED EPITAXY
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Issue Dt:
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11/22/2016
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14321866
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07/02/2014
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Publication #:
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Pub Dt:
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01/07/2016
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Title:
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INHIBITING DIFFUSION OF ELEMENTS BETWEEN MATERIAL LAYERS OF A LAYERED CIRCUIT STRUCTURE
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02/16/2016
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14322987
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07/03/2014
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Pub Dt:
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01/07/2016
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Title:
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METHODS OF FORMING A CHANNEL REGION FOR A SEMICONDUCTOR DEVICE BY PERFORMING A TRIPLE CLADDING PROCESS
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Patent #:
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Issue Dt:
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10/04/2016
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Application #:
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14323164
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07/03/2014
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Pub Dt:
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01/07/2016
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Title:
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PHOTODETECTOR AND METHOD OF FORMING THE PHOTODETECTOR ON STACKED TRENCH ISOLATION REGIONS
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Patent #:
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Issue Dt:
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06/23/2015
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14323212
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07/03/2014
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Publication #:
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Pub Dt:
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10/23/2014
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Title:
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Graphene and Nanotube/Nanowire Transistor with a Self-Aligned Gate Structure on Transparent Substrates and Method of Making Same
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Issue Dt:
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09/13/2016
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14325500
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07/08/2014
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Pub Dt:
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01/14/2016
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Title:
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INTEGRATED CIRCUITS WITH AN INSULTATING LAYER AND METHODS FOR PRODUCING SUCH INTEGRATED CIRCUITS
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Issue Dt:
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06/21/2016
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14325515
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07/08/2014
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Pub Dt:
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11/06/2014
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Title:
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RETICLES FOR USE IN FORMING IMPLANT MASKING LAYERS AND METHODS OF FORMING IMPLANT MASKING LAYERS
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06/14/2016
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14325668
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07/08/2014
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Pub Dt:
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01/14/2016
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Title:
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METHOD AND STRUCTURE TO SUPPRESS FINFET HEATING
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12/15/2015
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14326623
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07/09/2014
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Pub Dt:
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10/30/2014
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Title:
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METHODS OF FORMING METAL SILICIDE REGIONS ON A SEMICONDUCTOR DEVICE
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10/11/2016
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14326659
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07/09/2014
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Pub Dt:
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01/14/2016
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Title:
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FABRICATION OF MULTILAYER CIRCUIT ELEMENTS
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03/15/2016
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14326761
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07/09/2014
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Pub Dt:
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03/19/2015
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Title:
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AUTHORIZED REMOTE ACCESS TO AN OPERATING SYSTEM HOSTED BY A VIRTUAL MACHINE
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01/26/2016
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14327598
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07/10/2014
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Pub Dt:
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10/30/2014
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Title:
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UNIFORM FINFET GATE HEIGHT
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Issue Dt:
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06/14/2016
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14328788
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07/11/2014
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Publication #:
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Pub Dt:
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10/30/2014
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Title:
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TEST COVERAGE OF INTEGRATED CIRCUITS WITH MASKING PATTERN SELECTION
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Patent #:
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Issue Dt:
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08/02/2016
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14328906
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07/11/2014
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Publication #:
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Pub Dt:
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01/22/2015
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Title:
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Hiding Sensitive Data In Plain Text Environment
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Patent #:
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Issue Dt:
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01/19/2016
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Application #:
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14328921
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Filing Dt:
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07/11/2014
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Publication #:
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Pub Dt:
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10/30/2014
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Title:
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SELF-ALIGNED PROCESS TO FABRICATE A MEMORY CELL ARRAY WITH A SURROUNDING-GATE ACCESS TRANSISTOR
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Patent #:
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Issue Dt:
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10/27/2015
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Application #:
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14329263
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Filing Dt:
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07/11/2014
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Title:
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COMBINATION FINFET/ULTRA-THIN BODY TRANSISTOR STRUCTURE AND METHODS OF MAKING SUCH STRUCTURES
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Patent #:
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Issue Dt:
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01/10/2017
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Application #:
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14331276
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Filing Dt:
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07/15/2014
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Publication #:
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Pub Dt:
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01/21/2016
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Title:
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GENERATING A PARALLEL DATA SIGNAL BY CONVERTING SERIAL DATA OF A SERIAL DATA SIGNAL TO PARALLEL DATA
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Patent #:
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NONE
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Application #:
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14332607
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Filing Dt:
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07/16/2014
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Publication #:
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Pub Dt:
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01/29/2015
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Title:
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AGGREGATING AND FILTERING DATA FROM MOBILE DEVICES
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Patent #:
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Issue Dt:
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04/05/2016
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Application #:
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14332886
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Filing Dt:
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07/16/2014
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Publication #:
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Pub Dt:
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01/21/2016
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Title:
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INTEGRATED LDMOS DEVICES FOR SILICON PHOTONICS
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Issue Dt:
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02/23/2016
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Application #:
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14333135
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Filing Dt:
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07/16/2014
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Publication #:
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Pub Dt:
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11/06/2014
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Title:
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FINFET SEMICONDUCTOR DEVICE WITH A RECESSED LINER THAT DEFINES A FIN HEIGHT OF THE FINFET DEVICE
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Issue Dt:
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06/09/2015
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Application #:
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14333555
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Filing Dt:
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07/17/2014
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Publication #:
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Pub Dt:
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11/06/2014
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Title:
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ROBUST REPLACEMENT GATE INTEGRATION
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Patent #:
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Issue Dt:
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02/03/2015
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Application #:
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14333715
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Filing Dt:
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07/17/2014
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Publication #:
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Pub Dt:
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12/11/2014
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Title:
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AQUA REGIA AND HYDROGEN PEROXIDE HCL COMBINATION TO REMOVE NI AND NIPT RESIDUES
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Patent #:
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Issue Dt:
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01/19/2016
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Application #:
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14333806
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Filing Dt:
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07/17/2014
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Publication #:
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Pub Dt:
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02/05/2015
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Title:
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RESISTIVE MEMORY ELEMENT BASED ON OXYGEN-DOPED AMORPHOUS CARBON
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Patent #:
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Issue Dt:
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02/14/2017
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Application #:
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14333841
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Filing Dt:
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07/17/2014
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Publication #:
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Pub Dt:
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03/05/2015
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Title:
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NANODEVICE ASSEMBLIES
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02/28/2017
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14334385
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07/17/2014
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01/21/2016
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Title:
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ANISOTROPIC MATERIAL DAMAGE PROCESS FOR ETCHING LOW-K DIELECTRIC MATERIALS
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01/27/2015
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14334603
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07/17/2014
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Title:
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UTILIZING STORED WRITE ENVIRONMENT CONDITIONS FOR READ ERROR RECOVERY
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06/14/2016
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14334950
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07/18/2014
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Pub Dt:
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01/21/2016
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Title:
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TRANSISTORS COMPRISING DOPED REGION-GAP-DOPED REGION STRUCTURES AND METHODS OF FABRICATION
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07/07/2015
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14334953
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07/18/2014
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Title:
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SHALLOW TRENCH ISOLATION STRUCTURE WITH SIGMA CAVITY
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03/01/2016
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14335230
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07/18/2014
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Pub Dt:
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01/29/2015
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Title:
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HANDLING VIRTUAL MEMORY ADDRESS SYNONYMS IN A MULTI-LEVEL CACHE HIERARCHY STRUCTURE
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11/22/2016
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14335486
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07/18/2014
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02/19/2015
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Title:
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DISPLAY TECHNIQUES FOR GRAPHS
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06/16/2015
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14336407
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07/21/2014
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Pub Dt:
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02/05/2015
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Title:
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RARE-EARTH OXIDE ISOLATED SEMICONDUCTOR FIN
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06/21/2016
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14337290
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07/22/2014
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01/28/2016
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Title:
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WAFER TEST STRUCTURES AND METHODS OF PROVIDING WAFER TEST STRUCTURES
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08/11/2015
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14337596
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07/22/2014
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11/13/2014
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Title:
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BIT CELL WITH DOUBLE PATTERENED METAL LAYER STRUCTURES
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06/16/2015
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14337774
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07/22/2014
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Pub Dt:
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11/06/2014
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Title:
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SELF-ALIGNED CONTACTS FOR REPLACEMENT METAL GATE TRANSISTORS
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06/16/2015
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14338876
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07/23/2014
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11/13/2014
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Title:
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STRUCTURE AND METHOD FOR REDUCING FLOATING BODY EFFECT OF SOI MOSFETS
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04/12/2016
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14339505
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07/24/2014
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Pub Dt:
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01/28/2016
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Title:
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BIPOLAR JUNCTION TRANSISTORS AND METHODS OF FABRICATION
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06/23/2015
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14340633
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07/25/2014
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11/13/2014
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Title:
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VERTICAL ELECTRONIC FUSE
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03/07/2017
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14341000
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07/25/2014
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Pub Dt:
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01/28/2016
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Title:
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METHODS OF FORMING FINS FOR A FINFET DEVICE BY FORMING AND REPLACING SACRIFICIAL FIN STRUCTURES WITH ALTERNATIVE MATERIALS
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10/11/2016
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14341092
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07/25/2014
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01/28/2016
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Title:
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MULTI-POLYGON CONSTRAINT DECOMPOSITION TECHNIQUES FOR USE IN DOUBLE PATTERNING APPLICATIONS
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03/01/2016
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14341985
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07/28/2014
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01/28/2016
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Title:
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METHODS FOR FABRICATING INTEGRATED CIRCUITS USING DIRECTED SELF-ASSEMBLY
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09/13/2016
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14344629
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03/13/2014
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12/18/2014
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Title:
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Message Reconciliation During Disaster Recovery
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04/18/2017
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14345415
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08/04/2014
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11/13/2014
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Title:
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DETECTING OCCURRENCE OF ABNORMALITY
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09/13/2016
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14353053
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09/08/2014
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01/29/2015
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Title:
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NON-INTRUSIVE METHOD AND APPARATUS FOR AUTOMATICALLY DISPATCHING SECURITY RULES IN CLOUD ENVIRONMENT
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12/27/2016
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14358609
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09/26/2014
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02/19/2015
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Title:
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DECODING OF LDPC CODE
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01/12/2016
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14364330
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06/11/2014
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Pub Dt:
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11/06/2014
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Title:
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METHOD FOR ROUTING DATA IN A WIRELESS SENSOR NETWORK
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12/01/2015
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14365325
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06/13/2014
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Pub Dt:
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11/27/2014
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Title:
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TECHNIQUES FOR MEDICAL IMAGE RETREIVAL
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06/20/2017
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14367225
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06/19/2014
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11/06/2014
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Title:
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REMOVAL OF COMPONENTS FROM A STARTING MATERIAL
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11/06/2018
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14378118
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08/12/2014
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01/29/2015
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Title:
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OBJECT CACHING FOR MOBILE DATA COMMUNICATION WITH MOBILITY MANAGEMENT
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09/19/2017
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14381963
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08/28/2014
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03/19/2015
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Position Sensing Apparatus
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12/22/2015
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14387572
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09/24/2014
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05/14/2015
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OPERATING A TAPE STORAGE DEVICE
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04/28/2015
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14444330
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07/28/2014
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Pub Dt:
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11/13/2014
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Title:
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INTEGRATED CIRCUIT HAVING RAISED SOURCE DRAINS DEVICES WITH REDUCED SILICIDE CONTACT RESISTANCE AND METHODS TO FABRICATE SAME
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12/29/2015
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14445101
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07/29/2014
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Title:
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LATERAL DOUBLE-DIFFUSED METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (LDMOSFET) WITH A BELOW SOURCE ISOLATION REGION AND A METHOD OF FORMING THE LDMOSFET
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12/08/2015
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14445775
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07/29/2014
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10/22/2015
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Title:
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CALIBRATION SCHEMES FOR CHARGE-RECYCLING STACKED VOLTAGE DOMAINS
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03/22/2016
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14445893
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07/29/2014
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02/04/2016
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Title:
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SEMICONDUCTOR STRUCTURE INCLUDING A FERROELECTRIC TRANSISTOR AND METHOD FOR THE FORMATION THEREOF
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05/17/2016
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14446020
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07/29/2014
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03/26/2015
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DETECTING PHISHING OF A MATRIX BARCODE
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07/28/2015
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14446536
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07/30/2014
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04/23/2015
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CONGESTION ESTIMATION TECHNIQUES AT PRE-SYNTHESIS STAGE
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11/17/2015
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14446567
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07/30/2014
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03/05/2015
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Title:
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REDUCING OVERHEAD IN LOADING CONSTANTS
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02/10/2015
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14446634
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07/30/2014
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11/20/2014
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METHOD OF FORMING A THROUGH-SILICON VIA UTILIZING A METAL CONTACT PAD IN A BACK-END-OF-LINE WIRING LEVEL TO FILL THE THROUGH-SILICON VIA
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08/09/2016
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14446710
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07/30/2014
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02/05/2015
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Title:
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IDENTIFYING CONTENT FROM AN ENCRYPTED COMMUNICATION
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02/10/2015
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14446797
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07/30/2014
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11/13/2014
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CONTACT LANDING PADS FOR A SEMICONDUCTOR DEVICE AND METHODS OF MAKING SAME
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02/02/2016
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14447678
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07/31/2014
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02/04/2016
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UNIAXIALLY-STRAINED FD-SOI FINFET
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12/01/2015
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14447685
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07/31/2014
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FINFETS AND TECHNIQUES FOR CONTROLLING SOURCE AND DRAIN JUNCTION PROFILES IN FINFETS
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06/16/2015
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14447710
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07/31/2014
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Pub Dt:
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11/20/2014
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Title:
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STRUCTURE AND METHOD FOR MAKING CRACK STOP FOR 3D INTEGRATED CIRCUITS
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12/01/2015
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14447727
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07/31/2014
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Title:
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METHODS FOR FORMING VERTICAL AND SHARP JUNCTIONS IN FINFET STRUCTURES
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03/03/2015
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14447830
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07/31/2014
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Pub Dt:
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11/20/2014
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STRAIN ENHANCEMENT IN TRANSISTORS COMPRISING AN EMBEDDED STRAIN-INDUCING SEMICONDUCTOR ALLOY BY CREATING A PATTERNING NON-UNIFORMITY AT THE BOTTOM OF THE GATE ELECTRODE
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05/23/2017
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14448790
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07/31/2014
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02/05/2015
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TECHNIQUES FOR INCREASING INSTRUCTION ISSUE RATE AND REDUCING LATENCY IN AN OUT-OF-ORDER PROCESSOR
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06/30/2015
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14449177
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08/01/2014
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Pub Dt:
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03/12/2015
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Title:
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ELECTROMECHANICAL SWITCHING DEVICE WITH 2D LAYERED MATERIAL SURFACES
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06/16/2015
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14449180
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08/01/2014
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Pub Dt:
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11/20/2014
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Title:
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LOW VOLTAGE METAL GATE ANTIFUSE WITH DEPLETION MODE MOSFET
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NONE
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14449222
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08/01/2014
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Pub Dt:
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02/04/2016
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ENDPOINT DETERMINATION USING INDIVIDUALLY MEASURED TARGET SPECTRA
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08/11/2015
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14449557
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08/01/2014
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Pub Dt:
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11/20/2014
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Title:
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PIXEL SENSOR CELL WITH HOLD NODE FOR LEAKAGE CANCELLATION AND METHODS OF MANUFACTURE AND DESIGN STRUCTURE
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