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07/05/2016
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14686260
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04/14/2015
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08/06/2015
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Title:
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METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE USING SOURCE/DRAIN EPITAXIAL OVERGROWTH FOR FORMING SELF-ALIGNED CONTACTS WITHOUT SPACER LOSS AND A SEMICONDUCTOR DEVICE FORMED BY SAME
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05/17/2016
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14686857
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04/15/2015
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03/07/2017
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14686904
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04/15/2015
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10/20/2016
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WHOLE WAFER EDGE SEAL
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08/08/2017
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14687002
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04/15/2015
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10/20/2016
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Title:
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ON CHIP ANTENNA WITH OPENING
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03/29/2016
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14687049
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04/15/2015
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08/06/2015
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Title:
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ALTERING CAPACITANCE OF MIM CAPACITOR HAVING REACTIVE LAYER THEREIN
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11/17/2015
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14687050
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04/15/2015
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08/06/2015
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DATA STORAGE TAPE WITH RANDOM ACCESS DATA
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06/28/2016
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14687203
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04/15/2015
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07/14/2016
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01/12/2016
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14687300
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04/15/2015
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11/26/2015
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METHODS OF FABRICATING SEMICONDUCTOR FIN STRUCTURES
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07/26/2016
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14687477
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04/15/2015
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08/06/2015
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COLOR-INSENSITIVE RULES FOR ROUTING STRUCTURES
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06/28/2016
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14687489
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04/15/2015
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10/15/2015
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CHARGE SENSORS USING INVERTED LATERAL BIPOLAR JUNCTION TRANSISTORS
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02/16/2016
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14688027
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04/16/2015
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08/06/2015
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OVERLAY-TOLERANT VIA MASK AND REACTIVE ION ETCH (RIE) TECHNIQUE
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03/19/2019
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14689088
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04/17/2015
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10/20/2016
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SYSTEMATIC DEFECTS INSPECTION METHOD WITH COMBINED EBEAM INSPECTION AND NET TRACING CLASSIFICATION
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01/03/2017
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14689181
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04/17/2015
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10/20/2016
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01/10/2017
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14691233
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04/20/2015
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10/20/2016
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PUNCH-THROUGH-STOP AFTER PARTIAL FIN ETCH
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05/30/2017
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14691270
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04/20/2015
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08/13/2015
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FORMATION OF LARGE SCALE SINGLE CRYSTALLINE GRAPHENE
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11/29/2016
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14691392
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04/20/2015
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08/13/2015
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INFRARED-BASED METROLOGY FOR DETECTION OF STRESS AND DEFECTS AROUND THROUGH SILICON VIAS
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09/05/2017
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14692881
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04/22/2015
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10/27/2016
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HIGH DENSITY CAPACITOR STRUCTURE AND METHOD
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10/18/2016
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14693978
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04/23/2015
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06/09/2016
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METHOD OF FORMING A SEMICONDUCTOR DEVICE STRUCTURE AND SUCH A SEMICONDUCTOR DEVICE STRUCTURE
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06/07/2016
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14694243
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04/23/2015
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08/13/2015
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METHOD OF MANUFACTURING A FINFET DEVICE USING A SACRIFICIAL EPITAXY REGION FOR IMPROVED FIN MERGE AND FINFET DEVICE FORMED BY SAME
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01/17/2017
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14694265
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04/23/2015
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09/24/2015
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BURIED WAVEGUIDE PHOTODETECTOR
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08/23/2016
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14694276
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04/23/2015
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METHODS OF FACILITATING FABRICATING TRANSISTORS
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12/29/2015
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14694831
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04/23/2015
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08/13/2015
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BOOSTING DECOMPRESSION IN THE PRESENCE OF REOCCURRING HUFFMAN TREES
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01/24/2017
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14695091
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04/24/2015
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10/27/2016
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SYSTEMS AND METHODS FOR CONTROLLING INTEGRATED CIRCUIT CHIP TEMPERATURE USING TIMING CLOSURE-BASED ADAPTIVE FREQUENCY SCALING
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09/12/2017
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14695112
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04/24/2015
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10/27/2016
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PRE-TEST POWER-OPTIMIZED BIN REASSIGNMENT FOLLOWING SELECTIVE VOLTAGE BINNING
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01/24/2017
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14695232
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04/24/2015
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10/27/2016
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METHOD OF MANUFACTURING P-CHANNEL FET DEVICE WITH SIGE CHANNEL
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07/24/2018
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14695411
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04/24/2015
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10/27/2016
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FINFET DEVICES HAVING ASYMMETRICAL EPITAXIALLY-GROWN SOURCE AND DRAIN REGIONS AND METHODS OF FORMING THE SAME
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03/15/2016
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14695965
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04/24/2015
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08/20/2015
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INTEGRATED CIRCUITS WITH IMPROVED CONTACT STRUCTURES
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07/12/2016
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14696034
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04/24/2015
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08/13/2015
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DOUBLE MIRROR STRUCTURE FOR WAVELENGTH DIVISION MULTIPLEXING WITH POLYMER WAVEGUIDES
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08/02/2016
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14696534
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04/27/2015
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08/13/2015
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FINFET DEVICE
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02/09/2016
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14696605
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04/27/2015
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08/20/2015
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A MANUFACTURING PROCESS FOR FINFET DEVICE
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07/12/2016
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14696693
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04/27/2015
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08/13/2015
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MOSFET WITH WORK FUNCTION ADJUSTED METAL BACKGATE
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11/01/2016
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14696736
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04/27/2015
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09/17/2015
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MOSFET WITH WORK FUNCTION ADJUSTED METAL BACKGATE
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10/18/2016
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14696843
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04/27/2015
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08/13/2015
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WAVELENGTH DIVISION MULTIPLEXING WITH MULTI-CORE FIBER
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10/25/2016
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14696954
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04/27/2015
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10/27/2016
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SEMICONDUCTOR DEVICE STRUCTURES WITH SELF-ALIGNED FIN STRUCTURE(S) AND FABRICATION METHODS THEREOF
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05/10/2016
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14697670
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04/28/2015
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08/27/2015
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SEMICONDUCTOR DEVICE INCLUDING FINFET AND DIODE HAVING REDUCED DEFECTS IN DEPLETION REGION
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07/12/2016
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04/28/2015
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MEMORY BIT CELL FOR REDUCED LAYOUT AREA
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08/23/2016
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14698103
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04/28/2015
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08/13/2015
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REDUCED THRESHOLD VOLTAGE-WIDTH DEPENDENCY IN TRANSISTORS COMPRISING HIGH-K METAL GATE ELECTRODE STRUCTURES
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10/18/2016
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04/28/2015
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08/13/2015
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SELF ALIGNED EMBEDDED GATE CARBON TRANSISTORS
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08/30/2016
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04/29/2015
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SERIES-CONNECTED NANOWIRE STRUCTURES
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05/24/2016
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04/29/2015
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06/16/2016
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INTEGRATED CIRCUITS WITH CAPACITORS AND METHODS OF PRODUCING THE SAME
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11/28/2017
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04/29/2015
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11/03/2016
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ELECTROSTATIC DISCHARGE (ESD) PROTECTION TRANSISTOR DEVICES AND INTEGRATED CIRCUITS WITH ELECTROSTATIC DISCHARGE PROTECTION TRANSISTOR DEVICES
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08/23/2016
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14699154
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04/29/2015
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CUT FIRST ALTERNATIVE FOR 2D SELF-ALIGNED VIA
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11/01/2016
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14699427
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04/29/2015
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08/20/2015
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METHOD TO IMPROVE RELIABILITY OF REPLACEMENT GATE DEVICE
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01/12/2016
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14699543
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04/29/2015
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SEMICONDUCTOR DEVICE AND METHODS OF FORMING FINS AND GATES WITH ULTRAVIOLET CURING
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07/12/2016
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14699557
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04/29/2015
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10/08/2015
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COLORIMETRIC RADIATION DOSIMETRY BASED ON FUNCTIONAL POLYMER AND NANOPARTICLE HYBRID
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05/10/2016
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04/29/2015
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08/27/2015
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TAPE HEAD WITH THERMAL TAPE-HEAD DISTANCE SENSOR
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09/13/2016
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04/29/2015
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06/30/2016
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10/11/2016
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04/29/2015
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08/27/2015
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METHOD TO IMPROVE RELIABILITY OF REPLACEMENT GATE DEVICE
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07/12/2016
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04/29/2015
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08/27/2015
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METHOD TO IMPROVE RELIABILITY OF REPLACEMENT GATE DEVICE
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05/10/2016
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04/29/2015
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08/20/2015
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PHYSICAL UNCLONABLE FUNCTION GENERATION AND MANAGEMENT
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05/31/2016
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14700147
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04/30/2015
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09/17/2015
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INTEGRATED CIRCUIT WITH ON CHIP PLANAR DIODE AND CMOS DEVICES
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10/17/2017
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14700402
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04/30/2015
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11/03/2016
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ON-CHIP USABLE LIFE DEPLETION METER AND ASSOCIATED METHOD
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14700639
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04/30/2015
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11/03/2016
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03/29/2016
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04/30/2015
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08/27/2015
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TUNABLE FILTER STRUCTURES AND DESIGN STRUCTURES
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02/07/2017
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14700850
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04/30/2015
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11/19/2015
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AXIOCENTRIC SCRUBBING LAND GRID ARRAY CONTACTS AND METHODS FOR FABRICATION
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05/15/2018
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04/30/2015
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01/14/2016
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MULTI-PETASCALE HIGHLY EFFICIENT PARALLEL SUPERCOMPUTER
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03/15/2016
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14701910
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05/01/2015
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10/15/2015
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PROVIDING ACCESS CONTROL FOR PUBLIC AND PRIVATE DOCUMENT FIELDS
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02/21/2017
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14702984
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05/04/2015
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11/10/2016
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SILVER ALLOYING POST-CHIP JOIN
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06/06/2017
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05/04/2015
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11/10/2016
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Title:
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METHOD WHEREIN TEST CELLS AND DUMMY CELLS ARE INCLUDED INTO A LAYOUT OF AN INTEGRATED CIRCUIT
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|
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Patent #:
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Issue Dt:
|
06/06/2017
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Application #:
|
14704488
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Filing Dt:
|
05/05/2015
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Publication #:
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Pub Dt:
|
11/10/2016
| | | | |
Title:
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METHOD FOR SELECTIVE RE-ROUTING OF SELECTED AREAS IN A TARGET LAYER AND IN ADJACENT INTERCONNECTING LAYERS OF AN IC DEVICE
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Patent #:
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Issue Dt:
|
01/19/2016
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Application #:
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14705397
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Filing Dt:
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05/06/2015
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Publication #:
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Pub Dt:
|
08/20/2015
| | | | |
Title:
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ON-CHIP DIODE WITH FULLY DEPLETED SEMICONDUTOR DEVICES
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Patent #:
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Issue Dt:
|
01/12/2016
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Application #:
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14705425
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Filing Dt:
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05/06/2015
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Publication #:
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Pub Dt:
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08/20/2015
| | | | |
Title:
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HETEROGENEOUS INTEGRATION OF GROUP III NITRIDE ON SILICON FOR ADVANCED INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
|
02/21/2017
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Application #:
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14707923
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Filing Dt:
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05/08/2015
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Publication #:
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Pub Dt:
|
08/27/2015
| | | | |
Title:
|
BACK-END TRANSISTORS WITH HIGHLY DOPED LOW-TEMPERATURE CONTACTS
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Patent #:
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Issue Dt:
|
01/12/2016
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Application #:
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14708405
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Filing Dt:
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05/11/2015
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Publication #:
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Pub Dt:
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09/03/2015
| | | | |
Title:
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METHODS OF FORMING REPLACEMENT GATE STRUCTURES AND FINS ON FINFET DEVICES AND THE RESULTING DEVICES
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Patent #:
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Issue Dt:
|
10/18/2016
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Application #:
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14708753
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Filing Dt:
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05/11/2015
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Publication #:
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Pub Dt:
|
08/27/2015
| | | | |
Title:
|
PROACTIVE RISK ANALYSIS AND GOVERNANCE OF UPGRADE PROCESS
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Patent #:
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Issue Dt:
|
11/10/2015
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Application #:
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14708755
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Filing Dt:
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05/11/2015
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Publication #:
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Pub Dt:
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08/27/2015
| | | | |
Title:
|
INTEGRATED CIRCUIT STRUCTURES HAVING OFF-AXIS IN-HOLE CAPACITOR
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Patent #:
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Issue Dt:
|
03/07/2017
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Application #:
|
14709889
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Filing Dt:
|
05/12/2015
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Publication #:
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Pub Dt:
|
11/17/2016
| | | | |
Title:
|
ALIGNMENT MONITORING STRUCTURE AND ALIGNMENT MONITORING METHOD FOR SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
|
02/14/2017
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Application #:
|
14709924
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Filing Dt:
|
05/12/2015
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Publication #:
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Pub Dt:
|
11/19/2015
| | | | |
Title:
|
ARTICLES INCLUDING BONDED METAL STRUCTURES AND METHODS OF PREPARING THE SAME
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|
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Patent #:
|
|
Issue Dt:
|
09/20/2016
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Application #:
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14710053
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Filing Dt:
|
05/12/2015
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Title:
|
METHODS OF FORMING FINS FOR FINFET SEMICONDUCTOR DEVICES AND THE RESULTING DEVICES
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|
|
Patent #:
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|
Issue Dt:
|
11/08/2016
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Application #:
|
14710894
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Filing Dt:
|
05/13/2015
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Publication #:
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Pub Dt:
|
11/17/2016
| | | | |
Title:
|
VIA FORMATION USING SIDEWALL IMAGE TRANSFER PROCESS TO DEFINE LATERAL DIMENSION
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|
Patent #:
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Issue Dt:
|
12/15/2015
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Application #:
|
14710935
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Filing Dt:
|
05/13/2015
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Publication #:
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Pub Dt:
|
08/27/2015
| | | | |
Title:
|
METHOD OF SELF-CORRECTING POWER GRID FOR SEMICONDUCTOR STRUCTURES
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Patent #:
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Issue Dt:
|
01/12/2016
|
Application #:
|
14711029
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Filing Dt:
|
05/13/2015
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Publication #:
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Pub Dt:
|
08/27/2015
| | | | |
Title:
|
SEMICONDUCTOR DEVICE WITH FIELD-INDUCING STRUCTURE
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|
Patent #:
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|
Issue Dt:
|
12/29/2015
|
Application #:
|
14711069
|
Filing Dt:
|
05/13/2015
|
Publication #:
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|
Pub Dt:
|
08/27/2015
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURES WITH PAIR(S) OF VERTICAL FIELD EFFECT TRANSISTORS, EACH PAIR HAVING A SHARED SOURCE/DRAIN REGION AND METHODS OF FORMING THE STRUCTURES
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|
Patent #:
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|
Issue Dt:
|
03/01/2016
|
Application #:
|
14711119
|
Filing Dt:
|
05/13/2015
|
Publication #:
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|
Pub Dt:
|
09/03/2015
| | | | |
Title:
|
THICK AND THIN DATA VOLUME MANAGEMENT
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Patent #:
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Issue Dt:
|
08/23/2016
|
Application #:
|
14711196
|
Filing Dt:
|
05/13/2015
|
Publication #:
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|
Pub Dt:
|
09/10/2015
| | | | |
Title:
|
SEMICONDUCTOR DEVICE WITH LOW-K SPACERS
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|
Patent #:
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Issue Dt:
|
12/22/2015
|
Application #:
|
14711377
|
Filing Dt:
|
05/13/2015
|
Publication #:
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|
Pub Dt:
|
09/03/2015
| | | | |
Title:
|
METHOD OF USING AN EUV MASK DURING EUV PHOTOLITHOGRAPHY PROCESSES
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|
Patent #:
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|
Issue Dt:
|
12/20/2016
|
Application #:
|
14711380
|
Filing Dt:
|
05/13/2015
|
Publication #:
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|
Pub Dt:
|
11/17/2016
| | | | |
Title:
|
FILLING CAVITIES IN AN INTEGRATED CIRCUIT AND RESULTING DEVICES
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|
|
Patent #:
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|
Issue Dt:
|
05/17/2016
|
Application #:
|
14711462
|
Filing Dt:
|
05/13/2015
|
Publication #:
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|
Pub Dt:
|
09/03/2015
| | | | |
Title:
|
HETEROJUNCTION LIGHT EMITTING DIODE
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|
|
Patent #:
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|
Issue Dt:
|
02/16/2016
|
Application #:
|
14711872
|
Filing Dt:
|
05/14/2015
|
Publication #:
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|
Pub Dt:
|
08/27/2015
| | | | |
Title:
|
SPUTTER AND SURFACE MODIFICATION ETCH PROCESSING FOR METAL PATTERNING IN INTEGRATED CIRCUITS
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|
Patent #:
|
|
Issue Dt:
|
10/10/2017
|
Application #:
|
14712092
|
Filing Dt:
|
05/14/2015
|
Publication #:
|
|
Pub Dt:
|
08/27/2015
| | | | |
Title:
|
BACKSIDE INTEGRATION OF RF FILTERS FOR RF FRONT END MODULES AND DESIGN STRUCTURE
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|
|
Patent #:
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|
Issue Dt:
|
11/08/2016
|
Application #:
|
14712388
|
Filing Dt:
|
05/14/2015
|
Publication #:
|
|
Pub Dt:
|
11/17/2016
| | | | |
Title:
|
GATE CONTACT STRUCTURE HAVING GATE CONTACT LAYER
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|
Patent #:
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|
Issue Dt:
|
03/14/2017
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Application #:
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14712397
|
Filing Dt:
|
05/14/2015
|
Publication #:
|
|
Pub Dt:
|
09/10/2015
| | | | |
Title:
|
DUAL SHALLOW TRENCH ISOLATION (STI) STRUCTURE FOR FIELD EFFECT TRANSISTOR (FET)
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Patent #:
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|
Issue Dt:
|
08/08/2017
|
Application #:
|
14712830
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Filing Dt:
|
05/14/2015
|
Publication #:
|
|
Pub Dt:
|
11/17/2016
| | | | |
Title:
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METHOD, APPARATUS, AND SYSTEM FOR IMPROVED STANDARD CELL DESIGN AND ROUTING FOR IMPROVING STANDARD CELL ROUTABILITY
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|
Patent #:
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Issue Dt:
|
10/27/2015
|
Application #:
|
14713327
|
Filing Dt:
|
05/15/2015
|
Publication #:
|
|
Pub Dt:
|
09/03/2015
| | | | |
Title:
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INTEGRATED SEMICONDUCTOR DEVICES WITH SINGLE CRYSTALLINE BEAM, METHODS OF MANUFACTURE AND DESIGN STRUCTURE
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Patent #:
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Issue Dt:
|
03/21/2017
|
Application #:
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14713626
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Filing Dt:
|
05/15/2015
|
Publication #:
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|
Pub Dt:
|
09/03/2015
| | | | |
Title:
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CIRCUIT FOR DETECTING STRUCTURAL DEFECTS IN AN INTEGRATED CIRCUIT CHIP, METHODS OF USE AND MANUFACTURE AND DESIGN STRUCTURES
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Patent #:
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Issue Dt:
|
01/17/2017
|
Application #:
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14714779
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Filing Dt:
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05/18/2015
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Publication #:
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Pub Dt:
|
09/10/2015
| | | | |
Title:
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SHALLOW TRENCH ISOLATION STRUCTURES
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Patent #:
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Issue Dt:
|
04/26/2016
|
Application #:
|
14715050
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Filing Dt:
|
05/18/2015
|
Title:
|
METHODS OF FORMING ELASTICALLY RELAXED SiGe VIRTUAL SUBSTRATES ON BULK SILICON
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Patent #:
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Issue Dt:
|
06/07/2016
|
Application #:
|
14715109
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Filing Dt:
|
05/18/2015
|
Title:
|
METHODS OF FORMING ELASTICALLY RELAXED SIGE VIRTUAL SUBSTRATES ON BULK SILICON
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|
Patent #:
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Issue Dt:
|
12/27/2016
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Application #:
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14715693
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Filing Dt:
|
05/19/2015
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Publication #:
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Pub Dt:
|
09/10/2015
| | | | |
Title:
|
SILICON-ON-INSULATOR HEAT SINK
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|
Patent #:
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|
Issue Dt:
|
11/17/2015
|
Application #:
|
14716236
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Filing Dt:
|
05/19/2015
|
Publication #:
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Pub Dt:
|
10/01/2015
| | | | |
Title:
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REDUCING WAFER BONDING MISALIGNMENT BY VARYING THERMAL TREATMENT PRIOR TO BONDING
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Patent #:
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Issue Dt:
|
05/02/2017
|
Application #:
|
14716565
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Filing Dt:
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05/19/2015
|
Publication #:
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Pub Dt:
|
11/24/2016
| | | | |
Title:
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METHOD, APPARATUS, AND SYSTEM FOR OFFSET METAL POWER RAIL FOR CELL DESIGN
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Patent #:
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Issue Dt:
|
01/17/2017
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Application #:
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14716696
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Filing Dt:
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05/19/2015
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Publication #:
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Pub Dt:
|
01/21/2016
| | | | |
Title:
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SHALLOW TRENCH ISOLATION STRUCTURE WITH SIGMA CAVITY
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Patent #:
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Issue Dt:
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07/10/2018
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Application #:
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14716938
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Filing Dt:
|
05/20/2015
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Publication #:
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Pub Dt:
|
11/24/2016
| | | | |
Title:
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PRESERVING THE SEED LAYER ON STI EDGE AND IMPROVING THE EPITAXIAL GROWTH
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Patent #:
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Issue Dt:
|
10/18/2016
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Application #:
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14717344
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Filing Dt:
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05/20/2015
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Publication #:
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Pub Dt:
|
09/24/2015
| | | | |
Title:
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ACTIVE MATRIX USING HYBRID INTEGRATED CIRCUIT AND BIPOLAR TRANSISTOR
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Patent #:
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Issue Dt:
|
01/12/2016
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Application #:
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14717387
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Filing Dt:
|
05/20/2015
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Publication #:
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Pub Dt:
|
09/10/2015
| | | | |
Title:
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METHODS FOR FABRICATION INTERCONNECT STRUCTURES WITH FUNCTIONAL COMPONENTS AND ELECTRICAL CONDUCTIVE CONTACT STRUCTURES ON A SAME LEVEL
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Patent #:
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Issue Dt:
|
10/10/2017
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Application #:
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14718314
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Filing Dt:
|
05/21/2015
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Publication #:
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Pub Dt:
|
11/24/2016
| | | | |
Title:
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THIN FILM BASED FAN OUT AND MULTI DIE PACKAGE PLATFORM
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Patent #:
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Issue Dt:
|
04/05/2016
|
Application #:
|
14718331
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Filing Dt:
|
05/21/2015
|
Publication #:
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|
Pub Dt:
|
09/10/2015
| | | | |
Title:
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FILE SYSTEM LEVEL DATA PROTECTION DURING POTENTIAL SECURITY BREACH
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Patent #:
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NONE
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Issue Dt:
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|
Application #:
|
14718402
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Filing Dt:
|
05/21/2015
|
Publication #:
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Pub Dt:
|
11/24/2016
| | | | |
Title:
|
INTERFACE PASSIVATION LAYERS AND METHODS OF FABRICATING
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Patent #:
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Issue Dt:
|
01/24/2017
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Application #:
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14718502
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Filing Dt:
|
05/21/2015
|
Publication #:
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Pub Dt:
|
11/24/2016
| | | | |
Title:
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E-FUSE IN SOI CONFIGURATION
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Patent #:
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Issue Dt:
|
11/08/2016
|
Application #:
|
14718574
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Filing Dt:
|
05/21/2015
|
Publication #:
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Pub Dt:
|
11/24/2016
| | | | |
Title:
|
DEVICE COMPRISING A PLURALITY OF FDSOI STATIC RANDOM-ACCESS MEMORY BITCELLS AND METHOD OF OPERATION THEREOF
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|