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Reel/Frame:049490/0001   Pages: 892
Recorded: 11/29/2018
Conveyance: SECURITY AGREEMENT
Total properties: 13706
Page 126 of 138
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138
1
Patent #:
9390769
Issue Dt:
07/12/2016
Application #:
14922323
Filing Dt:
10/26/2015
Title:
SENSE AMPLIFIERS AND MULTIPLEXED LATCHES
2
Patent #:
10078107
Issue Dt:
09/18/2018
Application #:
14924439
Filing Dt:
10/27/2015
Publication #:
US20170115337
Pub Dt:
04/27/2017
Title:
WAFER LEVEL ELECTRICAL TEST FOR OPTICAL PROXIMITY CORRECTION AND/OR ETCH BIAS
3
Patent #:
9362284
Issue Dt:
06/07/2016
Application #:
14924486
Filing Dt:
10/27/2015
Publication #:
US20160049400
Pub Dt:
02/18/2016
Title:
THRESHOLD VOLTAGE CONTROL FOR MIXED-TYPE NON-PLANAR SEMICONDUCTOR DEVICES
4
Patent #:
9947774
Issue Dt:
04/17/2018
Application #:
14925630
Filing Dt:
10/28/2015
Publication #:
US20170125551
Pub Dt:
05/04/2017
Title:
FIN FIELD EFFECT TRANSISTOR COMPLEMENTARY METAL OXIDE SEMICONDUCTOR WITH DUAL STRAINED CHANNELS WITH SOLID PHASE DOPING
5
Patent #:
9660040
Issue Dt:
05/23/2017
Application #:
14926657
Filing Dt:
10/29/2015
Publication #:
US20160049481
Pub Dt:
02/18/2016
Title:
TRANSISTOR CONTACTS SELF-ALIGNED TWO DIMENSIONS
6
Patent #:
9754903
Issue Dt:
09/05/2017
Application #:
14926880
Filing Dt:
10/29/2015
Publication #:
US20170125361
Pub Dt:
05/04/2017
Title:
SEMICONDUCTOR STRUCTURE WITH ANTI-EFUSE DEVICE
7
Patent #:
9741853
Issue Dt:
08/22/2017
Application #:
14926897
Filing Dt:
10/29/2015
Publication #:
US20170125587
Pub Dt:
05/04/2017
Title:
STRESS MEMORIZATION TECHNIQUES FOR TRANSISTOR DEVICES
8
Patent #:
9570555
Issue Dt:
02/14/2017
Application #:
14926936
Filing Dt:
10/29/2015
Title:
SOURCE AND DRAIN EPITAXIAL SEMICONDUCTOR MATERIAL INTEGRATION FOR HIGH VOLTAGE SEMICONDUCTOR DEVICES
9
Patent #:
9853110
Issue Dt:
12/26/2017
Application #:
14927765
Filing Dt:
10/30/2015
Publication #:
US20170125530
Pub Dt:
05/04/2017
Title:
METHOD OF FORMING A GATE CONTACT STRUCTURE FOR A SEMICONDUCTOR DEVICE
10
Patent #:
9601392
Issue Dt:
03/21/2017
Application #:
14927943
Filing Dt:
10/30/2015
Title:
DEVICE CHARACTERIZATION BY TIME DEPENDENT CHARGING DYNAMICS
11
Patent #:
10115719
Issue Dt:
10/30/2018
Application #:
14928272
Filing Dt:
10/30/2015
Publication #:
US20160126239
Pub Dt:
05/05/2016
Title:
INTEGRATED CIRCUITS WITH RESISTOR STRUCTURES FORMED FROM MIM CAPACITOR MATERIAL AND METHODS FOR FABRICATING SAME
12
Patent #:
9960284
Issue Dt:
05/01/2018
Application #:
14928595
Filing Dt:
10/30/2015
Publication #:
US20170125610
Pub Dt:
05/04/2017
Title:
SEMICONDUCTOR STRUCTURE INCLUDING A VARACTOR
13
Patent #:
9551674
Issue Dt:
01/24/2017
Application #:
14928605
Filing Dt:
10/30/2015
Title:
METHOD OF PRODUCING AN UN-DISTORTED DARK FIELD STRAIN MAP AT HIGH SPATIAL RESOLUTION THROUGH DARK FIELD ELECTRON HOLOGRAPHY
14
Patent #:
10199479
Issue Dt:
02/05/2019
Application #:
14928681
Filing Dt:
10/30/2015
Publication #:
US20160056263
Pub Dt:
02/25/2016
Title:
METHODS OF FORMING A GATE CAP LAYER ABOVE A REPLACEMENT GATE STRUCTURE
15
Patent #:
9923078
Issue Dt:
03/20/2018
Application #:
14928719
Filing Dt:
10/30/2015
Publication #:
US20170125543
Pub Dt:
05/04/2017
Title:
TRENCH SILICIDE CONTACTS WITH HIGH SELECTIVITY PROCESS
16
Patent #:
9530553
Issue Dt:
12/27/2016
Application #:
14929869
Filing Dt:
11/02/2015
Title:
HIGH PERFORMANCE INDUCTOR/TRANSFORMER AND METHODS OF MAKING SUCH INDUCTOR/TRANSFORMER STRUCTURES
17
Patent #:
9536982
Issue Dt:
01/03/2017
Application #:
14930895
Filing Dt:
11/03/2015
Title:
ETCH STOP FOR AIRGAP PROTECTION
18
Patent #:
9484255
Issue Dt:
11/01/2016
Application #:
14930933
Filing Dt:
11/03/2015
Title:
HYBRID SOURCE AND DRAIN CONTACT FORMATION USING METAL LINER AND METAL INSULATOR SEMICONDUCTOR CONTACTS
19
Patent #:
10161915
Issue Dt:
12/25/2018
Application #:
14932372
Filing Dt:
11/04/2015
Publication #:
US20170122913
Pub Dt:
05/04/2017
Title:
IN-SITU CONTACTLESS MONITORING OF PHOTOMASK PELLICLE DEGRADATION
20
Patent #:
9419101
Issue Dt:
08/16/2016
Application #:
14932394
Filing Dt:
11/04/2015
Title:
MULTI-LAYER SPACER USED IN FINFET
21
Patent #:
NONE
Issue Dt:
Application #:
14932409
Filing Dt:
11/04/2015
Publication #:
US20160056106
Pub Dt:
02/25/2016
Title:
STRUCTURE WITH SELF ALIGNED RESIST LAYER ON AN INTERCONNECT SURFACE AND METHOD OF MAKING SAME
22
Patent #:
10263065
Issue Dt:
04/16/2019
Application #:
14932441
Filing Dt:
11/04/2015
Publication #:
US20170125509
Pub Dt:
05/04/2017
Title:
METAL RESISTOR FORMING METHOD USING ION IMPLANTATION
23
Patent #:
9673115
Issue Dt:
06/06/2017
Application #:
14933107
Filing Dt:
11/05/2015
Publication #:
US20170133287
Pub Dt:
05/11/2017
Title:
TEST STRUCTURES AND METHOD OF FORMING AN ACCORDING TEST STRUCTURE
24
Patent #:
9537006
Issue Dt:
01/03/2017
Application #:
14933557
Filing Dt:
11/05/2015
Publication #:
US20160056288
Pub Dt:
02/25/2016
Title:
CIRCUIT ELEMENT INCLUDING A LAYER OF A STRESS-CREATING MATERIAL PROVIDING A VARIABLE STRESS
25
Patent #:
9905460
Issue Dt:
02/27/2018
Application #:
14933650
Filing Dt:
11/05/2015
Publication #:
US20170133325
Pub Dt:
05/11/2017
Title:
METHODS OF SELF-FORMING BARRIER FORMATION IN METAL INTERCONNECTION APPLICATIONS
26
Patent #:
9798088
Issue Dt:
10/24/2017
Application #:
14933668
Filing Dt:
11/05/2015
Publication #:
US20170131476
Pub Dt:
05/11/2017
Title:
BARRIER STRUCTURES FOR UNDERFILL BLOCKOUT REGIONS
27
Patent #:
NONE
Issue Dt:
Application #:
14934042
Filing Dt:
11/05/2015
Publication #:
US20170133406
Pub Dt:
05/11/2017
Title:
METHOD, APPARATUS, AND SYSTEM FOR STACKED CMOS LOGIC CIRCUITS ON FINS
28
Patent #:
9368513
Issue Dt:
06/14/2016
Application #:
14934369
Filing Dt:
11/06/2015
Publication #:
US20160071886
Pub Dt:
03/10/2016
Title:
HIGHLY CONFORMAL EXTENSION DOPING IN ADVANCED MULTI-GATE DEVICES
29
Patent #:
9906213
Issue Dt:
02/27/2018
Application #:
14934793
Filing Dt:
11/06/2015
Publication #:
US20170133923
Pub Dt:
05/11/2017
Title:
REDUCING THERMAL RUNAWAY IN INVERTER DEVICES
30
Patent #:
9466505
Issue Dt:
10/11/2016
Application #:
14935767
Filing Dt:
11/09/2015
Publication #:
US20160064236
Pub Dt:
03/03/2016
Title:
METHODS OF PATTERNING FEATURES HAVING DIFFERING WIDTHS
31
Patent #:
9659862
Issue Dt:
05/23/2017
Application #:
14936582
Filing Dt:
11/09/2015
Publication #:
US20170133319
Pub Dt:
05/11/2017
Title:
METHOD, APPARATUS, AND SYSTEM FOR E-FUSE IN ADVANCED CMOS TECHNOLOGIES
32
Patent #:
9548318
Issue Dt:
01/17/2017
Application #:
14936848
Filing Dt:
11/10/2015
Title:
CONNECTING TO BACK-PLATE CONTACTS OR DIODE JUNCTIONS THROUGH A RMG ELECTRODE AND RESULTING DEVICES
33
Patent #:
9548312
Issue Dt:
01/17/2017
Application #:
14937041
Filing Dt:
11/10/2015
Title:
METHOD INCLUDING A FORMATION OF A CONTROL GATE OF A NONVOLATILE MEMORY CELL AND SEMICONDUCTOR STRUCTURE INCLUDING A NONVOLATILE MEMORY CELL
34
Patent #:
9704807
Issue Dt:
07/11/2017
Application #:
14939251
Filing Dt:
11/12/2015
Publication #:
US20170141035
Pub Dt:
05/18/2017
Title:
PATTERN PLACEMENT ERROR COMPENSATION LAYER
35
Patent #:
9748176
Issue Dt:
08/29/2017
Application #:
14939319
Filing Dt:
11/12/2015
Publication #:
US20170141036
Pub Dt:
05/18/2017
Title:
PATTERN PLACEMENT ERROR COMPENSATION LAYER IN VIA OPENING
36
Patent #:
9633942
Issue Dt:
04/25/2017
Application #:
14939365
Filing Dt:
11/12/2015
Publication #:
US20170141027
Pub Dt:
05/18/2017
Title:
CONDUCTIVELY DOPED POLYMER PATTERN PLACEMENT ERROR COMPENSATION LAYER
37
Patent #:
9754829
Issue Dt:
09/05/2017
Application #:
14939464
Filing Dt:
11/12/2015
Publication #:
US20170140985
Pub Dt:
05/18/2017
Title:
SELF-ALIGNED CONDUCTIVE POLYMER PATTERN PLACEMENT ERROR COMPENSATION LAYER
38
Patent #:
9472558
Issue Dt:
10/18/2016
Application #:
14940499
Filing Dt:
11/13/2015
Title:
SEMICONDUCTOR STRUCTURES WITH STACKED NON-PLANAR FIELD EFFECT TRANSISTORS AND METHODS OF FORMING THE STRUCTURES
39
Patent #:
9799767
Issue Dt:
10/24/2017
Application #:
14940597
Filing Dt:
11/13/2015
Publication #:
US20170141226
Pub Dt:
05/18/2017
Title:
METHODS OF FORMING PMOS AND NMOS FINFET DEVICES ON CMOS BASED INTEGRATED CIRCUIT PRODUCTS
40
Patent #:
9748387
Issue Dt:
08/29/2017
Application #:
14940655
Filing Dt:
11/13/2015
Publication #:
US20170141227
Pub Dt:
05/18/2017
Title:
METHODS OF FORMING PMOS FINFET DEVICES AND MULTIPLE NMOS FINFET DEVICES WITH DIFFERENT PERFORMANCE CHARACTERISTICS
41
Patent #:
9740101
Issue Dt:
08/22/2017
Application #:
14940857
Filing Dt:
11/13/2015
Publication #:
US20170139324
Pub Dt:
05/18/2017
Title:
ADDITIONS OF ORGANIC SPECIES TO FACILITATE CROSSLINKER REMOVAL DURING PSPI CURE
42
Patent #:
9966182
Issue Dt:
05/08/2018
Application #:
14942311
Filing Dt:
11/16/2015
Publication #:
US20170140865
Pub Dt:
05/18/2017
Title:
MULTI-FREQUENCY INDUCTORS WITH LOW-K DIELECTRIC AREA
43
Patent #:
9412616
Issue Dt:
08/09/2016
Application #:
14942448
Filing Dt:
11/16/2015
Title:
METHODS OF FORMING SINGLE AND DOUBLE DIFFUSION BREAKS ON INTEGRATED CIRCUIT PRODUCTS COMPRISED OF FINFET DEVICES AND THE RESULTING PRODUCTS
44
Patent #:
9798244
Issue Dt:
10/24/2017
Application #:
14943086
Filing Dt:
11/17/2015
Publication #:
US20170139330
Pub Dt:
05/18/2017
Title:
METHODS, APPARATUS, AND SYSTEMS FOR MINIMIZING DEFECTIVITY IN TOP-COAT-FREE LITHOGRAPHY AND IMPROVING RETICLE CD UNIFORMITY
45
Patent #:
9484306
Issue Dt:
11/01/2016
Application #:
14943663
Filing Dt:
11/17/2015
Title:
MOSFET WITH ASYMMETRIC SELF-ALIGNED CONTACT
46
Patent #:
9502308
Issue Dt:
11/22/2016
Application #:
14944659
Filing Dt:
11/18/2015
Title:
METHODS FOR FORMING TRANSISTOR DEVICES WITH DIFFERENT SOURCE/DRAIN CONTACT LINERS AND THE RESULTING DEVICES
47
Patent #:
9484459
Issue Dt:
11/01/2016
Application #:
14944833
Filing Dt:
11/18/2015
Publication #:
US20160071978
Pub Dt:
03/10/2016
Title:
PERFORMANCE ENHANCEMENT IN TRANSISTORS BY PROVIDING AN EMBEDDED STRAIN-INDUCING SEMICONDUCTOR MATERIAL ON THE BASIS OF A SEED LAYER
48
Patent #:
10191108
Issue Dt:
01/29/2019
Application #:
14945520
Filing Dt:
11/19/2015
Publication #:
US20170146592
Pub Dt:
05/25/2017
Title:
ON-CHIP SENSOR FOR MONITORING ACTIVE CIRCUITS ON INTEGRATED CIRCUIT (IC) CHIPS
49
Patent #:
9767240
Issue Dt:
09/19/2017
Application #:
14945530
Filing Dt:
11/19/2015
Publication #:
US20170147727
Pub Dt:
05/25/2017
Title:
TEMPERATURE-AWARE INTEGRATED CIRCUIT DESIGN METHODS AND SYSTEMS
50
Patent #:
9607973
Issue Dt:
03/28/2017
Application #:
14946162
Filing Dt:
11/19/2015
Title:
METHOD FOR ESTABLISHING INTERCONNECTS IN PACKAGES USING THIN INTERPOSERS
51
Patent #:
9553061
Issue Dt:
01/24/2017
Application #:
14946208
Filing Dt:
11/19/2015
Title:
WIRING BOND PAD STRUCTURES
52
Patent #:
9679807
Issue Dt:
06/13/2017
Application #:
14948214
Filing Dt:
11/20/2015
Publication #:
US20170148669
Pub Dt:
05/25/2017
Title:
METHOD, APPARATUS, AND SYSTEM FOR MOL INTERCONNECTS WITHOUT TITANIUM LINER
53
Patent #:
9368453
Issue Dt:
06/14/2016
Application #:
14948476
Filing Dt:
11/23/2015
Publication #:
US20160079180
Pub Dt:
03/17/2016
Title:
OVERLAY MARK DEPENDENT DUMMY FILL TO MITIGATE GATE HEIGHT VARIATION
54
Patent #:
9590028
Issue Dt:
03/07/2017
Application #:
14948587
Filing Dt:
11/23/2015
Publication #:
US20160079342
Pub Dt:
03/17/2016
Title:
METHOD AND DEVICE FOR AN INTEGRATED TRENCH CAPACITOR
55
Patent #:
9606604
Issue Dt:
03/28/2017
Application #:
14951544
Filing Dt:
11/25/2015
Title:
ENERGY EFFICIENT HIGH-SPEED LINK AND METHOD TO MAXIMIZE ENERGY SAVINGS ON THE ENERGY EFFICIENT HIGH-SPEED LINK
56
Patent #:
9466538
Issue Dt:
10/11/2016
Application #:
14951634
Filing Dt:
11/25/2015
Title:
METHOD TO ACHIEVE ULTRA-HIGH CHIP-TO-CHIP ALIGNMENT ACCURACY FOR WAFER-TO-WAFER BONDING PROCESS
57
Patent #:
9535807
Issue Dt:
01/03/2017
Application #:
14951815
Filing Dt:
11/25/2015
Publication #:
US20160077939
Pub Dt:
03/17/2016
Title:
RECOVERING FROM UNCORRECTED MEMORY ERRORS
58
Patent #:
9660050
Issue Dt:
05/23/2017
Application #:
14952549
Filing Dt:
11/25/2015
Publication #:
US20170148894
Pub Dt:
05/25/2017
Title:
REPLACEMENT LOW-K SPACER
59
Patent #:
9767300
Issue Dt:
09/19/2017
Application #:
14953426
Filing Dt:
11/30/2015
Publication #:
US20160085983
Pub Dt:
03/24/2016
Title:
MANAGING RESTRICTED TAGGED CONTENT ELEMENTS WITHIN A PUBLISHED MESSAGE
60
Patent #:
9825094
Issue Dt:
11/21/2017
Application #:
14953702
Filing Dt:
11/30/2015
Publication #:
US20170054005
Pub Dt:
02/23/2017
Title:
FINFET PCM ACCESS TRANSISTOR HAVING GATE-WRAPPED SOURCE AND DRAIN REGIONS
61
Patent #:
9741847
Issue Dt:
08/22/2017
Application #:
14953874
Filing Dt:
11/30/2015
Publication #:
US20170154994
Pub Dt:
06/01/2017
Title:
METHODS OF FORMING A CONTACT STRUCTURE FOR A VERTICAL CHANNEL SEMICONDUCTOR DEVICE AND THE RESULTING DEVICE
62
Patent #:
9520392
Issue Dt:
12/13/2016
Application #:
14954050
Filing Dt:
11/30/2015
Title:
SEMICONDUCTOR DEVICE INCLUDING FINFET AND FIN VARACTOR
63
Patent #:
NONE
Issue Dt:
Application #:
14954053
Filing Dt:
11/30/2015
Publication #:
US20170154763
Pub Dt:
06/01/2017
Title:
MASS SPECTROMETRY SYSTEM AND METHOD FOR CONTAMINANT IDENTIFICATION IN SEMICONDUCTOR FABRICATION
64
Patent #:
NONE
Issue Dt:
Application #:
14954112
Filing Dt:
11/30/2015
Publication #:
US20170154816
Pub Dt:
06/01/2017
Title:
AMORPHOUS METAL INTERCONNECTIONS BY SUBTRACTIVE ETCH
65
Patent #:
9761720
Issue Dt:
09/12/2017
Application #:
14954166
Filing Dt:
11/30/2015
Publication #:
US20170154995
Pub Dt:
06/01/2017
Title:
REPLACEMENT BODY FINFET FOR IMPROVED JUNCTION PROFILE WITH GATE SELF-ALIGNED JUNCTIONS
66
Patent #:
9466567
Issue Dt:
10/11/2016
Application #:
14957842
Filing Dt:
12/03/2015
Publication #:
US20160086886
Pub Dt:
03/24/2016
Title:
NANOWIRE COMPATIBLE E-FUSE
67
Patent #:
9728506
Issue Dt:
08/08/2017
Application #:
14957860
Filing Dt:
12/03/2015
Publication #:
US20170162508
Pub Dt:
06/08/2017
Title:
STRAIN ENGINEERING DEVICES USING PARTIAL DEPTH FILMS IN THROUGH-SUBSTRATE VIAS
68
Patent #:
9653566
Issue Dt:
05/16/2017
Application #:
14958345
Filing Dt:
12/03/2015
Publication #:
US20160087073
Pub Dt:
03/24/2016
Title:
BIPOLAR JUNCTION TRANSISTORS WITH AN AIR GAP IN THE SHALLOW TRENCH ISOLATION
69
Patent #:
9859382
Issue Dt:
01/02/2018
Application #:
14959825
Filing Dt:
12/04/2015
Publication #:
US20170162656
Pub Dt:
06/08/2017
Title:
INTEGRATED CMOS WAFERS
70
Patent #:
9425108
Issue Dt:
08/23/2016
Application #:
14960378
Filing Dt:
12/05/2015
Title:
METHOD TO PREVENT LATERAL EPITAXIAL GROWTH IN SEMICONDUCTOR DEVICES
71
Patent #:
9590074
Issue Dt:
03/07/2017
Application #:
14960380
Filing Dt:
12/05/2015
Title:
METHOD TO PREVENT LATERAL EPITAXIAL GROWTH IN SEMICONDUCTOR DEVICES
72
Patent #:
9659604
Issue Dt:
05/23/2017
Application #:
14961484
Filing Dt:
12/07/2015
Publication #:
US20170162234
Pub Dt:
06/08/2017
Title:
DUAL-BIT 3-T HIGH DENSITY MTPROM ARRAY
73
Patent #:
9773867
Issue Dt:
09/26/2017
Application #:
14962015
Filing Dt:
12/08/2015
Publication #:
US20160093692
Pub Dt:
03/31/2016
Title:
FINFET SEMICONDUCTOR DEVICES WITH REPLACEMENT GATE STRUCTURES
74
Patent #:
9704971
Issue Dt:
07/11/2017
Application #:
14963397
Filing Dt:
12/09/2015
Publication #:
US20170170291
Pub Dt:
06/15/2017
Title:
EPI FACET HEIGHT UNIFORMITY IMPROVEMENT FOR FDSOI TECHNOLOGIES
75
Patent #:
9461128
Issue Dt:
10/04/2016
Application #:
14963789
Filing Dt:
12/09/2015
Publication #:
US20160093704
Pub Dt:
03/31/2016
Title:
METHOD FOR CREATING SELF-ALIGNED TRANSISTOR CONTACTS
76
Patent #:
NONE
Issue Dt:
Application #:
14964228
Filing Dt:
12/09/2015
Publication #:
US20170170048
Pub Dt:
06/15/2017
Title:
WAFER HANDLER FOR INFRARED LASER RELEASE
77
Patent #:
9571111
Issue Dt:
02/14/2017
Application #:
14964327
Filing Dt:
12/09/2015
Title:
SYSTEM AND METHOD TO SPEED UP PLL LOCK TIME ON SUBSEQUENT CALIBRATIONS VIA STORED BAND VALUES
78
Patent #:
9589850
Issue Dt:
03/07/2017
Application #:
14964746
Filing Dt:
12/10/2015
Title:
METHOD FOR CONTROLLED RECESSING OF MATERIALS IN CAVITIES IN IC DEVICES
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Patent #:
9570397
Issue Dt:
02/14/2017
Application #:
14964786
Filing Dt:
12/10/2015
Title:
LOCAL INTERCONNECT STRUCTURE INCLUDING NON-ERODED CONTACT VIA TRENCHES
80
Patent #:
9520396
Issue Dt:
12/13/2016
Application #:
14965193
Filing Dt:
12/10/2015
Publication #:
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Pub Dt:
04/21/2016
Title:
METHOD FOR MAKING HIGH VOLTAGE INTEGRATED CIRCUIT DEVICES IN A FIN-TYPE PROCESS AND RESULTING DEVICES
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Patent #:
9590082
Issue Dt:
03/07/2017
Application #:
14965267
Filing Dt:
12/10/2015
Title:
INTEGRATION OF HETEROJUNCTION BIPOLAR TRANSISTORS WITH DIFFERENT BASE PROFILES
82
Patent #:
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Issue Dt:
09/18/2018
Application #:
14966781
Filing Dt:
12/11/2015
Publication #:
US20170168242
Pub Dt:
06/15/2017
Title:
WAVEGUIDE STRUCTURES USED IN PHONOTICS CHIP PACKAGING
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Patent #:
9503106
Issue Dt:
11/22/2016
Application #:
14966881
Filing Dt:
12/11/2015
Title:
FREQUENCY-LOCKED VOLTAGE REGULATED LOOP
84
Patent #:
NONE
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Application #:
14967755
Filing Dt:
12/14/2015
Publication #:
US20170170016
Pub Dt:
06/15/2017
Title:
MULTIPLE PATTERNING METHOD FOR SUBSTRATE
85
Patent #:
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Issue Dt:
01/17/2017
Application #:
14967946
Filing Dt:
12/14/2015
Title:
METHOD AND STRUCTURE FOR III-V NANOWIRE TUNNEL FETS
86
Patent #:
9590056
Issue Dt:
03/07/2017
Application #:
14967983
Filing Dt:
12/14/2015
Publication #:
US20160099321
Pub Dt:
04/07/2016
Title:
SEMICONDUCTOR DEVICE COMPRISING CONTACT STRUCTURES WITH PROTECTION LAYERS FORMED ON SIDEWALLS OF CONTACT ETCH STOP LAYERS
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Patent #:
9595518
Issue Dt:
03/14/2017
Application #:
14969449
Filing Dt:
12/15/2015
Title:
FIN-TYPE METAL-SEMICONDUCTOR RESISTORS AND FABRICATION METHODS THEREOF
88
Patent #:
NONE
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Application #:
14969772
Filing Dt:
12/15/2015
Publication #:
US20170169934
Pub Dt:
06/15/2017
Title:
PATTERNED MAGNETIC SHIELDS FOR INDUCTORS AND TRANSFORMERS
89
Patent #:
9704962
Issue Dt:
07/11/2017
Application #:
14970661
Filing Dt:
12/16/2015
Publication #:
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Pub Dt:
06/22/2017
Title:
HORIZONTAL GATE ALL AROUND NANOWIRE TRANSISTOR BOTTOM ISOLATION
90
Patent #:
9941300
Issue Dt:
04/10/2018
Application #:
14970725
Filing Dt:
12/16/2015
Publication #:
US20170179156
Pub Dt:
06/22/2017
Title:
STRUCTURE AND METHOD FOR FULLY DEPLETED SILICON ON INSULATOR STRUCTURE FOR THRESHOLD VOLTAGE MODIFICATION
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Patent #:
9940986
Issue Dt:
04/10/2018
Application #:
14971644
Filing Dt:
12/16/2015
Publication #:
US20170178704
Pub Dt:
06/22/2017
Title:
ELECTROSTATIC DISCHARGE PROTECTION STRUCTURES FOR EFUSES
92
Patent #:
9620380
Issue Dt:
04/11/2017
Application #:
14972804
Filing Dt:
12/17/2015
Title:
METHODS FOR FABRICATING INTEGRATED CIRCUITS USING SELF-ALIGNED QUADRUPLE PATTERNING
93
Patent #:
NONE
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Application #:
14974136
Filing Dt:
12/18/2015
Publication #:
US20170179127
Pub Dt:
06/22/2017
Title:
SEMICONDUCTOR STRUCTURE HAVING SILICON GERMANIUM FINS AND METHOD OF FABRICATING SAME
94
Patent #:
9640633
Issue Dt:
05/02/2017
Application #:
14974589
Filing Dt:
12/18/2015
Title:
SELF ALIGNED GATE SHAPE PREVENTING VOID FORMATION
95
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10186482
Issue Dt:
01/22/2019
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14975726
Filing Dt:
12/19/2015
Publication #:
US20160104677
Pub Dt:
04/14/2016
Title:
SELF ALIGNED VIA FUSE
96
Patent #:
9559051
Issue Dt:
01/31/2017
Application #:
14976417
Filing Dt:
12/21/2015
Title:
METHOD FOR MANUFACTURING IN A SEMICONDUCTOR DEVICE A LOW RESISTANCE VIA WITHOUT A BOTTOM LINER
97
Patent #:
9712413
Issue Dt:
07/18/2017
Application #:
14976530
Filing Dt:
12/21/2015
Publication #:
US20160110244
Pub Dt:
04/21/2016
Title:
SYSTEMS AND METHODS FOR MANAGING COMPUTING SYSTEMS UTILIZING AUGMENTED REALITY
98
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9793168
Issue Dt:
10/17/2017
Application #:
14977387
Filing Dt:
12/21/2015
Publication #:
US20160111335
Pub Dt:
04/21/2016
Title:
SEMICONDUCTOR STRUCTURE WITH SELF-ALIGNED WELLS AND MULTIPLE CHANNEL MATERIALS
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Patent #:
9536870
Issue Dt:
01/03/2017
Application #:
14977737
Filing Dt:
12/22/2015
Publication #:
US20160111414
Pub Dt:
04/21/2016
Title:
SCR WITH FIN BODY REGIONS FOR ESD PROTECTION
100
Patent #:
9601513
Issue Dt:
03/21/2017
Application #:
14977899
Filing Dt:
12/22/2015
Title:
SUBSURFACE WIRES OF INTEGRATED CHIP AND METHODS OF FORMING
Assignor
1
GLOBALFOUNDRIES INC.
Exec Dt:
11/27/2018
Assignee
1
WILMINGTON TRUST, NATIONAL ASSOCIATION
1100 NORTH MARKET STREET
WILMINGTON, DELAWARE 19801
Correspondence name and address
CT CORPORATION
4400 EASTON COMMONS WAY
SUITE 125
COLUMBUS, OH 43219

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