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06/22/2017
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06/29/2017
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04/28/2016
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06/29/2017
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10/13/2016
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05/04/2017
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06/29/2017
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06/29/2017
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05/12/2016
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07/06/2017
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04/21/2016
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06/28/2016
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04/28/2016
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09/13/2016
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07/11/2017
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01/07/2016
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04/28/2016
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07/19/2016
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07/13/2017
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07/13/2017
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07/13/2017
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01/12/2016
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07/13/2017
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07/13/2017
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07/13/2017
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05/12/2016
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07/18/2017
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07/20/2017
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12/06/2016
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05/19/2016
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07/20/2017
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12/26/2017
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07/27/2017
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04/18/2017
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07/27/2017
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10/10/2017
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07/27/2017
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03/07/2017
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07/27/2017
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07/27/2017
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01/25/2016
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07/27/2017
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08/15/2017
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01/26/2016
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07/27/2017
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10/17/2017
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07/27/2017
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03/28/2017
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11/29/2016
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01/29/2016
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08/03/2017
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01/29/2016
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08/03/2017
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12/12/2017
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02/01/2016
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08/03/2017
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11/22/2016
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09/12/2017
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08/03/2017
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05/09/2017
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15012563
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11/29/2016
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02/01/2016
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06/09/2016
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10/01/2019
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02/02/2016
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08/03/2017
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08/29/2017
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15013169
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02/02/2016
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08/03/2017
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11/07/2017
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15013393
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Filing Dt:
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02/02/2016
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Publication #:
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Pub Dt:
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08/03/2017
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Title:
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BIPOLAR JUNCTION TRANSISTORS WITH EXTRINSIC DEVICE REGIONS FREE OF TRENCH ISOLATION
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Patent #:
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Issue Dt:
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08/01/2017
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Application #:
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15013411
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Filing Dt:
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02/02/2016
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Publication #:
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Pub Dt:
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08/03/2017
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Title:
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SWITCH IMPROVEMENT USING LAYOUT OPTIMIZATION
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Patent #:
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Issue Dt:
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09/04/2018
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Application #:
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15013956
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Filing Dt:
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02/02/2016
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Publication #:
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Pub Dt:
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08/03/2017
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Title:
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METHOD, APPARATUS AND SYSTEM FOR VOLTAGE COMPENSATION IN A SEMICONDUCTOR WAFER
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Patent #:
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Issue Dt:
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08/15/2017
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Application #:
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15014150
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Filing Dt:
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02/03/2016
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Publication #:
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Pub Dt:
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08/03/2017
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Title:
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METHODS TO FORM MULTI THRESHOLD-VOLTAGE DUAL CHANNEL WITHOUT CHANNEL DOPING
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Patent #:
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Issue Dt:
|
06/06/2017
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Application #:
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15014212
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Filing Dt:
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02/03/2016
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Title:
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METHODS TO UTILIZE PIEZOELECTRIC MATERIALS AS GATE DIELECTRIC IN HIGH FREQUENCY RBTs IN AN IC DEVICE
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Patent #:
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Issue Dt:
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08/07/2018
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Application #:
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15014479
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Filing Dt:
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02/03/2016
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Publication #:
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Pub Dt:
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08/03/2017
| | | | |
Title:
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GIMBAL ASSEMBLY TEST SYSTEM AND METHOD
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Patent #:
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Issue Dt:
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09/12/2017
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Application #:
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15014759
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Filing Dt:
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02/03/2016
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Publication #:
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Pub Dt:
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08/03/2017
| | | | |
Title:
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INTERCONNECT STRUCTURE HAVING TUNGSTEN CONTACT COPPER WIRING
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Patent #:
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Issue Dt:
|
03/06/2018
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Application #:
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15015176
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Filing Dt:
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02/04/2016
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Publication #:
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Pub Dt:
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08/10/2017
| | | | |
Title:
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APPARATUS AND METHOD FOR VECTOR S-PARAMETER MEASUREMENTS
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Patent #:
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Issue Dt:
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08/21/2018
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Application #:
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15015478
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Filing Dt:
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02/04/2016
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Publication #:
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Pub Dt:
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08/10/2017
| | | | |
Title:
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TEST STRUCUTRE FOR MONITORING INTERFACE DELAMINATION
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Patent #:
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Issue Dt:
|
05/16/2017
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Application #:
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15015535
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Filing Dt:
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02/04/2016
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Title:
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THRESHOLD VOLTAGE (VT)-TYPE TRANSISTOR SENSITIVE AND/OR FAN-OUT SENSITIVE SELECTIVE VOLTAGE BINNING
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Patent #:
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Issue Dt:
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01/16/2018
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Application #:
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15015578
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Filing Dt:
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02/04/2016
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Publication #:
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Pub Dt:
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06/02/2016
| | | | |
Title:
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WAFER CARRIER PURGE APPARATUSES, AUTOMATED MECHANICAL HANDLING SYSTEMS INCLUDING THE SAME, AND METHODS OF HANDLING A WAFER CARRIER DURING INTEGRATED CIRCUIT FABRICATION
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Patent #:
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Issue Dt:
|
06/12/2018
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Application #:
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15015614
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Filing Dt:
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02/04/2016
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Publication #:
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Pub Dt:
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08/18/2016
| | | | |
Title:
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SYSTEMS AND METHODS OF CONTROLLING A MANUFACTURING PROCESS FOR A MICROELECTRONIC COMPONENT
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Patent #:
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Issue Dt:
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12/26/2017
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Application #:
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15017004
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Filing Dt:
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02/05/2016
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Publication #:
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Pub Dt:
|
08/10/2017
| | | | |
Title:
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CORROSION RESISTANT CHIP SIDEWALL CONNECTION WITH CRACKSTOP AND HERMETIC SEAL
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Patent #:
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Issue Dt:
|
04/17/2018
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Application #:
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15019273
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Filing Dt:
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02/09/2016
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Publication #:
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Pub Dt:
|
08/10/2017
| | | | |
Title:
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DEVICE WITH DIFFUSION BLOCKING LAYER IN SOURCE/DRAIN REGION
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Patent #:
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Issue Dt:
|
11/26/2019
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Application #:
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15019590
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Filing Dt:
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02/09/2016
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Publication #:
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Pub Dt:
|
08/10/2017
| | | | |
Title:
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MEMORY BUILT-IN SELF-TEST (MBIST) TEST TIME REDUCTION
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Patent #:
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Issue Dt:
|
11/29/2016
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Application #:
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15024633
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Filing Dt:
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03/25/2016
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Publication #:
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Pub Dt:
|
08/18/2016
| | | | |
Title:
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LIGHT EMITTING DIODE (LED) DIMMER CIRCUIT AND DIMMING METHOD FOR LEDS
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Patent #:
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Issue Dt:
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10/24/2017
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Application #:
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15040235
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Filing Dt:
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02/10/2016
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Publication #:
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Pub Dt:
|
12/29/2016
| | | | |
Title:
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METHODS OF DESIGN RULE CHECKING OF CIRCUIT DESIGNS
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Patent #:
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Issue Dt:
|
12/06/2016
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Application #:
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15040278
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Filing Dt:
|
02/10/2016
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Title:
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HIGH DENSITY AND MODULAR CMOS LOGIC BASED ON 3D STACKED, INDEPENDENT-GATE, JUNCTIONLESS FINFETS
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Patent #:
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Issue Dt:
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04/24/2018
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Application #:
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15040307
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Filing Dt:
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02/10/2016
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Publication #:
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Pub Dt:
|
06/09/2016
| | | | |
Title:
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MULTI-GATE FIELD EFFECT TRANSISTOR (FET) INCLUDING ISOLATED FIN BODY
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Patent #:
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Issue Dt:
|
02/20/2018
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Application #:
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15040453
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Filing Dt:
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02/10/2016
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Publication #:
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Pub Dt:
|
08/10/2017
| | | | |
Title:
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DESIGN RULE AND PROCESS ASSUMPTION CO-OPTIMIZATION USING FEATURE-SPECIFIC LAYOUT-BASED STATISTICAL ANALYSES
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Patent #:
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Issue Dt:
|
03/21/2017
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Application #:
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15040953
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Filing Dt:
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02/10/2016
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Publication #:
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Pub Dt:
|
06/09/2016
| | | | |
Title:
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FINFET WORK FUNCTION METAL FORMATION
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Patent #:
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Issue Dt:
|
07/11/2017
|
Application #:
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15041103
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Filing Dt:
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02/11/2016
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Publication #:
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Pub Dt:
|
06/16/2016
| | | | |
Title:
|
OPTOELECTRONIC STRUCTURES HAVING MULTI-LEVEL OPTICAL WAVEGUIDES AND METHODS OF FORMING THE STRUCTURES
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Patent #:
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Issue Dt:
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10/17/2017
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Application #:
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15041476
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Filing Dt:
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02/11/2016
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Publication #:
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Pub Dt:
|
08/17/2017
| | | | |
Title:
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A PHOTOMASK STRUCTURE WITH AN ETCH STOP LAYER THAT ENABLES REPAIRS OF DETECTED DEFECTS THEREIN AND EXTREME ULTRAVIOLET (EUV) PHOTOLITHOGRAPHY METHODS USING THE PHOTOMASK STRUCTURE
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Patent #:
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Issue Dt:
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01/03/2017
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Application #:
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15041581
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Filing Dt:
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02/11/2016
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Publication #:
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Pub Dt:
|
06/09/2016
| | | | |
Title:
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SEMICONDUCTOR STRUCTURE INCLUDING A FERROELECTRIC TRANSISTOR AND METHOD FOR THE FORMATION THEREOF
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Patent #:
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Issue Dt:
|
07/04/2017
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Application #:
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15042547
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Filing Dt:
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02/12/2016
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Publication #:
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Pub Dt:
|
02/09/2017
| | | | |
Title:
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CAPACITOR STRUCTURE AND METHOD OF FORMING A CAPACITOR STRUCTURE
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Patent #:
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Issue Dt:
|
10/30/2018
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Application #:
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15042815
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Filing Dt:
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02/12/2016
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Publication #:
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Pub Dt:
|
08/17/2017
| | | | |
Title:
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PLACING AND ROUTING METHOD FOR IMPLEMENTING BACK BIAS IN FDSOI
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Patent #:
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Issue Dt:
|
09/27/2016
|
Application #:
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15044219
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Filing Dt:
|
02/16/2016
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Title:
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METHODS OF FORMING STRAINED AND RELAXED GERMANIUM FINS FOR PMOS AND NMOS FINFET DEVICES, RESPECTIVELY
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Patent #:
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Issue Dt:
|
10/10/2017
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Application #:
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15044431
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Filing Dt:
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02/16/2016
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Publication #:
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Pub Dt:
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08/17/2017
| | | | |
Title:
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FINFET HAVING NOTCHED FINS AND METHOD OF FORMING SAME
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Patent #:
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Issue Dt:
|
02/20/2018
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Application #:
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15045466
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Filing Dt:
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02/17/2016
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Publication #:
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Pub Dt:
|
08/17/2017
| | | | |
Title:
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METAL LINE LAYOUT BASED ON LINE SHIFTING
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Patent #:
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Issue Dt:
|
05/30/2017
|
Application #:
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15046245
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Filing Dt:
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02/17/2016
|
Title:
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MEMS-BASED RESONANT FINFET
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Patent #:
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Issue Dt:
|
06/18/2019
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Application #:
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15046496
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Filing Dt:
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02/18/2016
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Publication #:
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Pub Dt:
|
06/09/2016
| | | | |
Title:
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CHEMICAL MECHANICAL POLISHING APPARATUS
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Patent #:
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Issue Dt:
|
03/07/2017
|
Application #:
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15046916
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Filing Dt:
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02/18/2016
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Title:
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METAL LAYER TIP TO TIP SHORT
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Patent #:
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Issue Dt:
|
03/21/2017
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Application #:
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15046983
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Filing Dt:
|
02/18/2016
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Title:
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METHOD, APPARATUS, AND SYSTEM FOR GLOBAL HEALING OF STABILITY-LIMITED DIE THROUGH BIAS TEMPERATURE INSTABILITY
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Patent #:
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Issue Dt:
|
09/12/2017
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Application #:
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15047137
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Filing Dt:
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02/18/2016
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Publication #:
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Pub Dt:
|
08/24/2017
| | | | |
Title:
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METHODS OF FORMING FIELD EFFECT TRANSISTOR (FET) AND NON-FET CIRCUIT ELEMENTS ON A SEMICONDUCTOR-ON-INSULATOR SUBSTRATE
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Patent #:
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Issue Dt:
|
03/21/2017
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Application #:
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15047139
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Filing Dt:
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02/18/2016
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Title:
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METHOD, APPARATUS AND SYSTEM FOR TARGETED HEALING OF STABILITY FAILURES THROUGH BIAS TEMPERATURE INSTABILITY
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Patent #:
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Issue Dt:
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07/11/2017
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Application #:
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15047271
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Filing Dt:
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02/18/2016
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Title:
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METHOD, APPARATUS, AND SYSTEM FOR GLOBAL HEALING OF WRITE-LIMITED DIE THROUGH BIAS TEMPERATURE INSTABILITY
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Patent #:
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Issue Dt:
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03/13/2018
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Application #:
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15047395
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Filing Dt:
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02/18/2016
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Publication #:
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Pub Dt:
|
08/24/2017
| | | | |
Title:
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METHOD, APPARATUS, AND SYSTEM FOR TARGETED HEALING OF WRITE FAILS THROUGH BIAS TEMPERATURE INSTABILITY
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Patent #:
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Issue Dt:
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12/12/2017
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Application #:
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15047878
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Filing Dt:
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02/19/2016
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Publication #:
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Pub Dt:
|
03/16/2017
| | | | |
Title:
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METHOD, APPARATUS AND SYSTEM FOR USING HYBRID LIBRARY TRACK DESIGN FOR SOI TECHNOLOGY
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Patent #:
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Issue Dt:
|
09/05/2017
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Application #:
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15048066
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Filing Dt:
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02/19/2016
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Publication #:
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Pub Dt:
|
08/24/2017
| | | | |
Title:
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INTEGRATED CIRCUIT (IC) DESIGN ANALYSIS AND FEATURE EXTRACTION
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