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Patent #:
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Issue Dt:
|
04/15/2003
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Application #:
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09771262
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Filing Dt:
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01/26/2001
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Publication #:
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Pub Dt:
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08/01/2002
| | | | |
Title:
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SUBSTITUTED NORBORNENE FLUOROACRYLATE COPOLYMERS AND USE THEREOF IN LITHOGRAPHIC PHOTORESIST COMPOSITIONS
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Patent #:
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|
Issue Dt:
|
07/08/2003
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Application #:
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09771820
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Filing Dt:
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01/29/2001
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Title:
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PROCESS FOR REDUCING THE PITCH OF CONTACT HOLES, VIAS, AND TRENCH STRUCTURES IN INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
|
12/31/2002
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Application #:
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09772205
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Filing Dt:
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01/29/2001
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Publication #:
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|
Pub Dt:
|
10/10/2002
| | | | |
Title:
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METHOD OF FORMING RECESSED THIN FILM LANDING PAD STRUCTURE
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Patent #:
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|
Issue Dt:
|
06/17/2003
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Application #:
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09772345
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Filing Dt:
|
01/30/2001
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Publication #:
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|
Pub Dt:
|
08/01/2002
| | | | |
Title:
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METHOD FOR DELINEATION OF EDRAM SUPPORT DEVICE NOTCHED GATE
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Patent #:
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|
Issue Dt:
|
03/18/2003
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Application #:
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09772577
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Filing Dt:
|
01/30/2001
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Publication #:
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|
Pub Dt:
|
08/01/2002
| | | | |
Title:
|
PHASE SHIFT MASK AND SYSTEM AND METHOD FOR MAKING THE SAME
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Patent #:
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|
Issue Dt:
|
05/20/2003
|
Application #:
|
09772610
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Filing Dt:
|
01/30/2001
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Title:
|
SEMICONDUCTOR-ON-INSULATOR (SOI) TUNNELING JUNCTION TRANSISTOR
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|
Patent #:
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|
Issue Dt:
|
09/03/2002
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Application #:
|
09772649
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Filing Dt:
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01/30/2001
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Title:
|
SOI SEMICONDUCTOR DEVICE OPENING IMPLANTATION GETTERING METHOD
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Patent #:
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|
Issue Dt:
|
03/25/2003
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Application #:
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09772889
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Filing Dt:
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01/31/2001
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Title:
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PACKAGING SUBSTRATE COMPRISING STAGGERED VIAS
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Patent #:
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|
Issue Dt:
|
01/21/2003
|
Application #:
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09773323
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Filing Dt:
|
01/31/2001
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Publication #:
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|
Pub Dt:
|
08/01/2002
| | | | |
Title:
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METHOD FOR WRITING AND/OR ERASING HIGH DENSITY DATA ON A MEDIA
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Patent #:
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|
Issue Dt:
|
10/22/2002
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Application #:
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09773488
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Filing Dt:
|
02/02/2001
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Publication #:
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Pub Dt:
|
10/04/2001
| | | | |
Title:
|
COMPOSITION FOR INCREASING ACTIVITY OF A NO-CLEAN FLUX
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|
Patent #:
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|
Issue Dt:
|
05/08/2007
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Application #:
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09773798
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Filing Dt:
|
02/01/2001
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Publication #:
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Pub Dt:
|
08/01/2002
| | | | |
Title:
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PASSIVATION FOR IMPROVED BIPOLAR YIELD
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|
Patent #:
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|
Issue Dt:
|
07/29/2003
|
Application #:
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09773906
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Filing Dt:
|
02/02/2001
|
Title:
|
PLASMA ETCH PROCESS FOR NONHOMOGENOUS FILM
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|
Patent #:
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|
Issue Dt:
|
12/31/2002
|
Application #:
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09773954
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Filing Dt:
|
02/01/2001
|
Title:
|
OPTICAL TECHNIQUE TO DETECT ETCH PROCESS TERMINATION
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|
Patent #:
|
|
Issue Dt:
|
07/30/2002
|
Application #:
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09774126
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Filing Dt:
|
01/30/2001
|
Publication #:
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|
Pub Dt:
|
08/01/2002
| | | | |
Title:
|
INCORPORATION OF CARBON IN SILICON/SILICON GERMANIUM EPITAXIAL LAYER TO ENHANCE YIELD FOR SI-GE BIPOLAR TECHNOLOGY
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|
Patent #:
|
|
Issue Dt:
|
04/30/2002
|
Application #:
|
09774138
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Filing Dt:
|
01/30/2001
|
Title:
|
SEMICONDUCTOR-ON-INSULATOR (SOI) TUNNELING JUNCTION TRANSISTOR SRAM CELL
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|
Patent #:
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|
Issue Dt:
|
12/31/2002
|
Application #:
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09774152
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Filing Dt:
|
01/30/2001
|
Publication #:
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|
Pub Dt:
|
08/01/2002
| | | | |
Title:
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FLIP CHIP PACKAGE WITH IMPROVED CAP DESIGN AND PROCESS FOR MAKING THEREOF
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Patent #:
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|
Issue Dt:
|
05/18/2004
|
Application #:
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09774489
|
Filing Dt:
|
01/31/2001
|
Publication #:
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|
Pub Dt:
|
09/26/2002
| | | | |
Title:
|
HEAD-MOUNTED DISPLAY CONTENT TRANSFORMER
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|
Patent #:
|
|
Issue Dt:
|
11/05/2002
|
Application #:
|
09774708
|
Filing Dt:
|
02/01/2001
|
Title:
|
METHOD OF MANUFACTURING A SEMICONDUCTOR STRUCTURE WITH TREATMENT TO SACRIFICIAL STOP LAYER PRODUCING DIFFUSION TO AN ADJACENT LOW-K DIELECTRIC LAYER LOWERING THE CONSTANT
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|
Patent #:
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|
Issue Dt:
|
04/02/2002
|
Application #:
|
09774939
|
Filing Dt:
|
01/31/2001
|
Title:
|
Dual gate process using self-assembled molecular layer
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|
Patent #:
|
|
Issue Dt:
|
07/19/2005
|
Application #:
|
09774943
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Filing Dt:
|
01/31/2001
|
Publication #:
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|
Pub Dt:
|
08/01/2002
| | | | |
Title:
|
ASSEMBLY FOR WRITING AND / OR ERASING HIGH DENSITY DATA ON A MEDIA
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|
Patent #:
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|
Issue Dt:
|
07/19/2005
|
Application #:
|
09775374
|
Filing Dt:
|
02/01/2001
|
Publication #:
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|
Pub Dt:
|
08/01/2002
| | | | |
Title:
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SYSTEM AND METHOD FOR REMOTE OPTICAL DIGITAL NETWORKING OF COMPUTING DEVICES
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|
Patent #:
|
|
Issue Dt:
|
05/18/2004
|
Application #:
|
09776077
|
Filing Dt:
|
02/01/2001
|
Title:
|
EFFICIENT SIMD QUANTIZATION METHOD
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|
|
Patent #:
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|
Issue Dt:
|
03/02/2004
|
Application #:
|
09776339
|
Filing Dt:
|
02/02/2001
|
Title:
|
PCI AND MII COMPATIBLE HOME PHONELINE NETWORKING ALLIANCE (HPNA) INTERFACE DEVICE
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|
|
Patent #:
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|
Issue Dt:
|
04/16/2002
|
Application #:
|
09776736
|
Filing Dt:
|
02/06/2001
|
Title:
|
METHOD FOR MAKING A SLOT VIA FILLED DUAL DAMASCENE LOW K INTERCONNECT STRUCTURE WITHOUT MIDDLE STOP LAYER
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|
|
Patent #:
|
|
Issue Dt:
|
02/25/2003
|
Application #:
|
09776748
|
Filing Dt:
|
02/06/2001
|
Title:
|
NICKEL SILICIDE PROCESS USING STARVED SILICON DIFFUSION BARRIER
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|
|
Patent #:
|
|
Issue Dt:
|
11/12/2002
|
Application #:
|
09777539
|
Filing Dt:
|
02/06/2001
|
Publication #:
|
|
Pub Dt:
|
06/28/2001
| | | | |
Title:
|
MULTI-WAFER POLISHING TOOL
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|
|
Patent #:
|
|
Issue Dt:
|
06/17/2003
|
Application #:
|
09777548
|
Filing Dt:
|
02/06/2001
|
Publication #:
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|
Pub Dt:
|
08/08/2002
| | | | |
Title:
|
SUPPORT AND ALIGNMENT DEVICE FOR ENABLING CHEMICAL MECHANICAL POLISHING RINSE AND FILM MEASUREMENTS
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|
Patent #:
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|
Issue Dt:
|
12/17/2002
|
Application #:
|
09777637
|
Filing Dt:
|
02/06/2001
|
Title:
|
SEMICONDUCTOR-ON-INSULATOR (SOI) DEVICE HAVING SOURCE/DRAIN SILICON-GERMANIUM REGIONS AND METHOD OF MANUFACTURE
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|
Patent #:
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|
Issue Dt:
|
12/02/2003
|
Application #:
|
09777695
|
Filing Dt:
|
02/07/2001
|
Title:
|
DUAL DAMASCENE WITH SILICON CARBIDE MIDDLE ETCH STOP LAYER/ARC
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|
|
Patent #:
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|
Issue Dt:
|
10/15/2002
|
Application #:
|
09778109
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Filing Dt:
|
02/07/2001
|
Title:
|
SILICON CARBIDE BARC IN DUAL DAMASCENE PROCESSING
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|
Patent #:
|
|
Issue Dt:
|
02/03/2004
|
Application #:
|
09778335
|
Filing Dt:
|
02/07/2001
|
Publication #:
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|
Pub Dt:
|
08/08/2002
| | | | |
Title:
|
DAMASCENE DOUBLE-GATE MOSFET STRUCTURE AND ITS FABRICATION METHOD
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|
|
Patent #:
|
|
Issue Dt:
|
05/28/2002
|
Application #:
|
09778352
|
Filing Dt:
|
02/06/2001
|
Publication #:
|
|
Pub Dt:
|
12/13/2001
| | | | |
Title:
|
FLOATING POINT ADDITION PIPELINE INCLUDING EXTREME VALUE, COMPARISON AND ACCUMULATE FUNCTIONS
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|
Patent #:
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|
Issue Dt:
|
06/17/2003
|
Application #:
|
09778529
|
Filing Dt:
|
02/07/2001
|
Title:
|
ACCURATE CONTACT CRITICAL DIMENSION MEASUREMENT USING VARIABLE THRESHOLD METHOD
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|
|
Patent #:
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|
Issue Dt:
|
06/10/2003
|
Application #:
|
09778586
|
Filing Dt:
|
02/07/2001
|
Title:
|
TRI-TONE MASK PROCESS FOR DENSE AND ISOLATED PATTERNS
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|
|
Patent #:
|
|
Issue Dt:
|
06/24/2003
|
Application #:
|
09778777
|
Filing Dt:
|
02/08/2001
|
Title:
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SEMICONDUCTOR DEVICE HAVING A LOW DIELECTRIC CONSTANT MATERIAL
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|
|
Patent #:
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|
Issue Dt:
|
04/22/2003
|
Application #:
|
09779986
|
Filing Dt:
|
02/09/2001
|
Title:
|
LOW TEMPERATURE PROCESS FOR A THIN FILM TRANSISTOR
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|
|
Patent #:
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|
Issue Dt:
|
06/11/2002
|
Application #:
|
09779987
|
Filing Dt:
|
02/09/2001
|
Title:
|
PROCESS FOR MANUFACTURING MOS TRANSISTORS HAVING ELEVATED SOURCE AND DRAIN REGIONS AND A HIGH-K GATE DIELECTRIC
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|
Patent #:
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|
Issue Dt:
|
01/06/2004
|
Application #:
|
09780275
|
Filing Dt:
|
02/09/2001
|
Publication #:
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|
Pub Dt:
|
10/10/2002
| | | | |
Title:
|
ATTENUATING EXTREME ULTRAVIOLET (EUV) PHASE-SHIFTING MASK FABRICATION METHOD
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|
|
Patent #:
|
|
Issue Dt:
|
10/01/2002
|
Application #:
|
09780454
|
Filing Dt:
|
02/12/2001
|
Title:
|
METHOD OF MAKING A SILICIDE STOP LAYER IN A DAMASCENE SEMICONDUCTOR STRUCTURE
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|
|
Patent #:
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|
Issue Dt:
|
09/21/2004
|
Application #:
|
09780558
|
Filing Dt:
|
02/09/2001
|
Publication #:
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|
Pub Dt:
|
08/15/2002
| | | | |
Title:
|
METHOD AND SYSTEM FOR FAULT-TOLERANT STATIC TIMING ANALYSIS
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|
|
Patent #:
|
|
Issue Dt:
|
03/18/2003
|
Application #:
|
09781014
|
Filing Dt:
|
02/10/2001
|
Publication #:
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|
Pub Dt:
|
08/15/2002
| | | | |
Title:
|
HIGH Q INDUCTOR WITH FARADAY SHIELD AND DIELECTRIC WELL BURIED IN SUBSTRATE
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|
|
Patent #:
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|
Issue Dt:
|
12/17/2002
|
Application #:
|
09781039
|
Filing Dt:
|
02/09/2001
|
Title:
|
LOW TEMPERATURE PROCESS TO LOCALLY FORM HIGH-K GATE DIELECTRICS
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|
|
Patent #:
|
|
Issue Dt:
|
03/18/2003
|
Application #:
|
09781121
|
Filing Dt:
|
02/09/2001
|
Publication #:
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|
Pub Dt:
|
08/15/2002
| | | | |
Title:
|
COMMON BALL-LIMITING METALLURGY FOR I/O SITES
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|
|
Patent #:
|
|
Issue Dt:
|
04/30/2002
|
Application #:
|
09781225
|
Filing Dt:
|
02/13/2001
|
Title:
|
ENHANCEMENT OF NICKEL SILICIDE FORMATION BY USE OF NICKEL PRE-AMORPHIZING IMPLANT
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|
|
Patent #:
|
|
Issue Dt:
|
04/16/2002
|
Application #:
|
09781256
|
Filing Dt:
|
02/13/2001
|
Title:
|
SILICON-STARVED NITRIDE SPACER DEPOSITION
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|
Patent #:
|
|
Issue Dt:
|
04/30/2002
|
Application #:
|
09781357
|
Filing Dt:
|
02/12/2001
|
Title:
|
LOW TEMPERATURE PROCESS TO FORM ELEVATED DRAIN AND SOURCE OF A FIELD EFFECT TRANSISTOR HAVING HIGH-K GATE DIELECTRIC
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|
|
Patent #:
|
|
Issue Dt:
|
06/18/2002
|
Application #:
|
09781364
|
Filing Dt:
|
02/12/2001
|
Title:
|
FABRICATION OF FULLY DEPLETED FIELD EFFECT TRANSISTOR WITH RAISED SOURCE AND DRAIN IN SOI TECHNOLOGY
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|
|
Patent #:
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|
Issue Dt:
|
03/18/2003
|
Application #:
|
09781637
|
Filing Dt:
|
02/12/2001
|
Publication #:
|
|
Pub Dt:
|
06/28/2001
| | | | |
Title:
|
SEMICONDUCTOR DEVICE HAVING A THERMOSET-CONTAINING DIELECTRIC MATERIAL AND METHODS FOR FABRICATING THE SAME
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|
|
Patent #:
|
|
Issue Dt:
|
05/28/2002
|
Application #:
|
09781783
|
Filing Dt:
|
02/12/2001
|
Title:
|
FABRICATION OF FULLY DEPLETED FIELD EFFECT TRANSISTOR WITH HIGH-K GATE DIELECTRIC IN SOI TECHNOLOGY
|
|
|
Patent #:
|
|
Issue Dt:
|
11/04/2003
|
Application #:
|
09783204
|
Filing Dt:
|
02/15/2001
|
Title:
|
METHOD AND APPARATUS FOR DETERMINING AN ETCH ENDPOINT
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|
|
Patent #:
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|
Issue Dt:
|
04/27/2004
|
Application #:
|
09784790
|
Filing Dt:
|
02/15/2001
|
Title:
|
CHANNEL ISOLATION USING DIELECTRIC ISOLATION STRUCTURES
|
|
|
Patent #:
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|
Issue Dt:
|
04/09/2002
|
Application #:
|
09784842
|
Filing Dt:
|
02/15/2001
|
Title:
|
METHOD FOR LOW STRESS PLATING OF SEMICONDUCTOR VIAS AND CHANNELS
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|
|
Patent #:
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|
Issue Dt:
|
08/27/2002
|
Application #:
|
09785176
|
Filing Dt:
|
02/20/2001
|
Title:
|
NISI CONTACTING EXTENSIONS OF ACTIVE REGIONS
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|
|
Patent #:
|
|
Issue Dt:
|
12/24/2002
|
Application #:
|
09785432
|
Filing Dt:
|
02/16/2001
|
Publication #:
|
|
Pub Dt:
|
08/22/2002
| | | | |
Title:
|
CONDUCTIVE COUPLING OF ELECTRICAL STRUCTURES TO A SEMICONDUCTOR DEVICE LOCATED UNDER A BURIED OXIDE LAYER
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|
|
Patent #:
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|
Issue Dt:
|
10/15/2002
|
Application #:
|
09785444
|
Filing Dt:
|
02/20/2001
|
Title:
|
METHOD FOR PREVENTING DAMAGE OF LOW-K DIELECTRICS DURING PATTERNING
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|
|
Patent #:
|
|
Issue Dt:
|
11/25/2003
|
Application #:
|
09785609
|
Filing Dt:
|
02/16/2001
|
Publication #:
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|
Pub Dt:
|
08/22/2002
| | | | |
Title:
|
RADIATION SENSITIVE SILICON-CONTAINING NEGATIVE RESISTS AND USE THEREOF
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|
|
Patent #:
|
|
Issue Dt:
|
05/28/2002
|
Application #:
|
09788027
|
Filing Dt:
|
02/16/2001
|
Title:
|
METHOD AND CIRCUIT FOR PRELOADING PREDICTION CIRCUITS IN MICROPROCESSORS
|
|
|
Patent #:
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|
Issue Dt:
|
05/21/2002
|
Application #:
|
09788067
|
Filing Dt:
|
02/16/2001
|
Title:
|
PHYSICAL RENAME REGISTER FOR EFFICIENTLY STORING FLOATING POINT, INTEGER, CONDITION CODE, AND MULTIMEDIA VALUES
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|
|
Patent #:
|
|
Issue Dt:
|
09/30/2003
|
Application #:
|
09788631
|
Filing Dt:
|
02/16/2001
|
Publication #:
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|
Pub Dt:
|
06/28/2001
| | | | |
Title:
|
METHOD OF DESIGNING AND STRUCTURE FOR VISUAL AND ELECTRICAL TEST OF SEMICONDUCTOR DEVICES
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|
|
Patent #:
|
|
Issue Dt:
|
04/27/2004
|
Application #:
|
09788635
|
Filing Dt:
|
02/21/2001
|
Publication #:
|
|
Pub Dt:
|
10/10/2002
| | | | |
Title:
|
GUI FOR REPRESENTING ENTITY MATCHES UTILIZING GRAPHICAL TRANSITIONS PERFORMED DIRECTLY ON THE MATCHING OBJECT
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|
|
Patent #:
|
|
Issue Dt:
|
06/01/2004
|
Application #:
|
09788925
|
Filing Dt:
|
02/20/2001
|
Publication #:
|
|
Pub Dt:
|
08/22/2002
| | | | |
Title:
|
METHOD FOR INSERTION OF TEST POINTS INTO INTEGRATED CIRCUIT LOGIC DESIGNS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/22/2003
|
Application #:
|
09789141
|
Filing Dt:
|
02/20/2001
|
Publication #:
|
|
Pub Dt:
|
08/22/2002
| | | | |
Title:
|
SEMICONDUCTOR DEVICE HAVING SIGNAL CONTACTS AND HIGH CURRENT POWER CONTACTS
|
|
|
Patent #:
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|
Issue Dt:
|
04/16/2002
|
Application #:
|
09789765
|
Filing Dt:
|
02/22/2001
|
Title:
|
HYDROGEN PASSIVATED SILICON NITRIDE SPACERS FOR REDUCED NICKEL SILICIDE BRIDGING
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|
|
Patent #:
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|
Issue Dt:
|
09/02/2003
|
Application #:
|
09789871
|
Filing Dt:
|
02/21/2001
|
Title:
|
METHOD AND APPARATUS FOR CONTROLLING A TOOL USING A BASELINE CONTROL SCRIPT
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|
|
Patent #:
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|
Issue Dt:
|
11/05/2002
|
Application #:
|
09789939
|
Filing Dt:
|
02/12/2001
|
Title:
|
FABRICATION OF A FIELD EFFECT TRANSISTOR WITH AN UPSIDE DOWN T-SHAPED SEMICONDUCTOR PILLAR IN SOI TECHNOLOGY
|
|
|
Patent #:
|
|
Issue Dt:
|
12/03/2002
|
Application #:
|
09790135
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Filing Dt:
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02/21/2001
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Title:
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PROCESS FOR OBSERVING OVERLAY ERRORS ON LITHOGRAPHIC MASKS
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Patent #:
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Issue Dt:
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06/22/2004
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Application #:
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09791003
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Filing Dt:
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02/22/2001
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Publication #:
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Pub Dt:
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08/22/2002
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Title:
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SYSTEM AND METHOD TO PREDETERMINE A BITMAP OF A SELF-TESTED EMBEDDED ARRAY
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Patent #:
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Issue Dt:
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09/03/2002
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Application #:
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09791024
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Filing Dt:
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02/21/2001
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Publication #:
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Pub Dt:
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08/22/2002
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Title:
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SELF-ALIGNED SILICIDE PROCESS FOR REDUCTION OF SI CONSUMPTION IN SHALLOW JUNCTION AND THIN SOI ELECTRONIC DEVICES
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Patent #:
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Issue Dt:
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08/31/2004
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Application #:
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09791981
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Filing Dt:
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02/23/2001
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Title:
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METHOD AND APPARATUS FOR ADAPTIVELY SCHEDULING TOOL MAINTENANCE
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Patent #:
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Issue Dt:
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04/30/2002
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Application #:
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09792139
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Filing Dt:
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02/22/2001
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Title:
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SOI CHIP HAVING MULTIPLE THRESHOLD VOLTAGE MOSFETS BY USING MULTIPLE CHANNEL MATERIALS AND METHOD OF FABRICATING SAME
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Patent #:
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Issue Dt:
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10/08/2002
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Application #:
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09792146
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Filing Dt:
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02/22/2001
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Title:
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SILICON-ON-INSULATOR (SOI) ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICE WITH BACKSIDE CONTACT OPENING
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Patent #:
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Issue Dt:
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04/23/2002
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Application #:
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09792766
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Filing Dt:
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02/23/2001
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Title:
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Method of forming low resistance gate electrode
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Patent #:
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Issue Dt:
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11/05/2002
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Application #:
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09793055
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Filing Dt:
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02/26/2001
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Title:
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METHOD OF FORMING A DOUBLE GATE TRANSISTOR HAVING AN EPITAXIAL SILICON/GERMANIUM CHANNEL REGION
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Patent #:
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Issue Dt:
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08/26/2003
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Application #:
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09794466
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Filing Dt:
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02/26/2001
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Publication #:
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Pub Dt:
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11/07/2002
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Title:
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FLUORINE-CONTAINING STYRENE ACRYLATE COPOLYMERS AND USE THEREOF IN LITHOGRAPHIC PHOTORESIST COMPOSITIONS
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Patent #:
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Issue Dt:
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06/25/2002
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Application #:
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09794884
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Filing Dt:
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02/26/2001
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Title:
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METHOD OF FABRICATION OF SEMICONDUCTOR-ON-INSULATOR (SOI) WAFER HAVING A SI/SIGE/SI ACTIVE LAYER
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Patent #:
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Issue Dt:
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09/03/2002
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Application #:
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09795159
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Filing Dt:
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02/28/2001
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Title:
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SILICON-ON-INSULATOR (SOI) TRANSISTOR HAVING PARTIAL HETERO SOURCE/DRAIN JUNCTIONS FABRICATED WITH HIGH ENERGY GERMANIUM IMPLANTATION
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Patent #:
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Issue Dt:
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01/13/2004
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Application #:
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09795429
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Filing Dt:
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02/28/2001
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Publication #:
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Pub Dt:
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08/29/2002
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Title:
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HYBRID LOW-K INTERCONNECT STRUCTURE COMPRISED OF 2 SPIN-ON DIELECTRIC MATERIALS
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Patent #:
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Issue Dt:
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03/23/2004
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Application #:
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09795430
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Filing Dt:
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02/28/2001
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Publication #:
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Pub Dt:
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08/29/2002
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Title:
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INTERCONNECT STRUCTURE WITH PRECISE CONDUCTOR RESISTANCE AND METHOD TO FORM SAME
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Patent #:
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Issue Dt:
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03/11/2003
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Application #:
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09795610
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Filing Dt:
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02/27/2001
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Publication #:
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Pub Dt:
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08/29/2002
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Title:
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INTRINSIC DUAL GATE OXIDE MOSFET USING A DAMASCENE GATE PROCESS
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Patent #:
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Issue Dt:
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09/17/2002
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Application #:
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09796389
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Filing Dt:
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02/28/2001
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Publication #:
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Pub Dt:
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08/02/2001
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Title:
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USE OF BLIND VIAS FOR SOLDERED INTERCONNECTIONS BETWEEN SUBSTRATES AND PRINTED WIRING BOARDS
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Patent #:
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Issue Dt:
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09/09/2003
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Application #:
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09796445
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Filing Dt:
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03/02/2001
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Publication #:
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Pub Dt:
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09/05/2002
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Title:
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FORMING A PATTERN OF A NEGATIVE PHOTORESIST
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Patent #:
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Issue Dt:
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01/28/2003
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Application #:
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09797078
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Filing Dt:
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03/01/2001
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Publication #:
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Pub Dt:
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09/05/2002
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Title:
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COUPLED-CAP FLIP CHIP BGA PACKAGE WITH IMPROVED CAP DESIGN FOR REDUCED INTERFACIAL STRESSES
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Patent #:
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Issue Dt:
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06/10/2003
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Application #:
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09798550
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Filing Dt:
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03/02/2001
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Publication #:
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Pub Dt:
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02/13/2003
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Title:
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ASYMMETRIC POWER SUPPLY INCLUDING A FAST RESPONSE CONVERTER
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Patent #:
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Issue Dt:
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06/03/2003
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Application #:
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09800166
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Filing Dt:
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03/06/2001
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Title:
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USE OF THERMAL FLOW TO REMOVE SIDE LOBES
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Patent #:
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Issue Dt:
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08/05/2003
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Application #:
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09802437
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Filing Dt:
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03/09/2001
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Title:
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SILYLATION PROCESS FOR FORMING CONTACTS
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Patent #:
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Issue Dt:
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02/04/2003
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Application #:
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09803831
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Filing Dt:
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03/12/2001
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Title:
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METHOD OF FABRICATING ABRUPT SOURCE/DRAIN JUNCTIONS
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Patent #:
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Issue Dt:
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11/11/2003
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Application #:
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09803853
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Filing Dt:
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03/12/2001
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Title:
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ATTENUATED PHASE SHIFT MASK FOR USE IN EUV LITHOGRAPHY AND A METHOD OF MAKING SUCH A MASK
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Patent #:
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Issue Dt:
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08/06/2002
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Application #:
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09804535
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Filing Dt:
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03/12/2001
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Title:
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STRUCTURE AND METHOD FOR FORMING THE SAME OF A PRINTED WIRING BOARD HAVING BUILT-IN INSPECTION AIDS
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Patent #:
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Issue Dt:
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04/30/2002
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Application #:
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09804768
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Filing Dt:
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03/13/2001
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Publication #:
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Pub Dt:
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01/17/2002
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Title:
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LINE-ORIENTED REORDER BUFFER CONFIGURED TO SELECTIVELY STORE A MEMORY OPERATION RESULT IN ONE OF THE PLURALITY OF REORDER BUFFER STORAGE LOCATIONS CORRESPONDING TO THE EXECUTED INSTRUCTION
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Patent #:
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Issue Dt:
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08/08/2006
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Application #:
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09805027
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Filing Dt:
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03/12/2001
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Publication #:
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Pub Dt:
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09/12/2002
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Title:
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COPPER TO ALUMINUM INTERLAYER INTERCONNECT USING STUD AND VIA LINER
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Patent #:
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Issue Dt:
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08/13/2002
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Application #:
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09805420
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Filing Dt:
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03/13/2001
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Title:
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CLOCKED MEMORY DEVICE THAT INCLUDES A PROGRAMMING MECHANISM FOR SETTING WRITE RECOVERY TIME AS A FUNCTION OF THE INPUT CLOCK
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Patent #:
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Issue Dt:
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06/11/2002
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Application #:
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09805651
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Filing Dt:
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03/13/2001
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Title:
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POST-CMP-CU DEPOSITION AND CMP TO ELIMINATE SURFACE VOIDS
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Patent #:
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Issue Dt:
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12/10/2002
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Application #:
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09808381
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Filing Dt:
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03/14/2001
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Publication #:
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Pub Dt:
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09/19/2002
| | | | |
Title:
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INTEGRATED COIL INDUCTORS FOR IC DEVICES
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Patent #:
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Issue Dt:
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02/03/2004
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Application #:
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09808724
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Filing Dt:
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03/14/2001
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Publication #:
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Pub Dt:
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09/19/2002
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Title:
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DEFECT-FREE DIELECTRIC COATINGS AND PREPARATION THEREOF USING POLYMERIC NITROGENOUS POROGENS
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Patent #:
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Issue Dt:
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12/30/2003
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Application #:
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09808726
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Filing Dt:
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03/14/2001
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Publication #:
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Pub Dt:
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09/19/2002
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Title:
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NITROGEN-CONTAINING POLYMERS AS POROGENS IN THE PREPARATION OF HIGHLY POROUS, LOW DIELECTRIC CONSTANT MATERIALS
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Patent #:
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Issue Dt:
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06/01/2004
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Application #:
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09808896
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Filing Dt:
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03/15/2001
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Publication #:
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Pub Dt:
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08/30/2001
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Title:
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NON-UNIFORM GATE/DIELECTRIC FIELD EFFECT TRANSISTOR
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Patent #:
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Issue Dt:
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10/12/2004
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Application #:
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09809016
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Filing Dt:
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03/16/2001
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Title:
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EXTERNAL CPU ASSIST WHEN PERFORMING A NETWORK ADDRESS LOOKUP
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Patent #:
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Issue Dt:
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08/13/2002
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Application #:
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09809133
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Filing Dt:
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03/15/2001
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Title:
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FIELD EFFECT TRANSISTOR HAVING DOPED GATE WITH PREVENTION OF CONTAMINATION FROM THE GATE DURING IMPLANTATION
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Patent #:
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Issue Dt:
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08/26/2003
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Application #:
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09809300
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Filing Dt:
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03/16/2001
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Title:
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PLASMA ETCHING USING COMBINATION OF CHF3 AND CH3F
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Patent #:
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Issue Dt:
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07/15/2003
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Application #:
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09809710
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Filing Dt:
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03/14/2001
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Publication #:
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Pub Dt:
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04/25/2002
| | | | |
Title:
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METHOD OF CONTROLLING A SHAPE OF AN OXIDE LAYER FORMED ON A SUBSTRATE
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