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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:049490/0001   Pages: 892
Recorded: 11/29/2018
Conveyance: SECURITY AGREEMENT
1
Patent #:
Issue Dt:
04/15/2003
Application #:
09771262
Filing Dt:
01/26/2001
Publication #:
Pub Dt:
08/01/2002
Title:
SUBSTITUTED NORBORNENE FLUOROACRYLATE COPOLYMERS AND USE THEREOF IN LITHOGRAPHIC PHOTORESIST COMPOSITIONS
2
Patent #:
Issue Dt:
07/08/2003
Application #:
09771820
Filing Dt:
01/29/2001
Title:
PROCESS FOR REDUCING THE PITCH OF CONTACT HOLES, VIAS, AND TRENCH STRUCTURES IN INTEGRATED CIRCUITS
3
Patent #:
Issue Dt:
12/31/2002
Application #:
09772205
Filing Dt:
01/29/2001
Publication #:
Pub Dt:
10/10/2002
Title:
METHOD OF FORMING RECESSED THIN FILM LANDING PAD STRUCTURE
4
Patent #:
Issue Dt:
06/17/2003
Application #:
09772345
Filing Dt:
01/30/2001
Publication #:
Pub Dt:
08/01/2002
Title:
METHOD FOR DELINEATION OF EDRAM SUPPORT DEVICE NOTCHED GATE
5
Patent #:
Issue Dt:
03/18/2003
Application #:
09772577
Filing Dt:
01/30/2001
Publication #:
Pub Dt:
08/01/2002
Title:
PHASE SHIFT MASK AND SYSTEM AND METHOD FOR MAKING THE SAME
6
Patent #:
Issue Dt:
05/20/2003
Application #:
09772610
Filing Dt:
01/30/2001
Title:
SEMICONDUCTOR-ON-INSULATOR (SOI) TUNNELING JUNCTION TRANSISTOR
7
Patent #:
Issue Dt:
09/03/2002
Application #:
09772649
Filing Dt:
01/30/2001
Title:
SOI SEMICONDUCTOR DEVICE OPENING IMPLANTATION GETTERING METHOD
8
Patent #:
Issue Dt:
03/25/2003
Application #:
09772889
Filing Dt:
01/31/2001
Title:
PACKAGING SUBSTRATE COMPRISING STAGGERED VIAS
9
Patent #:
Issue Dt:
01/21/2003
Application #:
09773323
Filing Dt:
01/31/2001
Publication #:
Pub Dt:
08/01/2002
Title:
METHOD FOR WRITING AND/OR ERASING HIGH DENSITY DATA ON A MEDIA
10
Patent #:
Issue Dt:
10/22/2002
Application #:
09773488
Filing Dt:
02/02/2001
Publication #:
Pub Dt:
10/04/2001
Title:
COMPOSITION FOR INCREASING ACTIVITY OF A NO-CLEAN FLUX
11
Patent #:
Issue Dt:
05/08/2007
Application #:
09773798
Filing Dt:
02/01/2001
Publication #:
Pub Dt:
08/01/2002
Title:
PASSIVATION FOR IMPROVED BIPOLAR YIELD
12
Patent #:
Issue Dt:
07/29/2003
Application #:
09773906
Filing Dt:
02/02/2001
Title:
PLASMA ETCH PROCESS FOR NONHOMOGENOUS FILM
13
Patent #:
Issue Dt:
12/31/2002
Application #:
09773954
Filing Dt:
02/01/2001
Title:
OPTICAL TECHNIQUE TO DETECT ETCH PROCESS TERMINATION
14
Patent #:
Issue Dt:
07/30/2002
Application #:
09774126
Filing Dt:
01/30/2001
Publication #:
Pub Dt:
08/01/2002
Title:
INCORPORATION OF CARBON IN SILICON/SILICON GERMANIUM EPITAXIAL LAYER TO ENHANCE YIELD FOR SI-GE BIPOLAR TECHNOLOGY
15
Patent #:
Issue Dt:
04/30/2002
Application #:
09774138
Filing Dt:
01/30/2001
Title:
SEMICONDUCTOR-ON-INSULATOR (SOI) TUNNELING JUNCTION TRANSISTOR SRAM CELL
16
Patent #:
Issue Dt:
12/31/2002
Application #:
09774152
Filing Dt:
01/30/2001
Publication #:
Pub Dt:
08/01/2002
Title:
FLIP CHIP PACKAGE WITH IMPROVED CAP DESIGN AND PROCESS FOR MAKING THEREOF
17
Patent #:
Issue Dt:
05/18/2004
Application #:
09774489
Filing Dt:
01/31/2001
Publication #:
Pub Dt:
09/26/2002
Title:
HEAD-MOUNTED DISPLAY CONTENT TRANSFORMER
18
Patent #:
Issue Dt:
11/05/2002
Application #:
09774708
Filing Dt:
02/01/2001
Title:
METHOD OF MANUFACTURING A SEMICONDUCTOR STRUCTURE WITH TREATMENT TO SACRIFICIAL STOP LAYER PRODUCING DIFFUSION TO AN ADJACENT LOW-K DIELECTRIC LAYER LOWERING THE CONSTANT
19
Patent #:
Issue Dt:
04/02/2002
Application #:
09774939
Filing Dt:
01/31/2001
Title:
Dual gate process using self-assembled molecular layer
20
Patent #:
Issue Dt:
07/19/2005
Application #:
09774943
Filing Dt:
01/31/2001
Publication #:
Pub Dt:
08/01/2002
Title:
ASSEMBLY FOR WRITING AND / OR ERASING HIGH DENSITY DATA ON A MEDIA
21
Patent #:
Issue Dt:
07/19/2005
Application #:
09775374
Filing Dt:
02/01/2001
Publication #:
Pub Dt:
08/01/2002
Title:
SYSTEM AND METHOD FOR REMOTE OPTICAL DIGITAL NETWORKING OF COMPUTING DEVICES
22
Patent #:
Issue Dt:
05/18/2004
Application #:
09776077
Filing Dt:
02/01/2001
Title:
EFFICIENT SIMD QUANTIZATION METHOD
23
Patent #:
Issue Dt:
03/02/2004
Application #:
09776339
Filing Dt:
02/02/2001
Title:
PCI AND MII COMPATIBLE HOME PHONELINE NETWORKING ALLIANCE (HPNA) INTERFACE DEVICE
24
Patent #:
Issue Dt:
04/16/2002
Application #:
09776736
Filing Dt:
02/06/2001
Title:
METHOD FOR MAKING A SLOT VIA FILLED DUAL DAMASCENE LOW K INTERCONNECT STRUCTURE WITHOUT MIDDLE STOP LAYER
25
Patent #:
Issue Dt:
02/25/2003
Application #:
09776748
Filing Dt:
02/06/2001
Title:
NICKEL SILICIDE PROCESS USING STARVED SILICON DIFFUSION BARRIER
26
Patent #:
Issue Dt:
11/12/2002
Application #:
09777539
Filing Dt:
02/06/2001
Publication #:
Pub Dt:
06/28/2001
Title:
MULTI-WAFER POLISHING TOOL
27
Patent #:
Issue Dt:
06/17/2003
Application #:
09777548
Filing Dt:
02/06/2001
Publication #:
Pub Dt:
08/08/2002
Title:
SUPPORT AND ALIGNMENT DEVICE FOR ENABLING CHEMICAL MECHANICAL POLISHING RINSE AND FILM MEASUREMENTS
28
Patent #:
Issue Dt:
12/17/2002
Application #:
09777637
Filing Dt:
02/06/2001
Title:
SEMICONDUCTOR-ON-INSULATOR (SOI) DEVICE HAVING SOURCE/DRAIN SILICON-GERMANIUM REGIONS AND METHOD OF MANUFACTURE
29
Patent #:
Issue Dt:
12/02/2003
Application #:
09777695
Filing Dt:
02/07/2001
Title:
DUAL DAMASCENE WITH SILICON CARBIDE MIDDLE ETCH STOP LAYER/ARC
30
Patent #:
Issue Dt:
10/15/2002
Application #:
09778109
Filing Dt:
02/07/2001
Title:
SILICON CARBIDE BARC IN DUAL DAMASCENE PROCESSING
31
Patent #:
Issue Dt:
02/03/2004
Application #:
09778335
Filing Dt:
02/07/2001
Publication #:
Pub Dt:
08/08/2002
Title:
DAMASCENE DOUBLE-GATE MOSFET STRUCTURE AND ITS FABRICATION METHOD
32
Patent #:
Issue Dt:
05/28/2002
Application #:
09778352
Filing Dt:
02/06/2001
Publication #:
Pub Dt:
12/13/2001
Title:
FLOATING POINT ADDITION PIPELINE INCLUDING EXTREME VALUE, COMPARISON AND ACCUMULATE FUNCTIONS
33
Patent #:
Issue Dt:
06/17/2003
Application #:
09778529
Filing Dt:
02/07/2001
Title:
ACCURATE CONTACT CRITICAL DIMENSION MEASUREMENT USING VARIABLE THRESHOLD METHOD
34
Patent #:
Issue Dt:
06/10/2003
Application #:
09778586
Filing Dt:
02/07/2001
Title:
TRI-TONE MASK PROCESS FOR DENSE AND ISOLATED PATTERNS
35
Patent #:
Issue Dt:
06/24/2003
Application #:
09778777
Filing Dt:
02/08/2001
Title:
SEMICONDUCTOR DEVICE HAVING A LOW DIELECTRIC CONSTANT MATERIAL
36
Patent #:
Issue Dt:
04/22/2003
Application #:
09779986
Filing Dt:
02/09/2001
Title:
LOW TEMPERATURE PROCESS FOR A THIN FILM TRANSISTOR
37
Patent #:
Issue Dt:
06/11/2002
Application #:
09779987
Filing Dt:
02/09/2001
Title:
PROCESS FOR MANUFACTURING MOS TRANSISTORS HAVING ELEVATED SOURCE AND DRAIN REGIONS AND A HIGH-K GATE DIELECTRIC
38
Patent #:
Issue Dt:
01/06/2004
Application #:
09780275
Filing Dt:
02/09/2001
Publication #:
Pub Dt:
10/10/2002
Title:
ATTENUATING EXTREME ULTRAVIOLET (EUV) PHASE-SHIFTING MASK FABRICATION METHOD
39
Patent #:
Issue Dt:
10/01/2002
Application #:
09780454
Filing Dt:
02/12/2001
Title:
METHOD OF MAKING A SILICIDE STOP LAYER IN A DAMASCENE SEMICONDUCTOR STRUCTURE
40
Patent #:
Issue Dt:
09/21/2004
Application #:
09780558
Filing Dt:
02/09/2001
Publication #:
Pub Dt:
08/15/2002
Title:
METHOD AND SYSTEM FOR FAULT-TOLERANT STATIC TIMING ANALYSIS
41
Patent #:
Issue Dt:
03/18/2003
Application #:
09781014
Filing Dt:
02/10/2001
Publication #:
Pub Dt:
08/15/2002
Title:
HIGH Q INDUCTOR WITH FARADAY SHIELD AND DIELECTRIC WELL BURIED IN SUBSTRATE
42
Patent #:
Issue Dt:
12/17/2002
Application #:
09781039
Filing Dt:
02/09/2001
Title:
LOW TEMPERATURE PROCESS TO LOCALLY FORM HIGH-K GATE DIELECTRICS
43
Patent #:
Issue Dt:
03/18/2003
Application #:
09781121
Filing Dt:
02/09/2001
Publication #:
Pub Dt:
08/15/2002
Title:
COMMON BALL-LIMITING METALLURGY FOR I/O SITES
44
Patent #:
Issue Dt:
04/30/2002
Application #:
09781225
Filing Dt:
02/13/2001
Title:
ENHANCEMENT OF NICKEL SILICIDE FORMATION BY USE OF NICKEL PRE-AMORPHIZING IMPLANT
45
Patent #:
Issue Dt:
04/16/2002
Application #:
09781256
Filing Dt:
02/13/2001
Title:
SILICON-STARVED NITRIDE SPACER DEPOSITION
46
Patent #:
Issue Dt:
04/30/2002
Application #:
09781357
Filing Dt:
02/12/2001
Title:
LOW TEMPERATURE PROCESS TO FORM ELEVATED DRAIN AND SOURCE OF A FIELD EFFECT TRANSISTOR HAVING HIGH-K GATE DIELECTRIC
47
Patent #:
Issue Dt:
06/18/2002
Application #:
09781364
Filing Dt:
02/12/2001
Title:
FABRICATION OF FULLY DEPLETED FIELD EFFECT TRANSISTOR WITH RAISED SOURCE AND DRAIN IN SOI TECHNOLOGY
48
Patent #:
Issue Dt:
03/18/2003
Application #:
09781637
Filing Dt:
02/12/2001
Publication #:
Pub Dt:
06/28/2001
Title:
SEMICONDUCTOR DEVICE HAVING A THERMOSET-CONTAINING DIELECTRIC MATERIAL AND METHODS FOR FABRICATING THE SAME
49
Patent #:
Issue Dt:
05/28/2002
Application #:
09781783
Filing Dt:
02/12/2001
Title:
FABRICATION OF FULLY DEPLETED FIELD EFFECT TRANSISTOR WITH HIGH-K GATE DIELECTRIC IN SOI TECHNOLOGY
50
Patent #:
Issue Dt:
11/04/2003
Application #:
09783204
Filing Dt:
02/15/2001
Title:
METHOD AND APPARATUS FOR DETERMINING AN ETCH ENDPOINT
51
Patent #:
Issue Dt:
04/27/2004
Application #:
09784790
Filing Dt:
02/15/2001
Title:
CHANNEL ISOLATION USING DIELECTRIC ISOLATION STRUCTURES
52
Patent #:
Issue Dt:
04/09/2002
Application #:
09784842
Filing Dt:
02/15/2001
Title:
METHOD FOR LOW STRESS PLATING OF SEMICONDUCTOR VIAS AND CHANNELS
53
Patent #:
Issue Dt:
08/27/2002
Application #:
09785176
Filing Dt:
02/20/2001
Title:
NISI CONTACTING EXTENSIONS OF ACTIVE REGIONS
54
Patent #:
Issue Dt:
12/24/2002
Application #:
09785432
Filing Dt:
02/16/2001
Publication #:
Pub Dt:
08/22/2002
Title:
CONDUCTIVE COUPLING OF ELECTRICAL STRUCTURES TO A SEMICONDUCTOR DEVICE LOCATED UNDER A BURIED OXIDE LAYER
55
Patent #:
Issue Dt:
10/15/2002
Application #:
09785444
Filing Dt:
02/20/2001
Title:
METHOD FOR PREVENTING DAMAGE OF LOW-K DIELECTRICS DURING PATTERNING
56
Patent #:
Issue Dt:
11/25/2003
Application #:
09785609
Filing Dt:
02/16/2001
Publication #:
Pub Dt:
08/22/2002
Title:
RADIATION SENSITIVE SILICON-CONTAINING NEGATIVE RESISTS AND USE THEREOF
57
Patent #:
Issue Dt:
05/28/2002
Application #:
09788027
Filing Dt:
02/16/2001
Title:
METHOD AND CIRCUIT FOR PRELOADING PREDICTION CIRCUITS IN MICROPROCESSORS
58
Patent #:
Issue Dt:
05/21/2002
Application #:
09788067
Filing Dt:
02/16/2001
Title:
PHYSICAL RENAME REGISTER FOR EFFICIENTLY STORING FLOATING POINT, INTEGER, CONDITION CODE, AND MULTIMEDIA VALUES
59
Patent #:
Issue Dt:
09/30/2003
Application #:
09788631
Filing Dt:
02/16/2001
Publication #:
Pub Dt:
06/28/2001
Title:
METHOD OF DESIGNING AND STRUCTURE FOR VISUAL AND ELECTRICAL TEST OF SEMICONDUCTOR DEVICES
60
Patent #:
Issue Dt:
04/27/2004
Application #:
09788635
Filing Dt:
02/21/2001
Publication #:
Pub Dt:
10/10/2002
Title:
GUI FOR REPRESENTING ENTITY MATCHES UTILIZING GRAPHICAL TRANSITIONS PERFORMED DIRECTLY ON THE MATCHING OBJECT
61
Patent #:
Issue Dt:
06/01/2004
Application #:
09788925
Filing Dt:
02/20/2001
Publication #:
Pub Dt:
08/22/2002
Title:
METHOD FOR INSERTION OF TEST POINTS INTO INTEGRATED CIRCUIT LOGIC DESIGNS
62
Patent #:
Issue Dt:
04/22/2003
Application #:
09789141
Filing Dt:
02/20/2001
Publication #:
Pub Dt:
08/22/2002
Title:
SEMICONDUCTOR DEVICE HAVING SIGNAL CONTACTS AND HIGH CURRENT POWER CONTACTS
63
Patent #:
Issue Dt:
04/16/2002
Application #:
09789765
Filing Dt:
02/22/2001
Title:
HYDROGEN PASSIVATED SILICON NITRIDE SPACERS FOR REDUCED NICKEL SILICIDE BRIDGING
64
Patent #:
Issue Dt:
09/02/2003
Application #:
09789871
Filing Dt:
02/21/2001
Title:
METHOD AND APPARATUS FOR CONTROLLING A TOOL USING A BASELINE CONTROL SCRIPT
65
Patent #:
Issue Dt:
11/05/2002
Application #:
09789939
Filing Dt:
02/12/2001
Title:
FABRICATION OF A FIELD EFFECT TRANSISTOR WITH AN UPSIDE DOWN T-SHAPED SEMICONDUCTOR PILLAR IN SOI TECHNOLOGY
66
Patent #:
Issue Dt:
12/03/2002
Application #:
09790135
Filing Dt:
02/21/2001
Title:
PROCESS FOR OBSERVING OVERLAY ERRORS ON LITHOGRAPHIC MASKS
67
Patent #:
Issue Dt:
06/22/2004
Application #:
09791003
Filing Dt:
02/22/2001
Publication #:
Pub Dt:
08/22/2002
Title:
SYSTEM AND METHOD TO PREDETERMINE A BITMAP OF A SELF-TESTED EMBEDDED ARRAY
68
Patent #:
Issue Dt:
09/03/2002
Application #:
09791024
Filing Dt:
02/21/2001
Publication #:
Pub Dt:
08/22/2002
Title:
SELF-ALIGNED SILICIDE PROCESS FOR REDUCTION OF SI CONSUMPTION IN SHALLOW JUNCTION AND THIN SOI ELECTRONIC DEVICES
69
Patent #:
Issue Dt:
08/31/2004
Application #:
09791981
Filing Dt:
02/23/2001
Title:
METHOD AND APPARATUS FOR ADAPTIVELY SCHEDULING TOOL MAINTENANCE
70
Patent #:
Issue Dt:
04/30/2002
Application #:
09792139
Filing Dt:
02/22/2001
Title:
SOI CHIP HAVING MULTIPLE THRESHOLD VOLTAGE MOSFETS BY USING MULTIPLE CHANNEL MATERIALS AND METHOD OF FABRICATING SAME
71
Patent #:
Issue Dt:
10/08/2002
Application #:
09792146
Filing Dt:
02/22/2001
Title:
SILICON-ON-INSULATOR (SOI) ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICE WITH BACKSIDE CONTACT OPENING
72
Patent #:
Issue Dt:
04/23/2002
Application #:
09792766
Filing Dt:
02/23/2001
Title:
Method of forming low resistance gate electrode
73
Patent #:
Issue Dt:
11/05/2002
Application #:
09793055
Filing Dt:
02/26/2001
Title:
METHOD OF FORMING A DOUBLE GATE TRANSISTOR HAVING AN EPITAXIAL SILICON/GERMANIUM CHANNEL REGION
74
Patent #:
Issue Dt:
08/26/2003
Application #:
09794466
Filing Dt:
02/26/2001
Publication #:
Pub Dt:
11/07/2002
Title:
FLUORINE-CONTAINING STYRENE ACRYLATE COPOLYMERS AND USE THEREOF IN LITHOGRAPHIC PHOTORESIST COMPOSITIONS
75
Patent #:
Issue Dt:
06/25/2002
Application #:
09794884
Filing Dt:
02/26/2001
Title:
METHOD OF FABRICATION OF SEMICONDUCTOR-ON-INSULATOR (SOI) WAFER HAVING A SI/SIGE/SI ACTIVE LAYER
76
Patent #:
Issue Dt:
09/03/2002
Application #:
09795159
Filing Dt:
02/28/2001
Title:
SILICON-ON-INSULATOR (SOI) TRANSISTOR HAVING PARTIAL HETERO SOURCE/DRAIN JUNCTIONS FABRICATED WITH HIGH ENERGY GERMANIUM IMPLANTATION
77
Patent #:
Issue Dt:
01/13/2004
Application #:
09795429
Filing Dt:
02/28/2001
Publication #:
Pub Dt:
08/29/2002
Title:
HYBRID LOW-K INTERCONNECT STRUCTURE COMPRISED OF 2 SPIN-ON DIELECTRIC MATERIALS
78
Patent #:
Issue Dt:
03/23/2004
Application #:
09795430
Filing Dt:
02/28/2001
Publication #:
Pub Dt:
08/29/2002
Title:
INTERCONNECT STRUCTURE WITH PRECISE CONDUCTOR RESISTANCE AND METHOD TO FORM SAME
79
Patent #:
Issue Dt:
03/11/2003
Application #:
09795610
Filing Dt:
02/27/2001
Publication #:
Pub Dt:
08/29/2002
Title:
INTRINSIC DUAL GATE OXIDE MOSFET USING A DAMASCENE GATE PROCESS
80
Patent #:
Issue Dt:
09/17/2002
Application #:
09796389
Filing Dt:
02/28/2001
Publication #:
Pub Dt:
08/02/2001
Title:
USE OF BLIND VIAS FOR SOLDERED INTERCONNECTIONS BETWEEN SUBSTRATES AND PRINTED WIRING BOARDS
81
Patent #:
Issue Dt:
09/09/2003
Application #:
09796445
Filing Dt:
03/02/2001
Publication #:
Pub Dt:
09/05/2002
Title:
FORMING A PATTERN OF A NEGATIVE PHOTORESIST
82
Patent #:
Issue Dt:
01/28/2003
Application #:
09797078
Filing Dt:
03/01/2001
Publication #:
Pub Dt:
09/05/2002
Title:
COUPLED-CAP FLIP CHIP BGA PACKAGE WITH IMPROVED CAP DESIGN FOR REDUCED INTERFACIAL STRESSES
83
Patent #:
Issue Dt:
06/10/2003
Application #:
09798550
Filing Dt:
03/02/2001
Publication #:
Pub Dt:
02/13/2003
Title:
ASYMMETRIC POWER SUPPLY INCLUDING A FAST RESPONSE CONVERTER
84
Patent #:
Issue Dt:
06/03/2003
Application #:
09800166
Filing Dt:
03/06/2001
Title:
USE OF THERMAL FLOW TO REMOVE SIDE LOBES
85
Patent #:
Issue Dt:
08/05/2003
Application #:
09802437
Filing Dt:
03/09/2001
Title:
SILYLATION PROCESS FOR FORMING CONTACTS
86
Patent #:
Issue Dt:
02/04/2003
Application #:
09803831
Filing Dt:
03/12/2001
Title:
METHOD OF FABRICATING ABRUPT SOURCE/DRAIN JUNCTIONS
87
Patent #:
Issue Dt:
11/11/2003
Application #:
09803853
Filing Dt:
03/12/2001
Title:
ATTENUATED PHASE SHIFT MASK FOR USE IN EUV LITHOGRAPHY AND A METHOD OF MAKING SUCH A MASK
88
Patent #:
Issue Dt:
08/06/2002
Application #:
09804535
Filing Dt:
03/12/2001
Title:
STRUCTURE AND METHOD FOR FORMING THE SAME OF A PRINTED WIRING BOARD HAVING BUILT-IN INSPECTION AIDS
89
Patent #:
Issue Dt:
04/30/2002
Application #:
09804768
Filing Dt:
03/13/2001
Publication #:
Pub Dt:
01/17/2002
Title:
LINE-ORIENTED REORDER BUFFER CONFIGURED TO SELECTIVELY STORE A MEMORY OPERATION RESULT IN ONE OF THE PLURALITY OF REORDER BUFFER STORAGE LOCATIONS CORRESPONDING TO THE EXECUTED INSTRUCTION
90
Patent #:
Issue Dt:
08/08/2006
Application #:
09805027
Filing Dt:
03/12/2001
Publication #:
Pub Dt:
09/12/2002
Title:
COPPER TO ALUMINUM INTERLAYER INTERCONNECT USING STUD AND VIA LINER
91
Patent #:
Issue Dt:
08/13/2002
Application #:
09805420
Filing Dt:
03/13/2001
Title:
CLOCKED MEMORY DEVICE THAT INCLUDES A PROGRAMMING MECHANISM FOR SETTING WRITE RECOVERY TIME AS A FUNCTION OF THE INPUT CLOCK
92
Patent #:
Issue Dt:
06/11/2002
Application #:
09805651
Filing Dt:
03/13/2001
Title:
POST-CMP-CU DEPOSITION AND CMP TO ELIMINATE SURFACE VOIDS
93
Patent #:
Issue Dt:
12/10/2002
Application #:
09808381
Filing Dt:
03/14/2001
Publication #:
Pub Dt:
09/19/2002
Title:
INTEGRATED COIL INDUCTORS FOR IC DEVICES
94
Patent #:
Issue Dt:
02/03/2004
Application #:
09808724
Filing Dt:
03/14/2001
Publication #:
Pub Dt:
09/19/2002
Title:
DEFECT-FREE DIELECTRIC COATINGS AND PREPARATION THEREOF USING POLYMERIC NITROGENOUS POROGENS
95
Patent #:
Issue Dt:
12/30/2003
Application #:
09808726
Filing Dt:
03/14/2001
Publication #:
Pub Dt:
09/19/2002
Title:
NITROGEN-CONTAINING POLYMERS AS POROGENS IN THE PREPARATION OF HIGHLY POROUS, LOW DIELECTRIC CONSTANT MATERIALS
96
Patent #:
Issue Dt:
06/01/2004
Application #:
09808896
Filing Dt:
03/15/2001
Publication #:
Pub Dt:
08/30/2001
Title:
NON-UNIFORM GATE/DIELECTRIC FIELD EFFECT TRANSISTOR
97
Patent #:
Issue Dt:
10/12/2004
Application #:
09809016
Filing Dt:
03/16/2001
Title:
EXTERNAL CPU ASSIST WHEN PERFORMING A NETWORK ADDRESS LOOKUP
98
Patent #:
Issue Dt:
08/13/2002
Application #:
09809133
Filing Dt:
03/15/2001
Title:
FIELD EFFECT TRANSISTOR HAVING DOPED GATE WITH PREVENTION OF CONTAMINATION FROM THE GATE DURING IMPLANTATION
99
Patent #:
Issue Dt:
08/26/2003
Application #:
09809300
Filing Dt:
03/16/2001
Title:
PLASMA ETCHING USING COMBINATION OF CHF3 AND CH3F
100
Patent #:
Issue Dt:
07/15/2003
Application #:
09809710
Filing Dt:
03/14/2001
Publication #:
Pub Dt:
04/25/2002
Title:
METHOD OF CONTROLLING A SHAPE OF AN OXIDE LAYER FORMED ON A SUBSTRATE
Assignor
1
Exec Dt:
11/27/2018
Assignee
1
1100 NORTH MARKET STREET
WILMINGTON, DELAWARE 19801
Correspondence name and address
CT CORPORATION
4400 EASTON COMMONS WAY
SUITE 125
COLUMBUS, OH 43219

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