USPTO Assignments on the Web

	United States Patent and Trademark Office
	Home\|Site Index\|Search\|Guides\|Contacts\|eBusiness\|eBiz alerts\|News\|Help

Assignments on the Web > Patent Query

Patent Assignment Details

NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:	049490/0001			Pages:	892
		Recorded:	11/29/2018
Conveyance:	SECURITY AGREEMENT

Total properties: 13706
Page 131 of 138
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138

Patent #:	9754843	Issue Dt:	09/05/2017	Application #:	15205535	Filing Dt:	07/08/2016
Title:	HETEROGENEOUS INTEGRATION OF 3D SI AND III-V VERTICAL NANOWIRE STRUCTURES FOR MIXED SIGNAL CIRCUITS FABRICATION

Patent #:	10128187	Issue Dt:	11/13/2018	Application #:	15206361	Filing Dt:	07/11/2016
Publication #:	US20180012839	Pub Dt:	01/11/2018
Title:	INTEGRATED CIRCUIT STRUCTURE HAVING GATE CONTACT AND METHOD OF FORMING SAME

Patent #:	9966292	Issue Dt:	05/08/2018	Application #:	15207524	Filing Dt:	07/12/2016
Publication #:	US20180019147	Pub Dt:	01/18/2018
Title:	CENTERING FIXTURE FOR ELECTROSTATIC CHUCK SYSTEM

Patent #:	9852984	Issue Dt:	12/26/2017	Application #:	15207652	Filing Dt:	07/12/2016
Publication #:	US20160322298	Pub Dt:	11/03/2016
Title:	CUT FIRST ALTERNATIVE FOR 2D SELF-ALIGNED VIA

Patent #:	9646969	Issue Dt:	05/09/2017	Application #:	15208121	Filing Dt:	07/12/2016
Publication #:	US20160365450	Pub Dt:	12/15/2016
Title:	SPACER CHAMFERING GATE STACK SCHEME

Patent #:	9911740	Issue Dt:	03/06/2018	Application #:	15208495	Filing Dt:	07/12/2016
Publication #:	US20180019241	Pub Dt:	01/18/2018
Title:	METHOD, APPARATUS, AND SYSTEM HAVING SUPER STEEP RETROGRADE WELL WITH ENGINEERED DOPANT PROFILES

Patent #:	NONE	Issue Dt:		Application #:	15208852	Filing Dt:	07/13/2016
Publication #:	US20180019162	Pub Dt:	01/18/2018
Title:	AMORPHOUS CARBON LAYER FOR COBALT ETCH PROTECTION IN DUAL DAMASCENE BACK END OF THE LINE INTEGRATED CIRCUIT METALLIZATION INTEGRATION

Patent #:	9871020	Issue Dt:	01/16/2018	Application #:	15210403	Filing Dt:	07/14/2016
Publication #:	US20180019227	Pub Dt:	01/18/2018
Title:	THROUGH SILICON VIA SHARING IN A 3D INTEGRATED CIRCUIT

Patent #:	9780208	Issue Dt:	10/03/2017	Application #:	15212755	Filing Dt:	07/18/2016
Title:	METHOD AND STRUCTURE OF FORMING SELF-ALIGNED RMG GATE FOR VFET

Patent #:	10348243	Issue Dt:	07/09/2019	Application #:	15213529	Filing Dt:	07/19/2016
Publication #:	US20180026580	Pub Dt:	01/25/2018
Title:	SWITCHED CAPACITOR CIRCUIT STRUCTURE WITH METHOD OF CONTROLLING SOURCE-DRAIN RESISTANCE ACROSS SAME

Patent #:	10109046	Issue Dt:	10/23/2018	Application #:	15213665	Filing Dt:	07/19/2016
Publication #:	US20180025483	Pub Dt:	01/25/2018
Title:	METHODS OF DETECTING FAULTS IN REAL-TIME FOR SEMICONDUCTOR WAFERS

Patent #:	10504774	Issue Dt:	12/10/2019	Application #:	15214585	Filing Dt:	07/20/2016
Publication #:	US20180025936	Pub Dt:	01/25/2018
Title:	LITHOGRAPHIC PATTERNING TO FORM FINE PITCH FEATURES

Patent #:	9680019	Issue Dt:	06/13/2017	Application #:	15214854	Filing Dt:	07/20/2016
Title:	FIN-TYPE FIELD-EFFECT TRANSISTORS WITH STRAINED CHANNELS

Patent #:	9653454	Issue Dt:	05/16/2017	Application #:	15215043	Filing Dt:	07/20/2016
Title:	METHODS FOR AN ESD PROTECTION CIRCUIT INCLUDING TRIGGER-VOLTAGE TUNABLE CASCODE TRANSISTORS

Patent #:	9799693	Issue Dt:	10/24/2017	Application #:	15215674	Filing Dt:	07/21/2016
Publication #:	US20160343759	Pub Dt:	11/24/2016
Title:	PHOTODETECTOR AND METHOD OF FORMING THE PHOTODETECTOR ON STACKED TRENCH ISOLATION REGIONS

Patent #:	10056453	Issue Dt:	08/21/2018	Application #:	15217643	Filing Dt:	07/22/2016
Publication #:	US20180026096	Pub Dt:	01/25/2018
Title:	SEMICONDUCTOR WAFERS WITH REDUCED BOW AND WARPAGE

Patent #:	10186439	Issue Dt:	01/22/2019	Application #:	15218241	Filing Dt:	07/25/2016
Publication #:	US20180025929	Pub Dt:	01/25/2018
Title:	SYSTEMS AND METHODS FOR SENSING PROCESS PARAMETERS DURING SEMICONDUCTOR DEVICE FABRICATION

Patent #:	9704966	Issue Dt:	07/11/2017	Application #:	15218318	Filing Dt:	07/25/2016
Title:	FIN-BASED RF DIODES

Patent #:	10062772	Issue Dt:	08/28/2018	Application #:	15219370	Filing Dt:	07/26/2016
Publication #:	US20180033870	Pub Dt:	02/01/2018
Title:	PREVENTING BRIDGE FORMATION BETWEEN REPLACEMENT GATE AND SOURCE/DRAIN REGION THROUGH STI STRUCTURE

Patent #:	9721889	Issue Dt:	08/01/2017	Application #:	15219378	Filing Dt:	07/26/2016
Title:	MIDDLE OF THE LINE (MOL) METAL CONTACTS

Patent #:	10014389	Issue Dt:	07/03/2018	Application #:	15219403	Filing Dt:	07/26/2016
Publication #:	US20180033871	Pub Dt:	02/01/2018
Title:	METHODS OF FORMING IC PRODUCTS COMPRISING A NANO-SHEET DEVICE AND A TRANSISTOR DEVICE HAVING FIRST AND SECOND REPLACEMENT GATE STRUCTURES

Patent #:	9847418	Issue Dt:	12/19/2017	Application #:	15219917	Filing Dt:	07/26/2016
Title:	METHODS OF FORMING FIN CUT REGIONS BY OXIDIZING FIN PORTIONS

Patent #:	9741720	Issue Dt:	08/22/2017	Application #:	15219967	Filing Dt:	07/26/2016
Title:	HIGHER 'K' GATE DIELECTRIC CAP FOR REPLACEMENT METAL GATE (RMG) FINFET DEVICES

Patent #:	9997456	Issue Dt:	06/12/2018	Application #:	15220764	Filing Dt:	07/27/2016
Publication #:	US20180033718	Pub Dt:	02/01/2018
Title:	INTERCONNECT STRUCTURE HAVING POWER RAIL STRUCTURE AND RELATED METHOD

Patent #:	9831346	Issue Dt:	11/28/2017	Application #:	15220990	Filing Dt:	07/27/2016
Title:	FINFETS WITH AIR-GAP SPACERS AND METHODS FOR FORMING THE SAME

Patent #:	10079208	Issue Dt:	09/18/2018	Application #:	15221647	Filing Dt:	07/28/2016
Publication #:	US20180033728	Pub Dt:	02/01/2018
Title:	IC STRUCTURE WITH INTERFACE LINER AND METHODS OF FORMING SAME

Patent #:	9899183	Issue Dt:	02/20/2018	Application #:	15222096	Filing Dt:	07/28/2016
Publication #:	US20180033590	Pub Dt:	02/01/2018
Title:	STRUCTURE AND METHOD TO MEASURE FOCUS-DEPENDENT PATTERN SHIFT IN INTEGRATED CIRCUIT IMAGING

Patent #:	10593780	Issue Dt:	03/17/2020	Application #:	15222261	Filing Dt:	07/28/2016
Publication #:	US20170103917	Pub Dt:	04/13/2017
Title:	FORMING REPLACEMENT LOW-K SPACER IN TIGHT PITCH FIN FIELD EFFECT TRANSISTORS

Patent #:	10593575	Issue Dt:	03/17/2020	Application #:	15223882	Filing Dt:	07/29/2016
Publication #:	US20160336206	Pub Dt:	11/17/2016
Title:	SYSTEM AND METHOD FOR MONITORING WAFER HANDLING AND A WAFER HANDLING MACHINE

Patent #:	9646885	Issue Dt:	05/09/2017	Application #:	15224091	Filing Dt:	07/29/2016
Title:	METHOD TO PREVENT LATERAL EPITAXIAL GROWTH IN SEMICONDUCTOR DEVICES BY PERFORMING PLASMA NITRIDATION PROCESS ON FIN ENDS

Patent #:	NONE	Issue Dt:		Application #:	15224139	Filing Dt:	07/29/2016
Publication #:	US20180033789	Pub Dt:	02/01/2018
Title:	METHOD, APPARATUS, AND SYSTEM FOR REDUCING DOPANT CONCENTRATIONS IN CHANNEL REGIONS OF FINFET DEVICES

Patent #:	10008577	Issue Dt:	06/26/2018	Application #:	15225152	Filing Dt:	08/01/2016
Publication #:	US20180033863	Pub Dt:	02/01/2018
Title:	METHODS OF FORMING AN AIR-GAP SPACER ON A SEMICONDUCTOR DEVICE AND THE RESULTING DEVICE

Patent #:	9653583	Issue Dt:	05/16/2017	Application #:	15226165	Filing Dt:	08/02/2016
Title:	METHODS OF FORMING DIFFUSION BREAKS ON INTEGRATED CIRCUIT PRODUCTS COMPRISED OF FINFET DEVICES

Patent #:	9899375	Issue Dt:	02/20/2018	Application #:	15226575	Filing Dt:	08/02/2016
Publication #:	US20180040611	Pub Dt:	02/08/2018
Title:	CO-INTEGRATION OF SELF-ALIGNED AND NON-SELF ALIGNED HETEROJUNCTION BIPOLAR TRANSISTORS

Patent #:	10340288	Issue Dt:	07/02/2019	Application #:	15226867	Filing Dt:	08/02/2016
Publication #:	US20180040631	Pub Dt:	02/08/2018
Title:	METHOD, APPARATUS, AND SYSTEM FOR IMPROVED MEMORY CELL DESIGN HAVING UNIDIRECTIONAL LAYOUT USING SELF-ALIGNED DOUBLE PATTERNING

Patent #:	9882081	Issue Dt:	01/30/2018	Application #:	15227081	Filing Dt:	08/03/2016
Publication #:	US20170062647	Pub Dt:	03/02/2017
Title:	PHOTODETECTOR METHODS AND PHOTODETECTOR STRUCTURES

Patent #:	10170319	Issue Dt:	01/01/2019	Application #:	15227142	Filing Dt:	08/03/2016
Publication #:	US20170047226	Pub Dt:	02/16/2017
Title:	FORMING A CONTACT FOR A TALL FIN TRANSISTOR

Patent #:	9966433	Issue Dt:	05/08/2018	Application #:	15227330	Filing Dt:	08/03/2016
Publication #:	US20180040696	Pub Dt:	02/08/2018
Title:	MULTIPLE-STEP EPITAXIAL GROWTH S/D REGIONS FOR NMOS FINFET

Patent #:	9917009	Issue Dt:	03/13/2018	Application #:	15228317	Filing Dt:	08/04/2016
Publication #:	US20180040511	Pub Dt:	02/08/2018
Title:	METHODS OF FORMING A THROUGH-SUBSTRATE-VIA (TSV) AND A METALLIZATION LAYER AFTER FORMATION OF A SEMICONDUCTOR DEVICE

Patent #:	10030971	Issue Dt:	07/24/2018	Application #:	15228772	Filing Dt:	08/04/2016
Publication #:	US20170038201	Pub Dt:	02/09/2017
Title:	MEASUREMENT SYSTEM AND METHOD FOR MEASURING IN THIN FILMS

Patent #:	9825031	Issue Dt:	11/21/2017	Application #:	15229292	Filing Dt:	08/05/2016
Title:	METHODS OF FORMING A HIGH-K CONTACT LINER TO IMPROVE EFFECTIVE VIA SEPARATION DISTANCE AND THE RESULTING DEVICES

Patent #:	9966313	Issue Dt:	05/08/2018	Application #:	15229431	Filing Dt:	08/05/2016
Publication #:	US20180040516	Pub Dt:	02/08/2018
Title:	FINFET DEVICE AND METHOD OF MANUFACTURING

Patent #:	9666582	Issue Dt:	05/30/2017	Application #:	15230632	Filing Dt:	08/08/2016
Title:	ON-CHIP FINFET STRUCTURES TO IMPLEMENT PHYSICAL UNCLONABLE FUNCTION FOR SECURITY APPLICATION

Patent #:	9966466	Issue Dt:	05/08/2018	Application #:	15231105	Filing Dt:	08/08/2016
Publication #:	US20180040731	Pub Dt:	02/08/2018
Title:	SEMICONDUCTOR-ON-INSULATOR WAFER, SEMICONDUCTOR STRUCTURE INCLUDING A TRANSISTOR, AND METHODS FOR THE FORMATION AND OPERATION THEREOF

Patent #:	9864136	Issue Dt:	01/09/2018	Application #:	15231840	Filing Dt:	08/09/2016
Title:	NON-PLANAR MONOLITHIC HYBRID OPTOELECTRONIC STRUCTURES AND METHODS

Patent #:	10062619	Issue Dt:	08/28/2018	Application #:	15232090	Filing Dt:	08/09/2016
Publication #:	US20180047642	Pub Dt:	02/15/2018
Title:	AIR GAP SPACER IMPLANT FOR NZG RELIABILITY FIX

Patent #:	9711648	Issue Dt:	07/18/2017	Application #:	15232164	Filing Dt:	08/09/2016
Title:	STRUCTURE AND METHOD FOR CMP-FREE III-V ISOLATION

Patent #:	9824933	Issue Dt:	11/21/2017	Application #:	15232174	Filing Dt:	08/09/2016
Title:	STACKED VERTICAL-TRANSPORT FIELD-EFFECT TRANSISTORS

Patent #:	9564440	Issue Dt:	02/07/2017	Application #:	15232246	Filing Dt:	08/09/2016
Publication #:	US20160365348	Pub Dt:	12/15/2016
Title:	SPACER CHAMFERING GATE STACK SCHEME

Patent #:	9780185	Issue Dt:	10/03/2017	Application #:	15232300	Filing Dt:	08/09/2016
Publication #:	US20160365290	Pub Dt:	12/15/2016
Title:	SPACER CHAMFERING GATE STACK SCHEME

Patent #:	9768028	Issue Dt:	09/19/2017	Application #:	15232873	Filing Dt:	08/10/2016
Title:	SEMICONDUCTOR STRUCTURE WITH A DOPANT IMPLANT REGION HAVING A LINEARLY GRADED CONDUCTIVITY LEVEL AND METHOD OF FORMING THE STRUCTURE

Patent #:	9871050	Issue Dt:	01/16/2018	Application #:	15232906	Filing Dt:	08/10/2016
Title:	FLASH MEMORY DEVICE

Patent #:	NONE	Issue Dt:		Application #:	15233229	Filing Dt:	08/10/2016
Publication #:	US20180047807	Pub Dt:	02/15/2018
Title:	DEEP TRENCH CAPACITORS WITH A DIFFUSION PAD

Patent #:	9773881	Issue Dt:	09/26/2017	Application #:	15233315	Filing Dt:	08/10/2016
Publication #:	US20170125539	Pub Dt:	05/04/2017
Title:	ETCH STOP FOR AIRGAP PROTECTION

Patent #:	NONE	Issue Dt:		Application #:	15233445	Filing Dt:	08/10/2016
Publication #:	US20180047564	Pub Dt:	02/15/2018
Title:	METHOD TO TUNE CONTACT CD AND REDUCE MASK COUNT BY TILTED ION BEAM

Patent #:	10931143	Issue Dt:	02/23/2021	Application #:	15233454	Filing Dt:	08/10/2016
Publication #:	US20180048169	Pub Dt:	02/15/2018
Title:	RECHARGEABLE WAFER CARRIER SYSTEMS

Patent #:	9972634	Issue Dt:	05/15/2018	Application #:	15234066	Filing Dt:	08/11/2016
Publication #:	US20180047738	Pub Dt:	02/15/2018
Title:	SEMICONDUCTOR DEVICE COMPRISING A FLOATING GATE FLASH MEMORY DEVICE

Patent #:	9927698	Issue Dt:	03/27/2018	Application #:	15234078	Filing Dt:	08/11/2016
Publication #:	US20180046073	Pub Dt:	02/15/2018
Title:	DUAL EXPOSURE PATTERNING OF A PHOTOMASK TO PRINT A CONTACT, A VIA OR A CURVILINEAR SHAPE ON AN INTEGRATED CIRCUIT

Patent #:	NONE	Issue Dt:		Application #:	15234361	Filing Dt:	08/11/2016
Publication #:	US20170338350	Pub Dt:	11/23/2017
Title:	SEMICONDUCTOR DEVICE AND METHOD

Patent #:	9972620	Issue Dt:	05/15/2018	Application #:	15234762	Filing Dt:	08/11/2016
Publication #:	US20180047727	Pub Dt:	02/15/2018
Title:	PREVENTING SHORTING BETWEEN SOURCE AND/OR DRAIN CONTACTS AND GATE

Patent #:	9837439	Issue Dt:	12/05/2017	Application #:	15235256	Filing Dt:	08/12/2016
Title:	COMPENSATION OF TEMPERATURE EFFECTS IN SEMICONDUCTOR DEVICE STRUCTURES

Patent #:	9704746	Issue Dt:	07/11/2017	Application #:	15235892	Filing Dt:	08/12/2016
Title:	ADVANCED SELF-ALIGNED PATTERNING PROCESS WITH SIT SPACER AS A FINAL DIELECTRIC ETCH HARDMASK

Patent #:	9825041	Issue Dt:	11/21/2017	Application #:	15236608	Filing Dt:	08/15/2016
Title:	INTEGRATED CIRCUIT STRUCTURE WITH INSULATED MEMORY DEVICE AND RELATED METHODS

Patent #:	9947602	Issue Dt:	04/17/2018	Application #:	15237066	Filing Dt:	08/15/2016
Publication #:	US20180047648	Pub Dt:	02/15/2018
Title:	IC STRUCTURE INTEGRITY SENSOR HAVING INTERDIGITATED CONDUCTIVE ELEMENTS

Patent #:	10084057	Issue Dt:	09/25/2018	Application #:	15237794	Filing Dt:	08/16/2016
Publication #:	US20180053832	Pub Dt:	02/22/2018
Title:	NVM DEVICE IN SOI TECHNOLOGY AND METHOD OF FABRICATING AN ACCORDING DEVICE

Patent #:	10056376	Issue Dt:	08/21/2018	Application #:	15238023	Filing Dt:	08/16/2016
Publication #:	US20160358915	Pub Dt:	12/08/2016
Title:	FERROELECTRIC FINFET

Patent #:	9905552	Issue Dt:	02/27/2018	Application #:	15238107	Filing Dt:	08/16/2016
Publication #:	US20180053757	Pub Dt:	02/22/2018
Title:	ASSIST CUTS DISPOSED IN DUMMY LINES TO IMPROVE METAL SIGNAL CUTS IN ACTIVE LINES OF A SEMICONDUCTOR STRUCTURE

Patent #:	NONE	Issue Dt:		Application #:	15238760	Filing Dt:	08/17/2016
Publication #:	US20180053662	Pub Dt:	02/22/2018
Title:	TEXTURING OF SILICON SURFACE WITH DIRECT-SELF ASSEMBLY PATTERNING

Patent #:	NONE	Issue Dt:		Application #:	15238884	Filing Dt:	08/17/2016
Publication #:	US20160359038	Pub Dt:	12/08/2016
Title:	LOCAL THINNING OF SEMICONDUCTOR FINS

Patent #:	9952500	Issue Dt:	04/24/2018	Application #:	15239072	Filing Dt:	08/17/2016
Publication #:	US20180052388	Pub Dt:	02/22/2018
Title:	ADJUSTING OF PATTERNS IN DESIGN LAYOUT FOR OPTICAL PROXIMITY CORRECTION

Patent #:	10068899	Issue Dt:	09/04/2018	Application #:	15239976	Filing Dt:	08/18/2016
Publication #:	US20180053743	Pub Dt:	02/22/2018
Title:	IC STRUCTURE ON TWO SIDES OF SUBSTRATE AND METHOD OF FORMING

Patent #:	9997418	Issue Dt:	06/12/2018	Application #:	15240554	Filing Dt:	08/18/2016
Publication #:	US20160372332	Pub Dt:	12/22/2016
Title:	DUAL LINER SILICIDE

Patent #:	9773717	Issue Dt:	09/26/2017	Application #:	15242643	Filing Dt:	08/22/2016
Title:	INTEGRATED CIRCUITS WITH PELTIER COOLING PROVIDED BY BACK-END WIRING

Patent #:	9741615	Issue Dt:	08/22/2017	Application #:	15242951	Filing Dt:	08/22/2016
Title:	CONTACTS FOR A FIN-TYPE FIELD-EFFECT TRANSISTOR

Patent #:	10170583	Issue Dt:	01/01/2019	Application #:	15244067	Filing Dt:	08/23/2016
Publication #:	US20170054004	Pub Dt:	02/23/2017
Title:	FORMING A GATE CONTACT IN THE ACTIVE AREA

Patent #:	9773708	Issue Dt:	09/26/2017	Application #:	15245634	Filing Dt:	08/24/2016
Title:	DEVICES AND METHODS OF FORMING VFET WITH SELF-ALIGNED REPLACEMENT METAL GATES ALIGNED TO TOP SPACER POST TOP SOURCE DRAIN EPI

Patent #:	10043764	Issue Dt:	08/07/2018	Application #:	15247513	Filing Dt:	08/25/2016
Publication #:	US20160372425	Pub Dt:	12/22/2016
Title:	THROUGH SILICON VIA DEVICE HAVING LOW STRESS, THIN FILM GAPS AND METHODS FOR FORMING THE SAME

Patent #:	9842927	Issue Dt:	12/12/2017	Application #:	15248367	Filing Dt:	08/26/2016
Title:	INTEGRATED CIRCUIT STRUCTURE WITHOUT GATE CONTACT AND METHOD OF FORMING SAME

Patent #:	10014303	Issue Dt:	07/03/2018	Application #:	15248889	Filing Dt:	08/26/2016
Publication #:	US20180061842	Pub Dt:	03/01/2018
Title:	DEVICES WITH CONTACT-TO-GATE SHORTING THROUGH CONDUCTIVE PATHS BETWEEN FINS AND FABRICATION METHODS

Patent #:	10199315	Issue Dt:	02/05/2019	Application #:	15249700	Filing Dt:	08/29/2016
Publication #:	US20180061749	Pub Dt:	03/01/2018
Title:	POST ZERO VIA LAYER KEEP OUT ZONE OVER THROUGH SILICON VIA REDUCING BEOL PUMPING EFFECTS

Patent #:	9728626	Issue Dt:	08/08/2017	Application #:	15251435	Filing Dt:	08/30/2016
Title:	ALMOST DEFECT-FREE ACTIVE CHANNEL REGION

Patent #:	9679888	Issue Dt:	06/13/2017	Application #:	15251632	Filing Dt:	08/30/2016
Title:	ESD DEVICE FOR A SEMICONDUCTOR STRUCTURE

Patent #:	10388602	Issue Dt:	08/20/2019	Application #:	15251804	Filing Dt:	08/30/2016
Publication #:	US20170170118	Pub Dt:	06/15/2017
Title:	LOCAL INTERCONNECT STRUCTURE INCLUDING NON-ERODED CONTACT VIA TRENCHES

Patent #:	9559018	Issue Dt:	01/31/2017	Application #:	15252315	Filing Dt:	08/31/2016
Publication #:	US20160372493	Pub Dt:	12/22/2016
Title:	DUAL CHANNEL FINFET WITH RELAXED PFET REGION

Patent #:	9607903	Issue Dt:	03/28/2017	Application #:	15252586	Filing Dt:	08/31/2016
Publication #:	US20170040224	Pub Dt:	02/09/2017
Title:	METHOD FOR FORMING FIELD EFFECT TRANSISTORS

Patent #:	10418364	Issue Dt:	09/17/2019	Application #:	15252995	Filing Dt:	08/31/2016
Publication #:	US20180061839	Pub Dt:	03/01/2018
Title:	SEMICONDUCTOR DEVICE STRUCTURE WITH SELF-ALIGNED CAPACITOR DEVICE

Patent #:	10026645	Issue Dt:	07/17/2018	Application #:	15253097	Filing Dt:	08/31/2016
Publication #:	US20180061699	Pub Dt:	03/01/2018
Title:	MULTIPLE PATTERNING PROCESS FOR FORMING PILLAR MASK ELEMENTS

Patent #:	9640436	Issue Dt:	05/02/2017	Application #:	15254096	Filing Dt:	09/01/2016
Publication #:	US20170140987	Pub Dt:	05/18/2017
Title:	MOSFET WITH ASYMMETRIC SELF-ALIGNED CONTACT

Patent #:	10095115	Issue Dt:	10/09/2018	Application #:	15255237	Filing Dt:	09/02/2016
Publication #:	US20180067396	Pub Dt:	03/08/2018
Title:	FORMING EDGE ETCH PROTECTION USING DUAL LAYER OF POSITIVE-NEGATIVE TONE RESISTS

Patent #:	9570583	Issue Dt:	02/14/2017	Application #:	15255628	Filing Dt:	09/02/2016
Publication #:	US20160372576	Pub Dt:	12/22/2016
Title:	RECESSING RMG METAL GATE STACK FOR FORMING SELF-ALIGNED CONTACT

Patent #:	10050119	Issue Dt:	08/14/2018	Application #:	15256027	Filing Dt:	09/02/2016
Publication #:	US20180069091	Pub Dt:	03/08/2018
Title:	METHOD FOR LATE DIFFERENTIAL SOI THINNING FOR IMPROVED FDSOI PERFORMANCE AND HCI OPTIMIZATION

Patent #:	10090195	Issue Dt:	10/02/2018	Application #:	15257245	Filing Dt:	09/06/2016
Publication #:	US20170117179	Pub Dt:	04/27/2017
Title:	METHOD INCLUDING A FORMATION OF A DIFFUSION BARRIER AND SEMICONDUCTOR STRUCTURE INCLUDING A DIFFUSION BARRIER

Patent #:	10289109	Issue Dt:	05/14/2019	Application #:	15258217	Filing Dt:	09/07/2016
Publication #:	US20170097638	Pub Dt:	04/06/2017
Title:	METHODS OF ERROR DETECTION IN FABRICATION PROCESSES

Patent #:	10056468	Issue Dt:	08/21/2018	Application #:	15258333	Filing Dt:	09/07/2016
Publication #:	US20180069092	Pub Dt:	03/08/2018
Title:	SOURCE/DRAIN PARASITIC CAPACITANCE REDUCTION IN FINFET-BASED SEMICONDUCTOR STRUCTURE HAVING TUCKED FINS

Patent #:	9960252	Issue Dt:	05/01/2018	Application #:	15258597	Filing Dt:	09/07/2016
Publication #:	US20160380076	Pub Dt:	12/29/2016
Title:	METHOD TO IMPROVE RELIABILITY OF REPLACEMENT GATE DEVICE

Patent #:	10056381	Issue Dt:	08/21/2018	Application #:	15259268	Filing Dt:	09/08/2016
Publication #:	US20180069005	Pub Dt:	03/08/2018
Title:	PUNCHTHROUGH STOP LAYERS FOR FIN-TYPE FIELD-EFFECT TRANSISTORS

Patent #:	10096604	Issue Dt:	10/09/2018	Application #:	15259472	Filing Dt:	09/08/2016
Publication #:	US20180069009	Pub Dt:	03/08/2018
Title:	SELECTIVE SAC CAPPING ON FIN FIELD EFFECT TRANSISTOR STRUCTURES AND RELATED METHODS

Patent #:	9786751	Issue Dt:	10/10/2017	Application #:	15263551	Filing Dt:	09/13/2016
Publication #:	US20160380065	Pub Dt:	12/29/2016
Title:	SEMICONDUCTOR STRUCTURES WITH FIELD EFFECT TRANSISTOR(S) HAVING LOW-RESISTANCE SOURCE/DRAIN CONTACT(S)

Patent #:	9715064	Issue Dt:	07/25/2017	Application #:	15263817	Filing Dt:	09/13/2016
Title:	MULTI-CHIP MODULES WITH VERTICALLY ALIGNED GRATING COUPLERS FOR TRANSMISSION OF LIGHT SIGNALS BETWEEN OPTICAL WAVEGUIDES

100

Patent #:	10192864	Issue Dt:	01/29/2019	Application #:	15264885	Filing Dt:	09/14/2016
Publication #:	US20170005085	Pub Dt:	01/05/2017
Title:	LATERAL BICMOS REPLACEMENT METAL GATE

Assignor

GLOBALFOUNDRIES INC.

Exec Dt:

11/27/2018

Assignee

WILMINGTON TRUST, NATIONAL ASSOCIATION

1100 NORTH MARKET STREET

WILMINGTON, DELAWARE 19801

Correspondence name and address
	CT CORPORATION
	4400 EASTON COMMONS WAY
	SUITE 125
	COLUMBUS, OH 43219

Search Results as of: 05/08/2024 02:34 AM

If you have any comments or questions concerning the data displayed, contact PRD / Assignments at 571-272-3350. v.2.6

Web interface last modified: August 25, 2017 v.2.6