|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/19/2017
|
Application #:
|
15344856
|
Filing Dt:
|
11/07/2016
|
|
Title:
|
SEMICONDUCTOR STRUCTURE INCLUDING A FIRST TRANSISTOR AT A SEMICONDUCTOR-ON-INSULATOR REGION AND A SECOND TRANSISTOR AT A BULK REGION AND METHOD FOR THE FORMATION THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/22/2018
|
Application #:
|
15344862
|
Filing Dt:
|
11/07/2016
|
|
Publication #:
|
|
Pub Dt:
|
05/10/2018
| | | | |
|
Title:
|
NANOSTRUCTURE FIELD-EFFECT TRANSISTORS WITH ENHANCED MOBILITY SOURCE/DRAIN REGIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/19/2018
|
Application #:
|
15345137
|
Filing Dt:
|
11/07/2016
|
|
Publication #:
|
|
Pub Dt:
|
05/10/2018
| | | | |
|
Title:
|
SELF-ALIGNED CONTACT PROTECTION USING REINFORCED GATE CAP AND SPACER PORTIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/26/2019
|
Application #:
|
15345544
|
Filing Dt:
|
11/08/2016
|
|
Publication #:
|
|
Pub Dt:
|
05/10/2018
| | | | |
|
Title:
|
BENDING CIRCUIT FOR STATIC RANDOM ACCESS MEMORY (SRAM) SELF-TIMER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/09/2019
|
Application #:
|
15345608
|
Filing Dt:
|
11/08/2016
|
|
Publication #:
|
|
Pub Dt:
|
05/10/2018
| | | | |
|
Title:
|
SEPARATION OF INTEGRATED CIRCUIT STRUCTURE FROM ADJACENT CHIP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/29/2018
|
Application #:
|
15345612
|
Filing Dt:
|
11/08/2016
|
|
Publication #:
|
|
Pub Dt:
|
05/10/2018
| | | | |
|
Title:
|
SEMICONDUCTOR FIN LOOP FOR USE WITH DIFFUSION BREAK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/08/2018
|
Application #:
|
15345644
|
Filing Dt:
|
11/08/2016
|
|
Publication #:
|
|
Pub Dt:
|
05/10/2018
| | | | |
|
Title:
|
METHODS OF FORMING GATE ELECTRODES ON A VERTICAL TRANSISTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/2019
|
Application #:
|
15345882
|
Filing Dt:
|
11/08/2016
|
|
Publication #:
|
|
Pub Dt:
|
05/10/2018
| | | | |
|
Title:
|
SKIP VIA STRUCTURES
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
15346504
|
Filing Dt:
|
11/08/2016
|
|
Publication #:
|
|
Pub Dt:
|
10/19/2017
| | | | |
|
Title:
|
METHOD, SYSTEM AND PROGRAM PRODUCT FOR SADP-FRIENDLY INTERCONNECT STRUCTURE TRACK GENERATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2018
|
Application #:
|
15347119
|
Filing Dt:
|
11/09/2016
|
|
Publication #:
|
|
Pub Dt:
|
05/10/2018
| | | | |
|
Title:
|
STRUCTURE AND METHOD FOR CAPPING COBALT CONTACTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/23/2018
|
Application #:
|
15348109
|
Filing Dt:
|
11/10/2016
|
|
Title:
|
SPACER DEFINED FIN GROWTH AND DIFFERENTIAL FIN WIDTH
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
15348356
|
Filing Dt:
|
11/10/2016
|
|
Publication #:
|
|
Pub Dt:
|
05/10/2018
| | | | |
|
Title:
|
GATE STRUCTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/12/2017
|
Application #:
|
15349306
|
Filing Dt:
|
11/11/2016
|
|
Title:
|
METHOD OF MANUFACTURING A SEMICONDUCTOR WAFER HAVING AN SOI CONFIGURATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/14/2017
|
Application #:
|
15349358
|
Filing Dt:
|
11/11/2016
|
|
Title:
|
METHOD FOR FABRICATING A FINFET METALLIZATION ARCHITECTURE USING A SELF-ALIGNED CONTACT ETCH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/19/2017
|
Application #:
|
15351597
|
Filing Dt:
|
11/15/2016
|
|
Title:
|
PERFORMANCE-ENHANCED VERTICAL DEVICE AND METHOD OF FORMING THEREOF
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
15351678
|
Filing Dt:
|
11/15/2016
|
|
Publication #:
|
|
Pub Dt:
|
05/17/2018
| | | | |
|
Title:
|
SEMICONDUCTOR SUBSTRATE WITH METALLIC DOPED BURIED OXIDE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/15/2018
|
Application #:
|
15351747
|
Filing Dt:
|
11/15/2016
|
|
Publication #:
|
|
Pub Dt:
|
05/17/2018
| | | | |
|
Title:
|
METHOD AND STRUCTURE TO CONTROL CHANNEL LENGTH IN VERTICAL FET DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2019
|
Application #:
|
15351893
|
Filing Dt:
|
11/15/2016
|
|
Publication #:
|
|
Pub Dt:
|
05/17/2018
| | | | |
|
Title:
|
TRANSISTOR-BASED SEMICONDUCTOR DEVICE WITH AIR-GAP SPACERS AND GATE CONTACT OVER ACTIVE AREA
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/29/2017
|
Application #:
|
15352102
|
Filing Dt:
|
11/15/2016
|
|
Title:
|
METHODS OF FORMING SEMICONDUCTOR DEVICES USING SEMI-BIDIRECTIONAL PATTERNING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/09/2018
|
Application #:
|
15352139
|
Filing Dt:
|
11/15/2016
|
|
Title:
|
METHODS OF FORMING SEMICONDUCTOR DEVICES USING SEMI-BIDIRECTIONAL PATTERNING AND ISLANDS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/13/2018
|
Application #:
|
15352654
|
Filing Dt:
|
11/16/2016
|
|
Title:
|
CONTACT PUNCH THROUGH MITIGATION IN SOI SUBSTRATE
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
15352963
|
Filing Dt:
|
11/16/2016
|
|
Publication #:
|
|
Pub Dt:
|
05/17/2018
| | | | |
|
Title:
|
FORMATION OF BAND-EDGE CONTACTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/13/2018
|
Application #:
|
15353352
|
Filing Dt:
|
11/16/2016
|
|
Publication #:
|
|
Pub Dt:
|
10/05/2017
| | | | |
|
Title:
|
FABRICATION OF VERTICAL FIELD EFFECT TRANSISTOR STRUCTURE WITH CONTROLLED GATE LENGTH
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
15353771
|
Filing Dt:
|
11/17/2016
|
|
Publication #:
|
|
Pub Dt:
|
05/17/2018
| | | | |
|
Title:
|
METHODS OF FORMING INTEGRATED CIRCUIT STRUCTURE WITH SILICIDE REIGON
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
15354047
|
Filing Dt:
|
11/17/2016
|
|
Publication #:
|
|
Pub Dt:
|
05/17/2018
| | | | |
|
Title:
|
TUNNEL FINFET WITH SELF-ALIGNED GATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2018
|
Application #:
|
15354205
|
Filing Dt:
|
11/17/2016
|
|
Publication #:
|
|
Pub Dt:
|
05/17/2018
| | | | |
|
Title:
|
SELF-ALIGNED BACK-PLANE AND WELL CONTACTS FOR FULLY DEPLETED SILICON ON INSULATOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/10/2018
|
Application #:
|
15354212
|
Filing Dt:
|
11/17/2016
|
|
Title:
|
SELF-ALIGNED MIDDLE OF THE LINE (MOL) CONTACTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/18/2018
|
Application #:
|
15355231
|
Filing Dt:
|
11/18/2016
|
|
Publication #:
|
|
Pub Dt:
|
05/24/2018
| | | | |
|
Title:
|
FIELD-EFFECT TRANSISTORS WITH A BURIED BODY CONTACT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/29/2019
|
Application #:
|
15355256
|
Filing Dt:
|
11/18/2016
|
|
Publication #:
|
|
Pub Dt:
|
05/24/2018
| | | | |
|
Title:
|
EARLY DEVELOPMENT OF A DATABASE OF FAIL SIGNATURES FOR SYSTEMATIC DEFECTS IN INTEGRATED CIRCUIT (IC) CHIPS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/2020
|
Application #:
|
15355584
|
Filing Dt:
|
11/18/2016
|
|
Publication #:
|
|
Pub Dt:
|
05/24/2018
| | | | |
|
Title:
|
Parallel Stacked Inductor for High-Q and High Current Handling and Method of Making the Same
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/02/2018
|
Application #:
|
15357287
|
Filing Dt:
|
11/21/2016
|
|
Publication #:
|
|
Pub Dt:
|
05/04/2017
| | | | |
|
Title:
|
SOURCE AND DRAIN EPITAXIAL SEMICONDUCTOR MATERIAL INTEGRATION FOR HIGH VOLTAGE SEMICONDUCTOR DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/21/2018
|
Application #:
|
15359037
|
Filing Dt:
|
11/22/2016
|
|
Publication #:
|
|
Pub Dt:
|
05/24/2018
| | | | |
|
Title:
|
SELF-ALIGNED LITHOGRAPHIC PATTERNING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/10/2019
|
Application #:
|
15359953
|
Filing Dt:
|
11/23/2016
|
|
Publication #:
|
|
Pub Dt:
|
06/22/2017
| | | | |
|
Title:
|
SELF ALIGNED GATE SHAPE PREVENTING VOID FORMATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/21/2018
|
Application #:
|
15360255
|
Filing Dt:
|
11/23/2016
|
|
Publication #:
|
|
Pub Dt:
|
05/24/2018
| | | | |
|
Title:
|
POST SPACER SELF-ALIGNED CUTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/11/2018
|
Application #:
|
15360295
|
Filing Dt:
|
11/23/2016
|
|
Publication #:
|
|
Pub Dt:
|
05/24/2018
| | | | |
|
Title:
|
HETEROJUNCTION BIPOLAR TRANSISTOR DEVICE INTEGRATION SCHEMES ON A SAME WAFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/21/2017
|
Application #:
|
15360537
|
Filing Dt:
|
11/23/2016
|
|
Title:
|
METAL LAYER ROUTING LEVEL FOR VERTICAL FET SRAM AND LOGIC CELL SCALING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/26/2018
|
Application #:
|
15361790
|
Filing Dt:
|
11/28/2016
|
|
Publication #:
|
|
Pub Dt:
|
05/31/2018
| | | | |
|
Title:
|
SPACERS FOR TIGHT GATE PITCHES IN FIELD EFFECT TRANSISTORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/06/2018
|
Application #:
|
15361809
|
Filing Dt:
|
11/28/2016
|
|
Publication #:
|
|
Pub Dt:
|
05/31/2018
| | | | |
|
Title:
|
SEMICONDUCTOR STRUCTURE INCLUDING TWO-DIMENSIONAL AND THREE-DIMENSIONAL BONDING MATERIALS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2018
|
Application #:
|
15361824
|
Filing Dt:
|
11/28/2016
|
|
Title:
|
METHODS FOR FORMING DIFFERENT SHAPES IN DIFFERENT REGIONS OF THE SAME LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/30/2018
|
Application #:
|
15361994
|
Filing Dt:
|
11/28/2016
|
|
Publication #:
|
|
Pub Dt:
|
03/16/2017
| | | | |
|
Title:
|
EPITAXIAL AND SILICIDE LAYER FORMATION AT TOP AND BOTTOM SURFACES OF SEMICONDUCTOR FINS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/26/2017
|
Application #:
|
15362035
|
Filing Dt:
|
11/28/2016
|
|
Title:
|
METHOD OF PATTERNING PILLARS TO FORM VARIABLE CONTINUITY CUTS IN INTERCONNECTION LINES OF AN INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/20/2018
|
Application #:
|
15362499
|
Filing Dt:
|
11/28/2016
|
|
Title:
|
STRUCTURE AND METHOD OF CONDUCTIVE BUS BAR FOR RESISTIVE SEED SUBSTRATE PLATING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/01/2017
|
Application #:
|
15363056
|
Filing Dt:
|
11/29/2016
|
|
Title:
|
DISTRIBUTED CURRENT SOURCE/SINK USING INACTIVE MEMORY ELEMENTS
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
15363267
|
Filing Dt:
|
11/29/2016
|
|
Publication #:
|
|
Pub Dt:
|
05/31/2018
| | | | |
|
Title:
|
STIFFENER FOR FAN-OUT WAFER LEVEL PACKAGING AND METHOD OF MANUFACTURING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/17/2018
|
Application #:
|
15363461
|
Filing Dt:
|
11/29/2016
|
|
Title:
|
MULTIPLE-LAYER SPACERS FOR FIELD-EFFECT TRANSISTORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2018
|
Application #:
|
15363513
|
Filing Dt:
|
11/29/2016
|
|
Title:
|
SELF ALIGNED INTERCONNECT STRUCTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/19/2018
|
Application #:
|
15363563
|
Filing Dt:
|
11/29/2016
|
|
Publication #:
|
|
Pub Dt:
|
03/16/2017
| | | | |
|
Title:
|
SPACER CHAMFERING GATE STACK SCHEME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/27/2018
|
Application #:
|
15363596
|
Filing Dt:
|
11/29/2016
|
|
Publication #:
|
|
Pub Dt:
|
03/30/2017
| | | | |
|
Title:
|
METHOD FOR FIN FORMATION WITH A SELF-ALIGNED DIRECTED SELF-ASSEMBLY PROCESS AND CUT-LAST SCHEME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/12/2019
|
Application #:
|
15363607
|
Filing Dt:
|
11/29/2016
|
|
Publication #:
|
|
Pub Dt:
|
03/30/2017
| | | | |
|
Title:
|
METHOD FOR FIN FORMATION WITH A SELF-ALIGNED DIRECTED SELF-ASSEMBLY PROCESS AND CUT-LAST SCHEME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/27/2018
|
Application #:
|
15366223
|
Filing Dt:
|
12/01/2016
|
|
Publication #:
|
|
Pub Dt:
|
03/23/2017
| | | | |
|
Title:
|
DUAL LINER SILICIDE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/18/2018
|
Application #:
|
15366425
|
Filing Dt:
|
12/01/2016
|
|
Publication #:
|
|
Pub Dt:
|
06/07/2018
| | | | |
|
Title:
|
LOGIC AND FLASH FIELD-EFFECT TRANSISTORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/31/2017
|
Application #:
|
15366514
|
Filing Dt:
|
12/01/2016
|
|
Title:
|
METHOD OF FORMING SEMICONDUCTOR STRUCTURE INCLUDING SUSPENDED SEMICONDUCTOR LAYER AND RESULTING STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/09/2019
|
Application #:
|
15367366
|
Filing Dt:
|
12/02/2016
|
|
Publication #:
|
|
Pub Dt:
|
03/23/2017
| | | | |
|
Title:
|
FIN STRUCTURES AND MULTI-VT SCHEME BASED ON TAPERED FIN AND METHOD TO FORM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/28/2018
|
Application #:
|
15367815
|
Filing Dt:
|
12/02/2016
|
|
Publication #:
|
|
Pub Dt:
|
06/07/2018
| | | | |
|
Title:
|
PARALLEL PROGRAMMING OF ONE TIME PROGRAMMABLE MEMORY ARRAY FOR REDUCED TEST TIME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/03/2018
|
Application #:
|
15367888
|
Filing Dt:
|
12/02/2016
|
|
Publication #:
|
|
Pub Dt:
|
06/07/2018
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE COMPRISING A DIE SEAL INCLUDING LONG VIA LINES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/25/2019
|
Application #:
|
15370004
|
Filing Dt:
|
12/06/2016
|
|
Publication #:
|
|
Pub Dt:
|
06/07/2018
| | | | |
|
Title:
|
DIGITALLY CONTROLLED VARACTOR STRUCTURE FOR HIGH RESOLUTION DCO
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/12/2017
|
Application #:
|
15370404
|
Filing Dt:
|
12/06/2016
|
|
Title:
|
SELF-ALIGNED DEEP CONTACT FOR VERTICAL FET
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
15370555
|
Filing Dt:
|
12/06/2016
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Publication #:
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Pub Dt:
|
06/07/2018
| | | | |
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Title:
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GATE STRUCTURES WITH LOW RESISTANCE
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Patent #:
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|
Issue Dt:
|
12/03/2019
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Application #:
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15370585
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Filing Dt:
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12/06/2016
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Publication #:
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Pub Dt:
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06/07/2018
| | | | |
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Title:
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DUAL PHOTORESIST APPROACH TO LITHOGRAPHIC PATTERNING FOR PITCH REDUCTION
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Patent #:
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Issue Dt:
|
05/05/2020
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Application #:
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15370757
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Filing Dt:
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12/06/2016
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Publication #:
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Pub Dt:
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03/23/2017
| | | | |
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Title:
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Manufacturing Method for 3D Multipath Inductor
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Patent #:
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Issue Dt:
|
03/26/2019
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Application #:
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15372929
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Filing Dt:
|
12/08/2016
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Publication #:
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Pub Dt:
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06/14/2018
| | | | |
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Title:
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ACTIVE AND PASSIVE COMPONENTS WITH DEEP TRENCH ISOLATION STRUCTURES
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Patent #:
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Issue Dt:
|
01/23/2018
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Application #:
|
15373129
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Filing Dt:
|
12/08/2016
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|
Title:
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METHODS OF FORMING UNIFORM AND PITCH INDEPENDENT FIN RECESS
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Patent #:
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Issue Dt:
|
02/20/2018
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Application #:
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15373691
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Filing Dt:
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12/09/2016
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Title:
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METHODS OF FORMING A GATE CONTACT FOR A SEMICONDUCTOR DEVICE ABOVE THE ACTIVE REGION
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|
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Patent #:
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|
Issue Dt:
|
10/31/2017
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Application #:
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15373791
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Filing Dt:
|
12/09/2016
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|
Title:
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DIGITAL FREQUENCY MULTIPLIER TO GENERATE A LOCAL OSCILLATOR SIGNAL IN FDSOI TECHNOLOGY
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|
|
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Patent #:
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Issue Dt:
|
08/28/2018
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Application #:
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15373852
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Filing Dt:
|
12/09/2016
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Publication #:
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Pub Dt:
|
09/07/2017
| | | | |
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Title:
|
METHOD AND STRUCTURE FOR SRB ELASTIC RELAXATION
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Patent #:
|
NONE
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Issue Dt:
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|
Application #:
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15373898
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Filing Dt:
|
12/09/2016
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|
Publication #:
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Pub Dt:
|
06/14/2018
| | | | |
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Title:
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METHOD OF FORMING A SEMICONDUCTOR DEVICE INCLUDING AN INTEGRATED EFUSE HAVING DIELECTRIC LAYERS OF DIFFERENTIAL THICKNESS
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|
|
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Patent #:
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Issue Dt:
|
03/26/2019
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Application #:
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15374453
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Filing Dt:
|
12/09/2016
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|
Publication #:
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Pub Dt:
|
04/06/2017
| | | | |
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Title:
|
METHODS OF ERROR DETECTION IN FABRICATION PROCESSES
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|
|
|
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Patent #:
|
|
Issue Dt:
|
01/01/2019
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Application #:
|
15375623
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Filing Dt:
|
12/12/2016
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|
Publication #:
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Pub Dt:
|
06/14/2018
| | | | |
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Title:
|
PHOTOMASK BLANK INCLUDING A THIN CHROMIUM HARDMASK
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|
|
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Patent #:
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|
Issue Dt:
|
09/04/2018
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Application #:
|
15375890
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Filing Dt:
|
12/12/2016
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|
Publication #:
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Pub Dt:
|
04/13/2017
| | | | |
|
Title:
|
CONTACTING SOI SUBSTRATES
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|
|
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Patent #:
|
|
Issue Dt:
|
12/19/2017
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Application #:
|
15375924
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Filing Dt:
|
12/12/2016
|
|
Title:
|
THROUGH-SILICON VIA WITH IMPROVED SUBSTRATE CONTACT FOR REDUCED THROUGH-SILICON VIA (TSV) CAPACITANCE VARIABILITY
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/11/2019
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Application #:
|
15376831
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Filing Dt:
|
12/13/2016
|
|
Publication #:
|
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Pub Dt:
|
06/14/2018
| | | | |
|
Title:
|
AIR-GAP SPACERS FOR FIELD-EFFECT TRANSISTORS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/02/2018
|
Application #:
|
15377125
|
Filing Dt:
|
12/13/2016
|
|
Title:
|
METHOD OF MAKING SELF-ALIGNED CONTINUITY CUTS IN MANDREL AND NON-MANDREL METAL LINES
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|
|
|
|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
15377473
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Filing Dt:
|
12/13/2016
|
|
Publication #:
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Pub Dt:
|
03/30/2017
| | | | |
|
Title:
|
SELF-ALIGNED GATE TIE-DOWN CONTACTS WITH SELECTIVE ETCH STOP LINER
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|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
15377496
|
Filing Dt:
|
12/13/2016
|
|
Publication #:
|
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Pub Dt:
|
06/14/2018
| | | | |
|
Title:
|
FAN-OUT CIRCUIT PACKAGING WITH INTEGRATED LID
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/26/2017
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Application #:
|
15377503
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Filing Dt:
|
12/13/2016
|
|
Title:
|
ADVANCED METHOD FOR SCALED SRAM WITH FLEXIBLE ACTIVE PITCH
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/31/2018
|
Application #:
|
15377580
|
Filing Dt:
|
12/13/2016
|
|
Publication #:
|
|
Pub Dt:
|
06/14/2018
| | | | |
|
Title:
|
FULLY DEPLETED SILICON ON INSULATOR POWER AMPLIFIER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2018
|
Application #:
|
15377592
|
Filing Dt:
|
12/13/2016
|
|
Publication #:
|
|
Pub Dt:
|
06/14/2018
| | | | |
|
Title:
|
AIRGAPS TO ISOLATE METALLIZATION FEATURES
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/21/2019
|
Application #:
|
15378122
|
Filing Dt:
|
12/14/2016
|
|
Publication #:
|
|
Pub Dt:
|
06/14/2018
| | | | |
|
Title:
|
FORMING MULTI-SIZED THROUGH-SILICON-VIA (TSV) STRUCTURES
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/03/2017
|
Application #:
|
15378596
|
Filing Dt:
|
12/14/2016
|
|
Title:
|
METHOD OF CONTROLLING VFET CHANNEL LENGTH
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/24/2019
|
Application #:
|
15378990
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Filing Dt:
|
12/14/2016
|
|
Publication #:
|
|
Pub Dt:
|
06/14/2018
| | | | |
|
Title:
|
POLY GATE EXTENSION SOURCE TO BODY CONTACT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2018
|
Application #:
|
15379605
|
Filing Dt:
|
12/15/2016
|
|
Publication #:
|
|
Pub Dt:
|
06/21/2018
| | | | |
|
Title:
|
APPARATUS AND METHOD FOR FORMING INTERCONNECTION LINES HAVING VARIABLE PITCH AND VARIABLE WIDTHS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/07/2017
|
Application #:
|
15379645
|
Filing Dt:
|
12/15/2016
|
|
Title:
|
INTERCONNECTION CELLS HAVING VARIABLE WIDTH METAL LINES AND FULLY-SELF ALIGNED CONTINUITY CUTS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/19/2018
|
Application #:
|
15379707
|
Filing Dt:
|
12/15/2016
|
|
Publication #:
|
|
Pub Dt:
|
06/21/2018
| | | | |
|
Title:
|
INTERCONNECTION CELLS HAVING VARIABLE WIDTH METAL LINES AND FULLY-SELF ALIGNED VARIABLE LENGTH CONTINUITY CUTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/06/2018
|
Application #:
|
15379740
|
Filing Dt:
|
12/15/2016
|
|
Title:
|
INTERCONNECTION LINES HAVING VARIABLE WIDTHS AND PARTIALLY SELF-ALIGNED CONTINUITY CUTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/13/2018
|
Application #:
|
15381826
|
Filing Dt:
|
12/16/2016
|
|
Publication #:
|
|
Pub Dt:
|
06/21/2018
| | | | |
|
Title:
|
DEVICES AND METHODS OF COBALT FILL METALLIZATION
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/03/2018
|
Application #:
|
15383171
|
Filing Dt:
|
12/19/2016
|
|
Publication #:
|
|
Pub Dt:
|
06/21/2018
| | | | |
|
Title:
|
BIPOLAR JUNCTION TRANSISTORS WITH A COMBINED VERTICAL-LATERAL ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/13/2018
|
Application #:
|
15383461
|
Filing Dt:
|
12/19/2016
|
|
Title:
|
DIELECTRIC PRESERVATION IN A REPLACEMENT GATE PROCESS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/31/2017
|
Application #:
|
15384741
|
Filing Dt:
|
12/20/2016
|
|
Title:
|
INTEGRATED CIRCUIT STRUCTURE WITH REFRACTORY METAL ALIGNMENT MARKER AND METHODS OF FORMING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/17/2018
|
Application #:
|
15385068
|
Filing Dt:
|
12/20/2016
|
|
Publication #:
|
|
Pub Dt:
|
06/21/2018
| | | | |
|
Title:
|
WAFER BOND INTERCONNECT STRUCTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/24/2018
|
Application #:
|
15385949
|
Filing Dt:
|
12/21/2016
|
|
Title:
|
DEVICE STRUCTURES WITH MULTIPLE NITRIDED LAYERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2019
|
Application #:
|
15386097
|
Filing Dt:
|
12/21/2016
|
|
Publication #:
|
|
Pub Dt:
|
06/21/2018
| | | | |
|
Title:
|
INTEGRATED CIRCUIT CHIP WITH MOLDING COMPOUND HANDLER SUBSTRATE AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/28/2018
|
Application #:
|
15386507
|
Filing Dt:
|
12/21/2016
|
|
Publication #:
|
|
Pub Dt:
|
06/21/2018
| | | | |
|
Title:
|
WAFERS AND DEVICE STRUCTURES WITH BODY CONTACTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/23/2018
|
Application #:
|
15387120
|
Filing Dt:
|
12/21/2016
|
|
Publication #:
|
|
Pub Dt:
|
06/21/2018
| | | | |
|
Title:
|
INTEGRATED CIRCUIT STRUCTURE WITH CONTINUOUS METAL CRACK STOP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/27/2018
|
Application #:
|
15387933
|
Filing Dt:
|
12/22/2016
|
|
Title:
|
TALL SINGLE-FIN FIN-TYPE FIELD EFFECT TRANSISTOR STRUCTURES AND METHODS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/15/2018
|
Application #:
|
15387984
|
Filing Dt:
|
12/22/2016
|
|
Title:
|
LOW-K DIELECTRIC SPACER FOR A GATE CUT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/04/2018
|
Application #:
|
15388136
|
Filing Dt:
|
12/22/2016
|
|
Publication #:
|
|
Pub Dt:
|
06/28/2018
| | | | |
|
Title:
|
TEST STRUCTURE FOR TESTING VIA RESISTANCE AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/27/2018
|
Application #:
|
15388400
|
Filing Dt:
|
12/22/2016
|
|
Title:
|
MIDDLE OF THE LINE (MOL) CONTACTS WITH TWO-DIMENSIONAL SELF-ALIGNMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/10/2018
|
Application #:
|
15388530
|
Filing Dt:
|
12/22/2016
|
|
Publication #:
|
|
Pub Dt:
|
06/28/2018
| | | | |
|
Title:
|
CORROSION AND/OR ETCH PROTECTION LAYER FOR CONTACTS AND INTERCONNECT METALLIZATION INTEGRATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/10/2018
|
Application #:
|
15388772
|
Filing Dt:
|
12/22/2016
|
|
Title:
|
FULLY DEPLETED SILICON-ON-INSULATOR (FDSOI) TRANSISTOR DEVICE AND SELF-ALIGNED ACTIVE AREA IN FDSOI BULK EXPOSED REGIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/09/2019
|
Application #:
|
15389632
|
Filing Dt:
|
12/23/2016
|
|
Publication #:
|
|
Pub Dt:
|
06/28/2018
| | | | |
|
Title:
|
INTEGRATED CIRCUIT STRUCTURE INCLUDING POWER RAIL AND TAPPING WIRE WITH METHOD OF FORMING SAME
|
|
