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Reel/Frame:	049490/0001			Pages:	892
		Recorded:	11/29/2018
Conveyance:	SECURITY AGREEMENT

Total properties: 13706
Page 134 of 138
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Patent #:	9892971	Issue Dt:	02/13/2018	Application #:	15392042	Filing Dt:	12/28/2016
Title:	CRACK PREVENT AND STOP FOR THIN GLASS SUBSTRATES

Patent #:	10014409	Issue Dt:	07/03/2018	Application #:	15393400	Filing Dt:	12/29/2016
Publication #:	US20180190817	Pub Dt:	07/05/2018
Title:	METHOD AND STRUCTURE TO PROVIDE INTEGRATED LONG CHANNEL VERTICAL FINFET DEVICE

Patent #:	NONE	Issue Dt:		Application #:	15393488	Filing Dt:	12/29/2016
Publication #:	US20180190546	Pub Dt:	07/05/2018
Title:	METHOD FOR FORMING REPLACEMENT METAL GATE AND RELATED DEVICE

Patent #:	9824748	Issue Dt:	11/21/2017	Application #:	15395036	Filing Dt:	12/30/2016
Title:	SRAM BITCELL STRUCTURES FACILITATING BIASING OF PULL-UP TRANSISTORS

Patent #:	9935201	Issue Dt:	04/03/2018	Application #:	15396743	Filing Dt:	01/02/2017
Publication #:	US20170110583	Pub Dt:	04/20/2017
Title:	HIGH DOPED III-V SOURCE/DRAIN JUNCTIONS FOR FIELD EFFECT TRANSISTORS

Patent #:	9799661	Issue Dt:	10/24/2017	Application #:	15397004	Filing Dt:	01/03/2017
Title:	SRAM BITCELL STRUCTURES FACILITATING BIASING OF PULL-DOWN TRANSISTORS

Patent #:	9734897	Issue Dt:	08/15/2017	Application #:	15397021	Filing Dt:	01/03/2017
Title:	SRAM BITCELL STRUCTURES FACILITATING BIASING OF PASS GATE TRANSISTORS

Patent #:	10104148	Issue Dt:	10/16/2018	Application #:	15397028	Filing Dt:	01/03/2017
Publication #:	US20180191802	Pub Dt:	07/05/2018
Title:	NANOSECOND ACCURACY UNDER PRECISION TIME PROTOCOL FOR ETHERNET BY USING HIGH ACCURACY TIMESTAMP ASSIST DEVICE

Patent #:	NONE	Issue Dt:		Application #:	15397967	Filing Dt:	01/04/2017
Publication #:	US20180190792	Pub Dt:	07/05/2018
Title:	METHOD OF FORMING SEMICONDUCTOR STRUCTURE AND RESULTING STRUCTURE

Patent #:	9917103	Issue Dt:	03/13/2018	Application #:	15397978	Filing Dt:	01/04/2017
Title:	DIFFUSION BREAK FORMING AFTER SOURCE/DRAIN FORMING AND RELATED IC STRUCTURE

Patent #:	9799748	Issue Dt:	10/24/2017	Application #:	15398335	Filing Dt:	01/04/2017
Title:	METHOD OF FORMING INNER SPACERS ON A NANO-SHEET/WIRE DEVICE

Patent #:	10347622	Issue Dt:	07/09/2019	Application #:	15398946	Filing Dt:	01/05/2017
Publication #:	US20180190644	Pub Dt:	07/05/2018
Title:	SILICON-CONTROLLED RECTIFIERS HAVING A CATHODE COUPLED BY A CONTACT WITH A DIODE TRIGGER

Patent #:	10204861	Issue Dt:	02/12/2019	Application #:	15399200	Filing Dt:	01/05/2017
Publication #:	US20180190588	Pub Dt:	07/05/2018
Title:	Structure with Local Contact for Shorting a Gate Electrode to a Source/Drain Region

Patent #:	9893157	Issue Dt:	02/13/2018	Application #:	15401281	Filing Dt:	01/09/2017
Title:	STRUCTURES WITH CONTACT TRENCHES AND ISOLATION TRENCHES

Patent #:	10386714	Issue Dt:	08/20/2019	Application #:	15401299	Filing Dt:	01/09/2017
Publication #:	US20180196340	Pub Dt:	07/12/2018
Title:	CREATING KNOWLEDGE BASE FOR OPTICAL PROXIMITY CORRECTION TO REDUCE SUB-RESOLUTION ASSIST FEATURE PRINTING

Patent #:	10157927	Issue Dt:	12/18/2018	Application #:	15404754	Filing Dt:	01/12/2017
Publication #:	US20180197867	Pub Dt:	07/12/2018
Title:	SEMICONDUCTOR MEMORY DEVICES HAVING AN UNDERCUT SOURCE/DRAIN REGION

Patent #:	NONE	Issue Dt:		Application #:	15405026	Filing Dt:	01/12/2017
Publication #:	US20180197734	Pub Dt:	07/12/2018
Title:	BUFFER LAYER TO INHIBIT WORMHOLES IN SEMICONDUCTOR FABRICATION

Patent #:	10146132	Issue Dt:	12/04/2018	Application #:	15405448	Filing Dt:	01/13/2017
Publication #:	US20180203359	Pub Dt:	07/19/2018
Title:	MOBILE DISPENSE DEVICE FOR CHEMICALS USED IN MICRO-PROCESSING

Patent #:	10056481	Issue Dt:	08/21/2018	Application #:	15405495	Filing Dt:	01/13/2017
Publication #:	US20180204944	Pub Dt:	07/19/2018
Title:	SEMICONDUCTOR DEVICE STRUCTURE

Patent #:	9812324	Issue Dt:	11/07/2017	Application #:	15405789	Filing Dt:	01/13/2017
Title:	METHODS TO CONTROL FIN TIP PLACEMENT

Patent #:	10298345	Issue Dt:	05/21/2019	Application #:	15406350	Filing Dt:	01/13/2017
Publication #:	US20180205477	Pub Dt:	07/19/2018
Title:	CLOCK SYNCHRONIZATON USING CODEWORD MARKER

Patent #:	NONE	Issue Dt:		Application #:	15407407	Filing Dt:	01/17/2017
Publication #:	US20180204929	Pub Dt:	07/19/2018
Title:	METAL GATE FORMATION USING AN ENERGY REMOVAL FILM

Patent #:	10224330	Issue Dt:	03/05/2019	Application #:	15407960	Filing Dt:	01/17/2017
Publication #:	US20180204840	Pub Dt:	07/19/2018
Title:	SELF-ALIGNED JUNCTION STRUCTURES

Patent #:	10026824	Issue Dt:	07/17/2018	Application #:	15408540	Filing Dt:	01/18/2017
Publication #:	US20180204927	Pub Dt:	07/19/2018
Title:	AIR-GAP GATE SIDEWALL SPACER AND METHOD

Patent #:	10290574	Issue Dt:	05/14/2019	Application #:	15408883	Filing Dt:	01/18/2017
Publication #:	US20180204796	Pub Dt:	07/19/2018
Title:	EMBEDDED METAL-INSULATOR-METAL (MIM) DECOUPLING CAPACITOR IN MONOLITIC THREE-DIMENSIONAL (3D) INTEGRATED CIRCUIT (IC) STRUCTURE

Patent #:	9870942	Issue Dt:	01/16/2018	Application #:	15410032	Filing Dt:	01/19/2017
Title:	METHOD OF FORMING MANDREL AND NON-MANDREL METAL LINES HAVING VARIABLE WIDTHS

Patent #:	10026818	Issue Dt:	07/17/2018	Application #:	15410159	Filing Dt:	01/19/2017
Publication #:	US20180204920	Pub Dt:	07/19/2018
Title:	FIELD EFFECT TRANSISTOR STRUCTURE WITH RECESSED INTERLAYER DIELECTRIC AND METHOD

Patent #:	9871531	Issue Dt:	01/16/2018	Application #:	15412193	Filing Dt:	01/23/2017
Title:	NON-GEOMETRIC SCALING CURRENT STEERING DIGITAL TO ANALOG CONVERTER

Patent #:	9905476	Issue Dt:	02/27/2018	Application #:	15412598	Filing Dt:	01/23/2017
Publication #:	US20170133278	Pub Dt:	05/11/2017
Title:	ALTERNATIVE THRESHOLD VOLTAGE SCHEME VIA DIRECT METAL GATE PATTERNING FOR HIGH PERFORMANCE CMOS FinFETs

Patent #:	10109524	Issue Dt:	10/23/2018	Application #:	15413710	Filing Dt:	01/24/2017
Publication #:	US20180211873	Pub Dt:	07/26/2018
Title:	RECESSING OF LINER AND CONDUCTOR FOR VIA FORMATION

Patent #:	9911604	Issue Dt:	03/06/2018	Application #:	15413823	Filing Dt:	01/24/2017
Title:	SIDEWALL SPACER PATTERN FORMATION METHOD

Patent #:	9865543	Issue Dt:	01/09/2018	Application #:	15416152	Filing Dt:	01/26/2017
Title:	STRUCTURE AND METHOD FOR INHIBITING COBALT DIFFUSION

Patent #:	10153201	Issue Dt:	12/11/2018	Application #:	15417848	Filing Dt:	01/27/2017
Publication #:	US20170133265	Pub Dt:	05/11/2017
Title:	ADVANCED MOSFET CONTACT STRUCTURE TO REDUCE METAL-SEMICONDUCTOR INTERFACE RESISTANCE

Patent #:	10242946	Issue Dt:	03/26/2019	Application #:	15418001	Filing Dt:	01/27/2017
Publication #:	US20180218981	Pub Dt:	08/02/2018
Title:	CIRCUIT DESIGN HAVING ALIGNED POWER STAPLES

Patent #:	9971859	Issue Dt:	05/15/2018	Application #:	15418015	Filing Dt:	01/27/2017
Publication #:	US20170147726	Pub Dt:	05/25/2017
Title:	MODELING LOCALIZED TEMPERATURE CHANGES ON AN INTEGRATED CIRCUIT CHIP USING THERMAL POTENTIAL THEORY

Patent #:	10283505	Issue Dt:	05/07/2019	Application #:	15418996	Filing Dt:	01/30/2017
Publication #:	US20170141110	Pub Dt:	05/18/2017
Title:	DUMMY GATE USED AS INTERCONNECTION AND METHOD OF MAKING THE SAME

Patent #:	10008415	Issue Dt:	06/26/2018	Application #:	15419346	Filing Dt:	01/30/2017
Publication #:	US20170140994	Pub Dt:	05/18/2017
Title:	GATE STRUCTURE CUT AFTER FORMATION OF EPITAXIAL ACTIVE REGIONS

Patent #:	10103119	Issue Dt:	10/16/2018	Application #:	15420362	Filing Dt:	01/31/2017
Publication #:	US20180218991	Pub Dt:	08/02/2018
Title:	METHODS OF FORMING INTEGRATED CIRCUIT STRUCTURE FOR JOINING WAFERS AND RESULTING STRUCTURE

Patent #:	9728456	Issue Dt:	08/08/2017	Application #:	15420467	Filing Dt:	01/31/2017
Publication #:	US20170140984	Pub Dt:	05/18/2017
Title:	INTERCONNECT STRUCTURE INCLUDING MIDDLE OF LINE (MOL) METAL LAYER LOCAL INTERCONNECT ON ETCH STOP LAYER

Patent #:	10185312	Issue Dt:	01/22/2019	Application #:	15420749	Filing Dt:	01/31/2017
Publication #:	US20180217584	Pub Dt:	08/02/2018
Title:	INSITU TOOL HEALTH AND RECIPE QUALITY MONITORING ON A CDSEM

Patent #:	10002797	Issue Dt:	06/19/2018	Application #:	15420794	Filing Dt:	01/31/2017
Title:	CHIP INTEGRATION INCLUDING VERTICAL FIELD-EFFECT TRANSISTORS AND BIPOLAR JUNCTION TRANSISTORS

Patent #:	9893063	Issue Dt:	02/13/2018	Application #:	15420967	Filing Dt:	01/31/2017
Publication #:	US20170141109	Pub Dt:	05/18/2017
Title:	SPECIAL CONSTRUCT FOR CONTINUOUS NON-UNIFORM ACTIVE REGION FINFET STANDARD CELLS

Patent #:	10332834	Issue Dt:	06/25/2019	Application #:	15421698	Filing Dt:	02/01/2017
Publication #:	US20170141031	Pub Dt:	05/18/2017
Title:	SEMICONDUCTOR FUSES WITH NANOWIRE FUSE LINKS AND FABRICATION METHODS THEREOF

Patent #:	10170309	Issue Dt:	01/01/2019	Application #:	15422689	Filing Dt:	02/15/2017
Publication #:	US20180233361	Pub Dt:	08/16/2018
Title:	DUMMY PATTERN ADDITION TO IMPROVE CD UNIFORMITY

Patent #:	9997403	Issue Dt:	06/12/2018	Application #:	15422923	Filing Dt:	02/02/2017
Publication #:	US20170243784	Pub Dt:	08/24/2017
Title:	METAL LAYER TIP TO TIP SHORT

Patent #:	10083952	Issue Dt:	09/25/2018	Application #:	15423006	Filing Dt:	02/02/2017
Publication #:	US20180219006	Pub Dt:	08/02/2018
Title:	DIODE-TRIGGERED SCHOTTKY SILICON-CONTROLLED RECTIFIER FOR FIN-FET ELECTROSTATIC DISCHARGE CONTROL

Patent #:	10068804	Issue Dt:	09/04/2018	Application #:	15423326	Filing Dt:	02/02/2017
Publication #:	US20180218947	Pub Dt:	08/02/2018
Title:	METHODS, APPARATUS AND SYSTEM FOR PROVIDING ADJUSTABLE FIN HEIGHT FOR A FINFET DEVICE

Patent #:	9761662	Issue Dt:	09/12/2017	Application #:	15423647	Filing Dt:	02/03/2017
Title:	ACTIVE AREA SHAPES REDUCING DEVICE SIZE

Patent #:	9911823	Issue Dt:	03/06/2018	Application #:	15423945	Filing Dt:	02/03/2017
Publication #:	US20170148895	Pub Dt:	05/25/2017
Title:	POC PROCESS FLOW FOR CONFORMAL RECESS FILL

Patent #:	10468149	Issue Dt:	11/05/2019	Application #:	15424200	Filing Dt:	02/03/2017
Publication #:	US20180226166	Pub Dt:	08/09/2018
Title:	EXTREME ULTRAVIOLET MIRRORS AND MASKS WITH IMPROVED REFLECTIVITY

Patent #:	10170617	Issue Dt:	01/01/2019	Application #:	15424379	Filing Dt:	02/03/2017
Publication #:	US20180226505	Pub Dt:	08/09/2018
Title:	VERTICAL TRANSPORT FIELD EFFECT TRANSISTORS

Patent #:	9947532	Issue Dt:	04/17/2018	Application #:	15425338	Filing Dt:	02/06/2017
Publication #:	US20170148661	Pub Dt:	05/25/2017
Title:	FORMING ZIG-ZAG TRENCH STRUCTURE TO PREVENT ASPECT RATIO TRAPPING DEFECT ESCAPE

Patent #:	9831248	Issue Dt:	11/28/2017	Application #:	15425366	Filing Dt:	02/06/2017
Title:	EMBEDDED DRAM CELLS HAVING CAPACITORS WITHIN TRENCH SILICIDE TRENCHES OF A SEMICONDUCTOR STRUCTURE

Patent #:	NONE	Issue Dt:		Application #:	15425384	Filing Dt:	02/06/2017
Publication #:	US20180226292	Pub Dt:	08/09/2018
Title:	TRENCH ISOLATION FORMATION FROM THE SUBSTRATE BACK SIDE USING LAYER TRANSFER

Patent #:	10181420	Issue Dt:	01/15/2019	Application #:	15425478	Filing Dt:	02/06/2017
Publication #:	US20180226294	Pub Dt:	08/09/2018
Title:	DEVICES WITH CHAMFER-LESS VIAS MULTI-PATTERNING AND METHODS FOR FORMING CHAMFER-LESS VIAS

Patent #:	9935003	Issue Dt:	04/03/2018	Application #:	15426573	Filing Dt:	02/07/2017
Publication #:	US20170148668	Pub Dt:	05/25/2017
Title:	HDP FILL WITH REDUCED VOID FORMATION AND SPACER DAMAGE

Patent #:	10079300	Issue Dt:	09/18/2018	Application #:	15426728	Filing Dt:	02/07/2017
Publication #:	US20170148919	Pub Dt:	05/25/2017
Title:	SEMICONDUCTOR CIRCUIT ELEMENT

Patent #:	10964687	Issue Dt:	03/30/2021	Application #:	15427128	Filing Dt:	02/08/2017
Publication #:	US20180226394	Pub Dt:	08/09/2018
Title:	FINFET ESD DEVICE WITH SCHOTTKY DIODE

Patent #:	10002835	Issue Dt:	06/19/2018	Application #:	15427156	Filing Dt:	02/08/2017
Publication #:	US20170148737	Pub Dt:	05/25/2017
Title:	STRUCTURE FOR ESTABLISHING INTERCONNECTS IN PACKAGES USING THIN INTERPOSERS

Patent #:	10964796	Issue Dt:	03/30/2021	Application #:	15427182	Filing Dt:	02/08/2017
Publication #:	US20180226347	Pub Dt:	08/09/2018
Title:	Heterojunction Bipolar Transistors With Stress Material For Improved Mobility

Patent #:	10163900	Issue Dt:	12/25/2018	Application #:	15427403	Filing Dt:	02/08/2017
Publication #:	US20180226402	Pub Dt:	08/09/2018
Title:	INTEGRATION OF VERTICAL FIELD-EFFECT TRANSISTORS AND SADDLE FIN-TYPE FIELD EFFECT TRANSISTORS

Patent #:	9947793	Issue Dt:	04/17/2018	Application #:	15427594	Filing Dt:	02/08/2017
Title:	VERTICAL PILLAR-TYPE FIELD EFFECT TRANSISTOR AND METHOD

Patent #:	10424657	Issue Dt:	09/24/2019	Application #:	15428312	Filing Dt:	02/09/2017
Publication #:	US20170154977	Pub Dt:	06/01/2017
Title:	TRI-GATE FINFET DEVICE

Patent #:	10360334	Issue Dt:	07/23/2019	Application #:	15428449	Filing Dt:	02/09/2017
Publication #:	US20180225406	Pub Dt:	08/09/2018
Title:	CONTEXT AWARE PROCESSING TO RESOLVE STRONG SPACING EFFECTS DUE TO STRAIN RELAXATION IN STANDARD CELL LIBRARY

Patent #:	10600843	Issue Dt:	03/24/2020	Application #:	15428509	Filing Dt:	02/09/2017
Publication #:	US20170148850	Pub Dt:	05/25/2017
Title:	MEMORY DEVICE STRUCTURE

Patent #:	9899319	Issue Dt:	02/20/2018	Application #:	15428604	Filing Dt:	02/09/2017
Publication #:	US20170154846	Pub Dt:	06/01/2017
Title:	RAISED E-FUSE

Patent #:	10020307	Issue Dt:	07/10/2018	Application #:	15429502	Filing Dt:	02/10/2017
Title:	INTEGRATED CIRCUIT STRUCTURE INCLUDING LATERALLY RECESSED SOURCE/DRAIN EPITAXIAL REGION AND METHOD OF FORMING SAME

Patent #:	10199265	Issue Dt:	02/05/2019	Application #:	15430039	Filing Dt:	02/10/2017
Publication #:	US20180233404	Pub Dt:	08/16/2018
Title:	VARIABLE SPACE MANDREL CUT FOR SELF ALIGNED DOUBLE PATTERNING

Patent #:	9953727	Issue Dt:	04/24/2018	Application #:	15430170	Filing Dt:	02/10/2017
Title:	CIRCUIT AND METHOD FOR DETECTING TIME DEPENDENT DIELECTRIC BREAKDOWN (TDDB) SHORTS AND SIGNAL-MARGIN TESTING

Patent #:	11557420	Issue Dt:	01/17/2023	Application #:	15430596	Filing Dt:	02/13/2017
Publication #:	US20170154722	Pub Dt:	06/01/2017
Title:	COUPLING INDUCTORS IN AN IC DEVICE USING INTERCONNECTING ELEMENTS WITH SOLDER CAPS AND RESULTING DEVICES

Patent #:	10056469	Issue Dt:	08/21/2018	Application #:	15430647	Filing Dt:	02/13/2017
Publication #:	US20180233579	Pub Dt:	08/16/2018
Title:	GATE CUT INTEGRATION AND RELATED DEVICE

Patent #:	9812453	Issue Dt:	11/07/2017	Application #:	15431334	Filing Dt:	02/13/2017
Title:	SELF-ALIGNED SACRIFICIAL EPITAXIAL CAPPING FOR TRENCH SILICIDE

Patent #:	9865570	Issue Dt:	01/09/2018	Application #:	15431915	Filing Dt:	02/14/2017
Title:	INTEGRATED CIRCUIT PACKAGE WITH THERMALLY CONDUCTIVE PILLAR

Patent #:	10128352	Issue Dt:	11/13/2018	Application #:	15432372	Filing Dt:	02/14/2017
Publication #:	US20170162438	Pub Dt:	06/08/2017
Title:	GATE TIE-DOWN ENABLEMENT WITH INNER SPACER

Patent #:	NONE	Issue Dt:		Application #:	15432710	Filing Dt:	02/14/2017
Publication #:	US20180233580	Pub Dt:	08/16/2018
Title:	SEMICONDUCTOR STRUCTURE WITH GATE HEIGHT SCALING

Patent #:	10573534	Issue Dt:	02/25/2020	Application #:	15433099	Filing Dt:	02/15/2017
Publication #:	US20170236721	Pub Dt:	08/17/2017
Title:	RAPID HEATING PROCESS IN THE PRODUCTION OF SEMICONDUCTOR COMPONENTS

Patent #:	10658494	Issue Dt:	05/19/2020	Application #:	15433141	Filing Dt:	02/15/2017
Publication #:	US20180233583	Pub Dt:	08/16/2018
Title:	TRANSISTORS AND METHODS OF FORMING TRANSISTORS USING VERTICAL NANOWIRES

Patent #:	10249535	Issue Dt:	04/02/2019	Application #:	15433188	Filing Dt:	02/15/2017
Publication #:	US20180233412	Pub Dt:	08/16/2018
Title:	FORMING TS CUT FOR ZERO OR NEGATIVE TS EXTENSION AND RESULTING DEVICE

Patent #:	NONE	Issue Dt:		Application #:	15433330	Filing Dt:	02/15/2017
Publication #:	US20170162688	Pub Dt:	06/08/2017
Title:	METAL GATE STRUCTURE AND METHOD OF FORMATION

Patent #:	9847390	Issue Dt:	12/19/2017	Application #:	15434205	Filing Dt:	02/16/2017
Title:	SELF-ALIGNED WRAP-AROUND CONTACTS FOR NANOSHEET DEVICES

Patent #:	9935018	Issue Dt:	04/03/2018	Application #:	15436281	Filing Dt:	02/17/2017
Title:	METHODS OF FORMING VERTICAL TRANSISTOR DEVICES WITH DIFFERENT EFFECTIVE GATE LENGTHS

Patent #:	10290698	Issue Dt:	05/14/2019	Application #:	15437057	Filing Dt:	02/20/2017
Publication #:	US20170162647	Pub Dt:	06/08/2017
Title:	SUBSTRATE RESISTOR WITH OVERLYING GATE STRUCTURE

Patent #:	9805972	Issue Dt:	10/31/2017	Application #:	15437065	Filing Dt:	02/20/2017
Title:	SKIP VIA STRUCTURES

Patent #:	10026687	Issue Dt:	07/17/2018	Application #:	15437100	Filing Dt:	02/20/2017
Title:	METAL INTERCONNECTS FOR SUPER (SKIP) VIA INTEGRATION

Patent #:	9947545	Issue Dt:	04/17/2018	Application #:	15437837	Filing Dt:	02/21/2017
Publication #:	US20170243748	Pub Dt:	08/24/2017
Title:	METHODS FOR GATE FORMATION IN CIRCUIT STRUCTURES

Patent #:	9929148	Issue Dt:	03/27/2018	Application #:	15439444	Filing Dt:	02/22/2017
Title:	SEMICONDUCTOR DEVICE INCLUDING BURIED CAPACITIVE STRUCTURES AND A METHOD OF FORMING THE SAME

Patent #:	9905472	Issue Dt:	02/27/2018	Application #:	15440072	Filing Dt:	02/23/2017
Title:	SILICON NITRIDE CESL REMOVAL WITHOUT GATE CAP HEIGHT LOSS AND RESULTING DEVICE

Patent #:	9806221	Issue Dt:	10/31/2017	Application #:	15441345	Filing Dt:	02/24/2017
Publication #:	US20170162743	Pub Dt:	06/08/2017
Title:	Germanium Photodetector with SOI Doping Source

Patent #:	9991131	Issue Dt:	06/05/2018	Application #:	15443335	Filing Dt:	02/27/2017
Title:	DUAL MANDRELS TO ENABLE VARIABLE FIN PITCH

Patent #:	9911825	Issue Dt:	03/06/2018	Application #:	15443522	Filing Dt:	02/27/2017
Publication #:	US20170170293	Pub Dt:	06/15/2017
Title:	INTEGRATED CIRCUITS WITH SPACER CHAMFERING AND METHODS OF SPACER CHAMFERING

Patent #:	9899259	Issue Dt:	02/20/2018	Application #:	15443523	Filing Dt:	02/27/2017
Publication #:	US20170170070	Pub Dt:	06/15/2017
Title:	GATE TIE-DOWN ENABLEMENT WITH INNER SPACER

Patent #:	9935168	Issue Dt:	04/03/2018	Application #:	15445481	Filing Dt:	02/28/2017
Publication #:	US20170170266	Pub Dt:	06/15/2017
Title:	GATE CONTACT WITH VERTICAL ISOLATION FROM SOURCE-DRAIN

Patent #:	9881669	Issue Dt:	01/30/2018	Application #:	15446091	Filing Dt:	03/01/2017
Title:	WORDLINE DRIVER WITH INTEGRATED VOLTAGE LEVEL SHIFT FUNCTION

Patent #:	9831317	Issue Dt:	11/28/2017	Application #:	15447639	Filing Dt:	03/02/2017
Title:	BURIED CONTACT STRUCTURES FOR A VERTICAL FIELD-EFFECT TRANSISTOR

Patent #:	9899257	Issue Dt:	02/20/2018	Application #:	15448873	Filing Dt:	03/03/2017
Title:	ETCH STOP LINER FOR CONTACT PUNCH THROUGH MITIGATION IN SOI SUBSTRATE

Patent #:	9911474	Issue Dt:	03/06/2018	Application #:	15451470	Filing Dt:	03/07/2017
Title:	FEEDBACK CIRCUIT AT WORDLINE ENDS

Patent #:	10249726	Issue Dt:	04/02/2019	Application #:	15451565	Filing Dt:	03/07/2017
Publication #:	US20170179246	Pub Dt:	06/22/2017
Title:	METHODS OF FORMING A PROTECTION LAYER ON A SEMICONDUCTOR DEVICE AND THE RESULTING DEVICE

Patent #:	9865681	Issue Dt:	01/09/2018	Application #:	15453170	Filing Dt:	03/08/2017
Title:	NANOWIRE TRANSISTORS HAVING MULTIPLE THRESHOLD VOLTAGES

Patent #:	9923082	Issue Dt:	03/20/2018	Application #:	15453939	Filing Dt:	03/09/2017
Publication #:	US20170179257	Pub Dt:	06/22/2017
Title:	JUNCTION BUTTING STRUCTURE USING NONUNIFORM TRENCH SHAPE

100

Patent #:	10020386	Issue Dt:	07/10/2018	Application #:	15454511	Filing Dt:	03/09/2017
Title:	HIGH-VOLTAGE AND ANALOG BIPOLAR DEVICES

Assignor

GLOBALFOUNDRIES INC.

Exec Dt:

11/27/2018

Assignee

WILMINGTON TRUST, NATIONAL ASSOCIATION

1100 NORTH MARKET STREET

WILMINGTON, DELAWARE 19801

Correspondence name and address
	CT CORPORATION
	4400 EASTON COMMONS WAY
	SUITE 125
	COLUMBUS, OH 43219

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