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Patent Assignment Details
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Reel/Frame:049490/0001   Pages: 892
Recorded: 11/29/2018
Conveyance: SECURITY AGREEMENT
Total properties: 13706
Page 137 of 138
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138
1
Patent #:
10177237
Issue Dt:
01/08/2019
Application #:
15782380
Filing Dt:
10/12/2017
Publication #:
US20180053831
Pub Dt:
02/22/2018
Title:
ETCH STOP FOR AIRGAP PROTECTION
2
Patent #:
10679937
Issue Dt:
06/09/2020
Application #:
15785665
Filing Dt:
10/17/2017
Publication #:
US20180040555
Pub Dt:
02/08/2018
Title:
DEVICES AND METHODS OF FORMING LOW RESISTIVITY NOBLE METAL INTERCONNECT
3
Patent #:
10056377
Issue Dt:
08/21/2018
Application #:
15786164
Filing Dt:
10/17/2017
Publication #:
US20180145073
Pub Dt:
05/24/2018
Title:
METAL LAYER ROUTING LEVEL FOR VERTICAL FET SRAM AND LOGIC CELL SCALING
4
Patent #:
10224276
Issue Dt:
03/05/2019
Application #:
15787146
Filing Dt:
10/18/2017
Publication #:
US20180040556
Pub Dt:
02/08/2018
Title:
INTEGRATED CIRCUIT INCLUDING WIRE STRUCTURE, RELATED METHOD AND DESIGN STRUCTURE
5
Patent #:
10026494
Issue Dt:
07/17/2018
Application #:
15790543
Filing Dt:
10/23/2017
Publication #:
US20180075921
Pub Dt:
03/15/2018
Title:
WORD LINE VOLTAGE GENERATOR FOR CALCULATING OPTIMUM WORD LINE VOLTAGE LEVEL FOR PROGRAMMABLE MEMORY ARRAY
6
Patent #:
10460067
Issue Dt:
10/29/2019
Application #:
15791210
Filing Dt:
10/23/2017
Publication #:
US20190303525
Pub Dt:
10/03/2019
Title:
METHOD OF PATTERNING TARGET LAYER
7
Patent #:
10096557
Issue Dt:
10/09/2018
Application #:
15791568
Filing Dt:
10/24/2017
Publication #:
US20180061777
Pub Dt:
03/01/2018
Title:
TILED-STRESS-ALLEVIATING PAD STRUCTURE
8
Patent #:
10170574
Issue Dt:
01/01/2019
Application #:
15792206
Filing Dt:
10/24/2017
Publication #:
US20180047824
Pub Dt:
02/15/2018
Title:
HYBRID SOURCE AND DRAIN CONTACT FORMATION USING METAL LINER AND METAL INSULATOR SEMICONDUCTOR CONTACTS
9
Patent #:
9953882
Issue Dt:
04/24/2018
Application #:
15792281
Filing Dt:
10/24/2017
Publication #:
US20180090387
Pub Dt:
03/29/2018
Title:
METHOD FOR FORMING NANOWIRES INCLUDING MULTIPLE INTEGRATED DEVICES WITH ALTERNATE CHANNEL MATERIALS
10
Patent #:
10483172
Issue Dt:
11/19/2019
Application #:
15792357
Filing Dt:
10/24/2017
Publication #:
US20180047641
Pub Dt:
02/15/2018
Title:
TRANSISTOR DEVICE STRUCTURES WITH RETROGRADE WELLS IN CMOS APPLICATIONS
11
Patent #:
10177157
Issue Dt:
01/08/2019
Application #:
15792527
Filing Dt:
10/24/2017
Publication #:
US20180047734
Pub Dt:
02/15/2018
Title:
TRANSISTOR STRUCTURE HAVING MULTIPLE N-TYPE AND/OR P-TYPE ELONGATED REGIONS INTERSECTING UNDER COMMON GATE
12
Patent #:
10224418
Issue Dt:
03/05/2019
Application #:
15793419
Filing Dt:
10/25/2017
Publication #:
US20180061969
Pub Dt:
03/01/2018
Title:
INTEGRATED CIRCUIT FABRICATION WITH BORON ETCH-STOP LAYER
13
Patent #:
10141446
Issue Dt:
11/27/2018
Application #:
15793545
Filing Dt:
10/25/2017
Publication #:
US20180061993
Pub Dt:
03/01/2018
Title:
FORMATION OF BOTTOM JUNCTION IN VERTICAL FET DEVICES
14
Patent #:
10026740
Issue Dt:
07/17/2018
Application #:
15797533
Filing Dt:
10/30/2017
Title:
DRAM STRUCTURE WITH A SINGLE DIFFUSION BREAK
15
Patent #:
10121893
Issue Dt:
11/06/2018
Application #:
15797634
Filing Dt:
10/30/2017
Publication #:
US20180061976
Pub Dt:
03/01/2018
Title:
INTEGRATED CIRCUIT STRUCTURE WITHOUT GATE CONTACT AND METHOD OF FORMING SAME
16
Patent #:
10026753
Issue Dt:
07/17/2018
Application #:
15799243
Filing Dt:
10/31/2017
Publication #:
US20180053789
Pub Dt:
02/22/2018
Title:
METHOD FOR COMPENSATING FOR TEMPERATURE EFFECTS IN SEMICONDUCTOR DEVICE STRUCTURES USING A DIODE STRUCTURE AND A TUNABLE RESISTOR
17
Patent #:
10461067
Issue Dt:
10/29/2019
Application #:
15799600
Filing Dt:
10/31/2017
Publication #:
US20180068993
Pub Dt:
03/08/2018
Title:
THERMALLY ENHANCED PACKAGE TO REDUCE THERMAL INTERACTION BETWEEN DIES
18
Patent #:
10083858
Issue Dt:
09/25/2018
Application #:
15800551
Filing Dt:
11/01/2017
Publication #:
US20180174896
Pub Dt:
06/21/2018
Title:
INTERCONNECTION LINES HAVING VARIABLE WIDTHS AND PARTIALLY SELF-ALIGNED CONTINUITY CUTS
19
Patent #:
10236291
Issue Dt:
03/19/2019
Application #:
15801023
Filing Dt:
11/01/2017
Publication #:
US20180061832
Pub Dt:
03/01/2018
Title:
METHODS, APPARATUS AND SYSTEM FOR STI RECESS CONTROL FOR HIGHLY SCALED FINFET DEVICES
20
Patent #:
10224207
Issue Dt:
03/05/2019
Application #:
15801458
Filing Dt:
11/02/2017
Publication #:
US20180068858
Pub Dt:
03/08/2018
Title:
FORMING A CONTACT FOR A TALL FIN TRANSISTOR
21
Patent #:
10446484
Issue Dt:
10/15/2019
Application #:
15801501
Filing Dt:
11/02/2017
Publication #:
US20180166381
Pub Dt:
06/14/2018
Title:
THROUGH-SILICON VIA WITH IMPROVED SUBSTRATE CONTACT FOR REDUCED THROUGH-SILICON VIA (TSV) CAPACITANCE VARIABILITY
22
Patent #:
10121884
Issue Dt:
11/06/2018
Application #:
15806532
Filing Dt:
11/08/2017
Publication #:
US20180069106
Pub Dt:
03/08/2018
Title:
FABRICATION OF INTEGRATED CIRCUIT STRUCTURES FOR BIPOLOR TRANSISTORS
23
Patent #:
10224236
Issue Dt:
03/05/2019
Application #:
15813399
Filing Dt:
11/15/2017
Publication #:
US20180076082
Pub Dt:
03/15/2018
Title:
FORMING AIR GAP
24
Patent #:
10229987
Issue Dt:
03/12/2019
Application #:
15815857
Filing Dt:
11/17/2017
Publication #:
US20180076299
Pub Dt:
03/15/2018
Title:
EPITAXIAL AND SILICIDE LAYER FORMATION AT TOP AND BOTTOM SURFACES OF SEMICONDUCTOR FINS
25
Patent #:
10192887
Issue Dt:
01/29/2019
Application #:
15817362
Filing Dt:
11/20/2017
Publication #:
US20180090516
Pub Dt:
03/29/2018
Title:
METHOD TO IMPROVE CRYSTALLINE REGROWTH
26
Patent #:
10283407
Issue Dt:
05/07/2019
Application #:
15817554
Filing Dt:
11/20/2017
Publication #:
US20180090374
Pub Dt:
03/29/2018
Title:
TWO-DIMENSIONAL SELF-ALIGNED SUPER VIA INTEGRATION ON SELF-ALIGNED GATE CONTACT
27
Patent #:
10403574
Issue Dt:
09/03/2019
Application #:
15820602
Filing Dt:
11/22/2017
Publication #:
US20180096933
Pub Dt:
04/05/2018
Title:
METHOD TO REDUCE RESISTANCE FOR A COPPER (CU) INTERCONNECT LANDING ON MULTILAYERED METAL CONTACTS, AND SEMICONDUCTOR STRUCTURES FORMED THEREFROM
28
Patent #:
10483377
Issue Dt:
11/19/2019
Application #:
15821091
Filing Dt:
11/22/2017
Publication #:
US20180097089
Pub Dt:
04/05/2018
Title:
DEVICES AND METHODS OF FORMING UNMERGED EPITAXY FOR FINFET DEVICE
29
Patent #:
10361311
Issue Dt:
07/23/2019
Application #:
15825409
Filing Dt:
11/29/2017
Publication #:
US20180090327
Pub Dt:
03/29/2018
Title:
SEMICONDUCTOR STRUCTURE INCLUDING LOW-K SPACER MATERIAL
30
Patent #:
10283487
Issue Dt:
05/07/2019
Application #:
15826799
Filing Dt:
11/30/2017
Publication #:
US20180233488
Pub Dt:
08/16/2018
Title:
Methods of Forming Integrated Circuit Package with Thermally Conductive Pillar
31
Patent #:
10707167
Issue Dt:
07/07/2020
Application #:
15826939
Filing Dt:
11/30/2017
Publication #:
US20180090447
Pub Dt:
03/29/2018
Title:
CONTACTS TO SEMICONDUCTOR SUBSTRATE AND METHODS OF FORMING SAME
32
Patent #:
10047431
Issue Dt:
08/14/2018
Application #:
15828624
Filing Dt:
12/01/2017
Publication #:
US20180087145
Pub Dt:
03/29/2018
Title:
DIRECTED SURFACE FUNCTIONALIZATION ON SELECTED SURFACE AREAS OF TOPOGRAPHICAL FEATURES WITH NANOMETER RESOLUTION
33
Patent #:
10249633
Issue Dt:
04/02/2019
Application #:
15831833
Filing Dt:
12/05/2017
Publication #:
US20180108668
Pub Dt:
04/19/2018
Title:
FLASH MEMORY DEVICE
34
Patent #:
10170544
Issue Dt:
01/01/2019
Application #:
15833285
Filing Dt:
12/06/2017
Publication #:
US20180102409
Pub Dt:
04/12/2018
Title:
INTEGRATED CIRCUIT PRODUCTS THAT INCLUDE FINFET DEVICES AND A PROTECTION LAYER FORMED ON AN ISOLATION REGION
35
Patent #:
9966310
Issue Dt:
05/08/2018
Application #:
15837279
Filing Dt:
12/11/2017
Publication #:
US20180108566
Pub Dt:
04/19/2018
Title:
INTEGRATED CIRCUIT STRUCTURE HAVING DEEP TRENCH CAPACITOR AND THROUGH-SILICON VIA AND METHOD OF FORMING SAME
36
Patent #:
NONE
Issue Dt:
Application #:
15839243
Filing Dt:
12/12/2017
Publication #:
US20180130712
Pub Dt:
05/10/2018
Title:
SPACER DEFINED FIN GROWTH AND DIFFERENTIAL FIN WIDTH
37
Patent #:
10651293
Issue Dt:
05/12/2020
Application #:
15840835
Filing Dt:
12/13/2017
Publication #:
US20180114850
Pub Dt:
04/26/2018
Title:
METHODS OF SIMULTANEOUSLY FORMING BOTTOM AND TOP SPACERS ON A VERTICAL TRANSISTOR DEVICE
38
Patent #:
NONE
Issue Dt:
Application #:
15843649
Filing Dt:
12/15/2017
Publication #:
US20180130656
Pub Dt:
05/10/2018
Title:
FORMING DEFECT-FREE RELAXED SiGe FINS
39
Patent #:
10014298
Issue Dt:
07/03/2018
Application #:
15844840
Filing Dt:
12/18/2017
Title:
METHOD OF FORMING FIELD EFFECT TRANSISTORS WITH REPLACEMENT METAL GATES AND CONTACTS AND RESULTING STRUCTURE
40
Patent #:
NONE
Issue Dt:
Application #:
15845313
Filing Dt:
12/18/2017
Publication #:
US20180172609
Pub Dt:
06/21/2018
Title:
METHOD AND SYSTEM FOR NON-DESTRUCTIVE METROLOGY OF THIN LAYERS
41
Patent #:
10229855
Issue Dt:
03/12/2019
Application #:
15846365
Filing Dt:
12/19/2017
Publication #:
US20180122702
Pub Dt:
05/03/2018
Title:
METHODS OF FORMING TRANSISTOR DEVICES WITH DIFFERENT THRESHOLD VOLTAGES AND THE RESULTING DEVICES
42
Patent #:
10304747
Issue Dt:
05/28/2019
Application #:
15847028
Filing Dt:
12/19/2017
Publication #:
US20180122711
Pub Dt:
05/03/2018
Title:
DUAL LINER SILICIDE
43
Patent #:
10985260
Issue Dt:
04/20/2021
Application #:
15847186
Filing Dt:
12/19/2017
Publication #:
US20180108749
Pub Dt:
04/19/2018
Title:
TRENCH SILICIDE CONTACTS WITH HIGH SELECTIVITY PROCESS
44
Patent #:
10374029
Issue Dt:
08/06/2019
Application #:
15848324
Filing Dt:
12/20/2017
Publication #:
US20180122891
Pub Dt:
05/03/2018
Title:
SEMICONDUCTOR DEVICE RESISTOR STRUCTURE
45
Patent #:
10163677
Issue Dt:
12/25/2018
Application #:
15848371
Filing Dt:
12/20/2017
Publication #:
US20180138079
Pub Dt:
05/17/2018
Title:
ELECTRICALLY INSULATED FIN STRUCTURE(S) WITH ALTERNATIVE CHANNEL MATERIALS AND FABRICATION METHODS
46
Patent #:
10236343
Issue Dt:
03/19/2019
Application #:
15848591
Filing Dt:
12/20/2017
Publication #:
US20180190768
Pub Dt:
07/05/2018
Title:
STRAIN RETENTION SEMICONDUCTOR MEMBER FOR CHANNEL SIGE LAYER OF PFET
47
Patent #:
10283408
Issue Dt:
05/07/2019
Application #:
15851774
Filing Dt:
12/22/2017
Publication #:
US20180182668
Pub Dt:
06/28/2018
Title:
MIDDLE OF THE LINE (MOL) CONTACTS WITH TWO-DIMENSIONAL SELF-ALIGNMENT
48
Patent #:
10580689
Issue Dt:
03/03/2020
Application #:
15856525
Filing Dt:
12/28/2017
Publication #:
US20180122689
Pub Dt:
05/03/2018
Title:
CONTACT MODULE FOR OPTIMIZING EMITTER AND CONTACT RESISTANCE
49
Patent #:
10199378
Issue Dt:
02/05/2019
Application #:
15857202
Filing Dt:
12/28/2017
Publication #:
US20180122804
Pub Dt:
05/03/2018
Title:
SPECIAL CONSTRUCT FOR CONTINUOUS NON-UNIFORM ACTIVE REGION FINFET STANDARD CELLS
50
Patent #:
10304763
Issue Dt:
05/28/2019
Application #:
15858673
Filing Dt:
12/29/2017
Publication #:
US20180122730
Pub Dt:
05/03/2018
Title:
PRODUCING WAFER LEVEL PACKAGING USING LEADFRAME STRIP AND RELATED DEVICE
51
Patent #:
10325808
Issue Dt:
06/18/2019
Application #:
15858691
Filing Dt:
12/29/2017
Publication #:
US20180182671
Pub Dt:
06/28/2018
Title:
CRACK PREVENT AND STOP FOR THIN GLASS SUBSTRATES
52
Patent #:
10411010
Issue Dt:
09/10/2019
Application #:
15862064
Filing Dt:
01/04/2018
Publication #:
US20180182757
Pub Dt:
06/28/2018
Title:
TALL SINGLE-FIN FIN-TYPE FIELD EFFECT TRANSISTOR STRUCTURES AND METHODS
53
Patent #:
10379191
Issue Dt:
08/13/2019
Application #:
15868248
Filing Dt:
01/11/2018
Publication #:
US20180136304
Pub Dt:
05/17/2018
Title:
APPARATUS AND METHOD FOR VECTOR S-PARAMETER MEASUREMENTS
54
Patent #:
10508900
Issue Dt:
12/17/2019
Application #:
15870108
Filing Dt:
01/12/2018
Publication #:
US20180135967
Pub Dt:
05/17/2018
Title:
THREE-DIMENSIONAL SCATTEROMETRY FOR MEASURING DIELECTRIC THICKNESS
55
Patent #:
10707108
Issue Dt:
07/07/2020
Application #:
15872335
Filing Dt:
01/16/2018
Publication #:
US20180138064
Pub Dt:
05/17/2018
Title:
WAFER CARRIER PURGE APPARATUSES, AUTOMATED MECHANICAL HANDLING SYSTEMS INCLUDING THE SAME, AND METHODS OF HANDLING A WAFER CARRIER DURING INTEGRATED CIRCUIT FABRICATION
56
Patent #:
10158021
Issue Dt:
12/18/2018
Application #:
15873935
Filing Dt:
01/18/2018
Publication #:
US20180226503
Pub Dt:
08/09/2018
Title:
VERTICAL PILLAR-TYPE FIELD EFFECT TRANSISTOR AND METHOD
57
Patent #:
10409006
Issue Dt:
09/10/2019
Application #:
15874210
Filing Dt:
01/18/2018
Publication #:
US20180164508
Pub Dt:
06/14/2018
Title:
PHOTONICS CHIP
58
Patent #:
10431665
Issue Dt:
10/01/2019
Application #:
15875055
Filing Dt:
01/19/2018
Publication #:
US20180151690
Pub Dt:
05/31/2018
Title:
MULTIPLE-LAYER SPACERS FOR FIELD-EFFECT TRANSISTORS
59
Patent #:
10199264
Issue Dt:
02/05/2019
Application #:
15875212
Filing Dt:
01/19/2018
Publication #:
US20180151504
Pub Dt:
05/31/2018
Title:
SELF ALIGNED INTERCONNECT STRUCTURES
60
Patent #:
10325913
Issue Dt:
06/18/2019
Application #:
15875609
Filing Dt:
01/19/2018
Publication #:
US20180145079
Pub Dt:
05/24/2018
Title:
METHOD, APPARATUS, AND SYSTEM HAVING SUPER STEEP RETROGRADE WELL WITH ENGINEERED DOPANT PROFILES
61
Patent #:
10242895
Issue Dt:
03/26/2019
Application #:
15876472
Filing Dt:
01/22/2018
Publication #:
US20180143077
Pub Dt:
05/24/2018
Title:
SELF-CONTAINED METROLOGY WAFER CARRIER SYSTEMS
62
Patent #:
10263099
Issue Dt:
04/16/2019
Application #:
15876606
Filing Dt:
01/22/2018
Publication #:
US20180158931
Pub Dt:
06/07/2018
Title:
SELF-ALIGNED FINFET FORMATION
63
Patent #:
10446443
Issue Dt:
10/15/2019
Application #:
15877549
Filing Dt:
01/23/2018
Publication #:
US20180158733
Pub Dt:
06/07/2018
Title:
INTEGRATED CIURCUIT PRODUCT HAVING A THROUGH-SUBSTRATE-VIA (TSV) AND A METALLIZATION LAYER THAT ARE FORMED AFTER FORMATION OF A SEMICONDUCTOR DEVICE
64
Patent #:
10074564
Issue Dt:
09/11/2018
Application #:
15878486
Filing Dt:
01/24/2018
Publication #:
US20180166335
Pub Dt:
06/14/2018
Title:
SELF-ALIGNED MIDDLE OF THE LINE (MOL) CONTACTS
65
Patent #:
10332977
Issue Dt:
06/25/2019
Application #:
15880059
Filing Dt:
01/25/2018
Publication #:
US20180151433
Pub Dt:
05/31/2018
Title:
GATE TIE-DOWN ENABLEMENT WITH INNER SPACER
66
Patent #:
10147496
Issue Dt:
12/04/2018
Application #:
15881356
Filing Dt:
01/26/2018
Publication #:
US20180151238
Pub Dt:
05/31/2018
Title:
NOVEL OTPROM FOR POST-PROCESS PROGRAMMING USING SELECTIVE BREAKDOWN
67
Patent #:
10529728
Issue Dt:
01/07/2020
Application #:
15883975
Filing Dt:
01/30/2018
Publication #:
US20180158833
Pub Dt:
06/07/2018
Title:
SEMICONDUCTOR STRUCTURE INCLUDING A PLURALITY OF PAIRS OF NONVOLATILE MEMORY CELLS AND AN EDGE CELL
68
Patent #:
11069809
Issue Dt:
07/20/2021
Application #:
15884045
Filing Dt:
01/30/2018
Publication #:
US20180175197
Pub Dt:
06/21/2018
Title:
SOI FINFET FINS WITH RECESSED FINS AND EPITAXY IN SOURCE DRAIN REGION
69
Patent #:
10403772
Issue Dt:
09/03/2019
Application #:
15886927
Filing Dt:
02/02/2018
Publication #:
US20180158967
Pub Dt:
06/07/2018
Title:
ELECTRICAL AND OPTICAL VIA CONNECTIONS ON A SAME CHIP
70
Patent #:
10340359
Issue Dt:
07/02/2019
Application #:
15889321
Filing Dt:
02/06/2018
Publication #:
US20180175155
Pub Dt:
06/21/2018
Title:
GATE STRUCTURE WITH DUAL WIDTH ELECTRODE LAYER
71
Patent #:
10164099
Issue Dt:
12/25/2018
Application #:
15889367
Filing Dt:
02/06/2018
Publication #:
US20180175198
Pub Dt:
06/21/2018
Title:
DEVICE WITH DIFFUSION BLOCKING LAYER IN SOURCE/DRAIN REGION
72
Patent #:
10056369
Issue Dt:
08/21/2018
Application #:
15890452
Filing Dt:
02/07/2018
Publication #:
US20180240796
Pub Dt:
08/23/2018
Title:
SEMICONDUCTOR DEVICE INCLUDING BURIED CAPACITIVE STRUCTURES AND A METHOD OF FORMING THE SAME
73
Patent #:
10395939
Issue Dt:
08/27/2019
Application #:
15890859
Filing Dt:
02/07/2018
Publication #:
US20180174855
Pub Dt:
06/21/2018
Title:
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Title:
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Title:
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Title:
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Title:
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Title:
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Title:
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Title:
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Title:
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Title:
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Title:
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Title:
MERGED GATE AND SOURCE/DRAIN CONTACTS IN A SEMICONDUCTOR DEVICE
Assignor
1
GLOBALFOUNDRIES INC.
Exec Dt:
11/27/2018
Assignee
1
WILMINGTON TRUST, NATIONAL ASSOCIATION
1100 NORTH MARKET STREET
WILMINGTON, DELAWARE 19801
Correspondence name and address
CT CORPORATION
4400 EASTON COMMONS WAY
SUITE 125
COLUMBUS, OH 43219

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