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11/11/2003
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10051790
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01/17/2002
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Title:
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10/14/2003
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10052142
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01/17/2002
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Title:
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12/30/2003
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10052146
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01/17/2002
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09/16/2003
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10053033
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11/07/2001
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05/08/2003
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06/01/2004
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10054409
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11/13/2001
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05/15/2003
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RESONANT OPERATION OF MEMS SWITCH
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10/19/2004
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10055138
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01/23/2002
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07/24/2003
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12/17/2002
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10055139
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01/23/2002
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11/22/2005
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10055275
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01/23/2002
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07/24/2003
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Title:
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PSEUDO RANDOM OPTIMIZED BUILT-IN SELF-TEST
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02/25/2003
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10055704
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01/22/2002
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06/06/2002
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BEOL DECOUPLING CAPACITOR
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07/29/2003
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10056531
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01/24/2002
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07/18/2002
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NANOPARTICLES FORMED WITH RIGID CONNECTOR COMPOUNDS
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11/30/2004
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10057024
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01/25/2002
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06/13/2002
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Title:
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SYNTHESIS OF SOLUBLE DERIVATIVES OF SEXITHIOPHENE AND THEIR USE AS THE SEMICONDUCTING CHANNELS IN THIN-FILM FIELD-EFFECT TRANSISTORS
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02/07/2006
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10057185
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01/25/2002
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06/13/2002
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METHOD OF FABRICATING A CAPACITOR HAVING SIDEWALL SPACER PROTECTING THE DIELECTRIC LAYER
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06/01/2004
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10058999
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01/29/2002
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07/31/2003
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Title:
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MODULE WITH ADHESIVELY ATTACHED HEAT SINK
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03/30/2004
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10059268
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01/31/2002
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Title:
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VAPOR TREATMENT FOR REPAIRING DAMAGE OF LOW-K DIELECTRIC
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01/07/2003
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10059713
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01/29/2002
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Title:
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ACCESSING FIRST CACHE WITH RETURN STACK TOP ENTRY AND SECOND CACHE WITH NESXT ENTRY UPON RETURN INSTRUCTION
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09/16/2003
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10059775
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01/30/2002
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07/31/2003
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Title:
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APPARATUS AND METHOD FOR FRONT SIDE CHEMICAL MECHANICAL PLANARIZATION (CMP) OF SEMICONDUCTOR WORKPIECES
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11/18/2003
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10059863
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01/30/2002
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07/31/2003
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HIGH RELIABILITY CONTENT-ADDRESSABLE MEMORY USING SHADOW CONTENT-ADDRESSABLE MEMORY
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09/02/2003
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10060422
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01/30/2002
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Title:
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TRANSISTOR HAVING A GATE STACK COMPRISED OF A METAL, AND A METHOD OF MAKING SAME
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01/13/2004
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10061263
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01/31/2002
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07/31/2003
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BODY CONTACT MOSFET
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08/10/2004
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10062812
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01/31/2002
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07/31/2003
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EMBEDDED DRAM SYSTEM HAVING WIDE DATA BANDWIDTH AND DATA TRANSFER DATA PROTOCOL
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08/17/2004
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10062972
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01/31/2002
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07/31/2003
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Title:
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EMBEDDED DRAM SYSTEM HAVING WIDE DATA BANDWIDTH AND DATA TRANSFER DATA PROTOCOL
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12/02/2003
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10063095
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03/19/2002
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09/25/2003
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FINFET CMOS WITH NVRAM CAPABILITY
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08/17/2004
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10063212
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03/29/2002
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10/02/2003
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COMPLEMENTARY TWO TRANSISTOR ROM CELL
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05/04/2004
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10063225
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04/01/2002
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10/02/2003
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DUAL EMITTER TRANSISTOR WITH ESD PROTECTION
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06/15/2004
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10063323
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04/11/2002
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10/16/2003
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DUAL DOUBLE GATE TRANSISTOR AND METHOD FOR FORMING
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02/24/2004
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10063329
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04/12/2002
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10/16/2003
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LOCALIZED DIRECT SENSE ARCHITECTURE
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12/16/2003
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10063330
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04/12/2002
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10/23/2003
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FIN MEMORY CELL AND METHOD OF FABRICATION
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09/21/2004
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10063376
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04/17/2002
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10/30/2003
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MOS ANTIFUSE WITH LOW POST-PROGRAM RESISTANCE
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01/24/2006
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10063394
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04/18/2002
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10/23/2003
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ON CHIP TIMING ADJUSTMENT IN MULTI-CHANNEL FAST DATA TRANSFER
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11/23/2004
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10063427
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04/23/2002
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10/23/2003
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PHYSICAL DESIGN CHARACTERIZATION SYSTEM
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12/11/2007
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10063495
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04/30/2002
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10/30/2003
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TESTING OF ECC MEMORIES
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12/12/2006
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10063497
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04/30/2002
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10/30/2003
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OPTIMIZED ECC/REDUNDANCY FAULT RECOVERY
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05/04/2004
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10063504
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05/01/2002
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11/06/2003
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GLOBAL VOLTAGE BUFFER FOR VOLTAGE ISLANDS
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08/10/2004
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10063846
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05/17/2002
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11/20/2003
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INCORPORATION OF AN IMPURITY INTO A THIN FILM
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07/13/2004
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10063858
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05/20/2002
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11/20/2003
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FAULT FREE FUSE NETWORK
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03/28/2006
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10063859
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05/20/2002
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11/20/2003
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METHOD AND APPARATUS FOR PROVIDING NOISE SUPPRESSION IN AN INTEGRATED CIRCUIT
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11/04/2003
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10063994
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06/03/2002
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FIN FET DEVICES FROM BULK SEMICONDUCTOR AND METHOD FOR FORMING
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10/28/2003
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10064303
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07/01/2002
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MONOLITHICALLY INTEGRATED SOLID-STATE SIGE THERMOELECTRIC ENERGY CONVERTER FOR HIGH SPEED AND LOW POWER CIRCUITS
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03/23/2004
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10064306
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07/01/2002
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01/01/2004
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WRITEBACK AND REFRESH CIRCUITRY FOR DIRECT SENSED DRAM MACRO
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06/22/2004
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10064375
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07/08/2002
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01/08/2004
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HIGH IMPEDANCE ANTIFUSE
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11/14/2006
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10064486
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07/19/2002
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01/22/2004
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METHOD AND APPARATUS TO MANAGE MULTI-COMPUTER DEMAND
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09/21/2004
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10064493
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07/22/2002
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01/22/2004
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APPLICATIONS OF SPACE-CHARGE-LIMITED CONDUCTION INDUCED CURRENT INCREASE IN NITRIDE-OXIDE DIELECTRIC CAPACITORS: VOLTAGE REGULATOR FOR POWER SUPPLY SYSTEM AND OTHERS
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01/06/2004
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10064867
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08/26/2002
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COLUMN REDUNDANCY SYSTEM AND METHOD FOR A MICRO-CELL EMBEDDED DRAM (E-DRAM) ARCHITECTURE
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09/21/2004
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10064921
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08/29/2002
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03/04/2004
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APPARATUS FOR REDUCING SOFT ERRORS IN DYNAMIC CIRCUITS
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11/16/2004
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10065201
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09/25/2002
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03/25/2004
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VOLTAGE ISLAND CHIP IMPLEMENTATION
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06/10/2003
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10065223
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09/26/2002
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SELF TIMING INTERLOCK CIRCUIT FOR EMBEDDED DRAM
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08/16/2005
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10065475
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10/22/2002
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04/22/2004
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TERMINATING RESISTOR DRIVER FOR HIGH SPEED DATA COMMUNICATION
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02/08/2005
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10065839
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11/25/2002
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05/27/2004
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DRAM-BASED SEPARATE I/O MEMORY SOLUTION FOR COMMUNICATION APPLICATIONS
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05/11/2004
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10065884
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11/27/2002
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THINNING OF FUSE PASSIVATION AFTER C4 FORMATION
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08/28/2007
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10066948
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02/04/2002
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REMOTE MANAGEMENT MECHANISM TO PREVENT ILLEGAL SYSTEM COMMANDS
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12/30/2003
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10068396
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02/05/2002
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INERT ATOM IMPLANTATION METHOD FOR SOI GETTERING
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05/13/2003
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10072330
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02/07/2002
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MICRO-STRUCTURES AND METHODS FOR THEIR MANUFACTURE
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06/13/2006
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10072346
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02/06/2002
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08/08/2002
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ADDRESS WRAP FUNCTION FOR ADDRESSABLE MEMORY DEVICES
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08/10/2004
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10072486
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02/07/2002
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08/07/2003
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NONINVASIVE OPTICAL METHOD AND SYSTEM FOR INSPECTING OR TESTING CMOS CIRCUITS
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08/31/2004
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10073066
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02/12/2002
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PHOSPHINE TREATMENT OF LOW DIELECTRIC CONSTANT MATERIALS IN SEMICONDUCTOR DEVICE MANUFACTURING
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06/24/2008
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10073630
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02/11/2002
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10/24/2002
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PROGRAM COMPONENTS HAVING MULTIPLE SELECTABLE IMPLEMENTATIONS
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05/25/2004
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10073695
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02/11/2002
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11/14/2002
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ENHANCED INTERFACE THERMOELECTRIC COOLERS WITH ALL-METAL TIPS
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05/24/2005
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10073755
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02/11/2002
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08/14/2003
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MAGNETIC-FIELD SENSOR DEVICE
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11/18/2003
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10078174
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02/15/2002
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08/21/2003
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UNIQUE FEATURE DESIGN ENABLING STRUCTURAL INTEGRITY FOR ADVANCED LOW K SEMICONDUCTOR CHIPS
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05/13/2003
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10078779
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02/19/2002
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METHOD OF PROTECTING SEMICONDUCTOR AREAS WHILE EXPOSING A GATE
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09/23/2003
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10078948
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02/19/2002
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08/21/2003
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SACRIFICIAL SEED LAYER PROCESS FOR FORMING C4 SOLDER BUMPS
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08/28/2007
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10079289
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02/19/2002
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07/11/2002
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FLUORINATED SILSESQUIOXANE POLYMERS AND USE THEREOF IN LITHOGRAPHIC PHOTORESIST COMPOSITIONS
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06/10/2003
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10079861
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02/22/2002
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Title:
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METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH RELIABLE CONTACTS/VIAS
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Patent #:
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Issue Dt:
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05/13/2003
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Application #:
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10082766
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Filing Dt:
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02/25/2002
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Title:
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NON-COHERENT CACHE BUFFER FOR READ ACCESSES TO SYSTEM MEMORY
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Patent #:
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Issue Dt:
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04/14/2009
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Application #:
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10083149
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Filing Dt:
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02/27/2002
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Title:
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ARRANGEMENT IN A CHANNEL ADAPTER FOR TRANSMITTING DATA ACCORDING TO LINK WIDTHS SELECTED BASED ON RECEIVED LINK MANAGEMENT PACKETS
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Patent #:
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Issue Dt:
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11/04/2003
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Application #:
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10083699
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Filing Dt:
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02/26/2002
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Title:
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METHOD OF DETECTING DEGRADATION IN PHOTOLITHOGRAPHY PROCESSES BASED UPON SCATTEROMETRIC MEASUREMENTS OF GRATING STRUCTURES, AND A DEVICE COMPRISING SUCH STRUCTURES
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Patent #:
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Issue Dt:
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12/09/2003
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Application #:
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10083809
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Filing Dt:
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02/26/2002
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Title:
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METHOD OF REDUCING ELECTOMIGRATION IN A COPPER LINE BY ELECTROPLATING AN INTERIM COPPER-ZINC ALLOY THIN FILM ON A COPPER SURFACE AND A SEMICONDUCTOR DEVICE THEREBY FORMED
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Patent #:
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Issue Dt:
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07/20/2004
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Application #:
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10083914
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Filing Dt:
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02/27/2002
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Publication #:
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Pub Dt:
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08/28/2003
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Title:
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SELF-ALIGNED PATTERN FORMATION USING DUAL WAVELENGTHS
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Patent #:
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Issue Dt:
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07/20/2004
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Application #:
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10084321
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Filing Dt:
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02/28/2002
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Title:
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METHOD FOR FORMING NITRIDE CAPPED CU LINES WITH REDUCED HILLOCK FORMATION
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Patent #:
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Issue Dt:
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04/06/2004
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Application #:
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10084563
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Filing Dt:
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02/26/2002
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Title:
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METHOD OF REDUCING ELECTROMIGRATION BY FORMING AN ELECTROPLATED COPPER-ZINC INTERCONNECT AND A SEMICONDUCTOR DEVICE THEREBY FORMED
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Patent #:
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Issue Dt:
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02/17/2004
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Application #:
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10085318
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Filing Dt:
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02/27/2002
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Title:
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INTERFACIAL BARRIER LAYER IN SEMICONDUCTOR DEVICES WITH HIGH-K GATE DIELECTRIC MATERIAL
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Patent #:
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Issue Dt:
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09/17/2002
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Application #:
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10085348
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Filing Dt:
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02/27/2002
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Title:
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NON-REDUCING PROCESS FOR DEPOSITION OF POLYSILICON GATE ELECTRODE OVER HIGH-K GATE DIELECTRIC MATERIAL
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Patent #:
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Issue Dt:
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02/24/2004
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Application #:
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10085938
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Filing Dt:
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02/28/2002
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Title:
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METHOD AND APPARATUS FOR MODELING OF BATCH DYNAMICS BASED UPON INTEGRATED METROLOGY
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Patent #:
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Issue Dt:
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11/30/2004
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Application #:
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10085956
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Filing Dt:
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02/28/2002
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Publication #:
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Pub Dt:
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08/28/2003
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Title:
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ASSOCIATION OF PROCESS CONTEXT WITH CONFIGURATION DOCUMENT FOR MANUFACTURING PROCESS
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Patent #:
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Issue Dt:
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01/11/2011
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Application #:
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10085965
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Filing Dt:
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02/28/2002
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Title:
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COMMUNICATION SCHEME-INDEPENDENT INFRASTRUCTURE
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Patent #:
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Issue Dt:
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04/18/2006
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Application #:
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10090507
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Filing Dt:
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03/04/2002
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Title:
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COMPUTER GRAPHICS PROCESSING SYSTEM, COMPUTER MEMORY, AND METHOD OF USE WITH COMPUTER GRAPHICS PROCESSING SYSTEM UTILIZING HIERARCHICAL IMAGE DEPTH BUFFER
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Patent #:
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Issue Dt:
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12/13/2005
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Application #:
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10090589
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Filing Dt:
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02/28/2002
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Publication #:
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Pub Dt:
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07/03/2003
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Title:
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OPTICAL APERTURE FOR DATA RECORDING HAVING TRANSMISSION ENHANCED BY WAVEGUIDE MODE RESONANCE
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Patent #:
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Issue Dt:
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08/24/2004
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Application #:
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10091193
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Filing Dt:
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03/05/2002
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Publication #:
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Pub Dt:
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11/07/2002
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Title:
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SEMICONDUCTOR HIGH DIELECTRIC CONSTANT DECOUPLING CAPACITOR STRUCTURES AND PROCESS FOR FABRICATION
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Patent #:
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Issue Dt:
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04/15/2008
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Application #:
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10091373
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Filing Dt:
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03/04/2002
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Publication #:
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Pub Dt:
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10/02/2003
| | | | |
Title:
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COPOLYMER FOR USE IN CHEMICAL AMPLIFICATION RESISTS
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Patent #:
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Issue Dt:
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02/11/2003
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Application #:
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10091643
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Filing Dt:
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03/06/2002
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Title:
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ELECTRICALLY POROUS ON-CHIP DECOUPLING/SHIELDING LAYER
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Patent #:
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Issue Dt:
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08/05/2003
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Application #:
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10091663
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Filing Dt:
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03/06/2002
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Title:
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LOW-POWER STATIC COLUMN REDUNDANCY SCHEME FOR SEMICONDUCTOR MEMORIES
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Patent #:
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Issue Dt:
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06/06/2006
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Application #:
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10091766
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Filing Dt:
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03/05/2002
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Title:
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COMPUTER SYSTEM INITIALIZATION VIA BOOT CODE STORED IN A NON-VOLATILE MEMORY HAVING AN INTERFACE COMPATIBLE WITH SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY
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Patent #:
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Issue Dt:
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12/21/2004
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Application #:
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10093055
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Filing Dt:
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03/07/2002
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Title:
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METHOD AND APPARATUS FOR REORDERING PACKET TRANSACTIONS WITHIN A PERIPHERAL INTERFACE CIRCUIT
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Patent #:
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Issue Dt:
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07/06/2004
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Application #:
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10093125
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Filing Dt:
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03/07/2002
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Title:
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BUFFER CIRCUIT FOR A PERIPHERAL INTERFACE CIRCUIT IN AN I/O NODE OF A COMPUTER SYSTEM
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Patent #:
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Issue Dt:
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04/20/2004
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Application #:
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10093146
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Filing Dt:
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03/07/2002
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Title:
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PERIPHERAL INTERFACE CIRCUIT FOR AN I/O NODE OF A COMPUTER SYSTEM
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Patent #:
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Issue Dt:
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07/06/2004
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Application #:
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10093270
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Filing Dt:
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03/07/2002
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Title:
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BUFFER CIRCUIT FOR ROTATING OUTSTANDING TRANSACTIONS
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Patent #:
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Issue Dt:
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06/29/2004
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Application #:
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10093346
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Filing Dt:
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03/07/2002
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Publication #:
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Pub Dt:
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04/17/2003
| | | | |
Title:
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PERIPHERAL INTERFACE CIRCUIT FOR HANDLING GRAPHICS RESPONSES IN AN I/O NODE OF A COMPUTER SYSTEM
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Patent #:
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Issue Dt:
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11/23/2004
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Application #:
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10093349
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Filing Dt:
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03/07/2002
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Title:
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METHOD AND APPARATUS FOR INITIATING PARTIAL TRANSACTIONS IN A PERIPHERAL INTERFACE CIRCUIT FOR AN I/O NODE OF A COMPUTER SYSTEM
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Patent #:
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Issue Dt:
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03/04/2003
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Application #:
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10094061
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Filing Dt:
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03/08/2002
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Title:
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METHOD FOR IDENTIFYING AND CONTROLLING IMPACT OF AMBIENT CONDITIONS ON PHOTOLITHOGRAPHY PROCESSES
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Patent #:
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Issue Dt:
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03/04/2003
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Application #:
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10094533
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Filing Dt:
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03/08/2002
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Title:
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LOW POWER STATIC MEMORY
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Patent #:
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Issue Dt:
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05/15/2012
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Application #:
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10094550
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Filing Dt:
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03/08/2002
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Publication #:
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Pub Dt:
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09/11/2003
| | | | |
Title:
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SYSTEM FOR BROKERING FAULT DETECTION DATA
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Patent #:
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Issue Dt:
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12/23/2003
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Application #:
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10095019
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Filing Dt:
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03/11/2002
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Publication #:
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Pub Dt:
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07/11/2002
| | | | |
Title:
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SYSTEM AND METHOD FOR INITIATING A SERIAL DATA TRANSFER BETWEEN TWO CLOCK DOMAINS
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Patent #:
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Issue Dt:
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11/02/2004
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Application #:
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10095889
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Filing Dt:
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03/12/2002
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Publication #:
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Pub Dt:
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07/18/2002
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Title:
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ANTIFUSES AND METHODS FOR FORMING THE SAME
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Patent #:
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Issue Dt:
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11/11/2008
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Application #:
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10096474
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Filing Dt:
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03/11/2002
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Publication #:
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Pub Dt:
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09/18/2003
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Title:
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METHOD FOR CONSTRUCTING SEGMENTATION-BASED PREDICTIVE MODELS
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Patent #:
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Issue Dt:
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04/29/2003
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Application #:
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10097159
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Filing Dt:
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03/13/2002
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Title:
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METHOD AND APPARATUS FOR ENHANCING ENDPOINT DETECTION OF A VIA ETCH
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Patent #:
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Issue Dt:
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03/04/2003
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Application #:
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10097467
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Filing Dt:
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03/14/2002
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Title:
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METHOD AND APPARATUS FOR AUTOMATIC ROUTING FOR REENTRANT PROCESSES
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Patent #:
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Issue Dt:
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01/27/2004
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Application #:
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10097637
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Filing Dt:
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03/14/2002
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Title:
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GROWTH OF PHOTORESIST LAYER IN PHOTOLITHOGRAPHIC PROCESS
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Patent #:
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Issue Dt:
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10/07/2003
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Application #:
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10097819
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Filing Dt:
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03/14/2002
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Title:
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REDUCING FEATURE DIMENSION USING SELF-ASSEMBLED MONOLAYER
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Patent #:
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Issue Dt:
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08/03/2004
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Application #:
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10099004
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Filing Dt:
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03/15/2002
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Publication #:
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Pub Dt:
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10/02/2003
| | | | |
Title:
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PROCESS OF PASSIVATING A METAL-GATED COMPLEMENTARY METAL OXIDE SEMICONDUCTOR
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Patent #:
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Issue Dt:
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07/01/2014
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Application #:
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10099508
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Filing Dt:
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03/15/2002
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Publication #:
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Pub Dt:
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09/18/2003
| | | | |
Title:
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Generating a common symbol table for symbols of independent applications
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