|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/23/2001
|
Application #:
|
09201995
|
Filing Dt:
|
12/01/1998
|
|
Title:
|
SEMICONDUCTOR DEVICE HAVING GATE ELECTRODE SHARED BETWEEN TWO SETS OF ACTIVE REGIONS AND FABRICATION THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/26/2000
|
Application #:
|
09203012
|
Filing Dt:
|
12/01/1998
|
|
Title:
|
SEMICONDUCTOR DEVICE AND FABRICATION METHOD USING A GERMANIUM SACRIFICIAL GATE ELECTRODE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/26/2000
|
Application #:
|
09203150
|
Filing Dt:
|
12/01/1998
|
|
Title:
|
THIN RESIST WITH AMORPHOUS SILICON HARD MASK FOR VIA ETCH APPLICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/03/2000
|
Application #:
|
09203283
|
Filing Dt:
|
12/01/1998
|
|
Title:
|
THIN RESIST WITH NITRIDE HARD MASK FOR VIA ETCH APPLICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/31/2000
|
Application #:
|
09203447
|
Filing Dt:
|
12/01/1998
|
|
Title:
|
METHOD FOR TRANSFERRING PATTERNS CREATED BY LITHOGRAPHY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/19/2000
|
Application #:
|
09203450
|
Filing Dt:
|
12/01/1998
|
|
Title:
|
THIN RESIST WITH TRANSITION METAL HARD MASK FOR VIA ETCH APPLICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/01/2000
|
Application #:
|
09203461
|
Filing Dt:
|
12/02/1998
|
|
Title:
|
ULTRA-THIN RESIST AND NITRIDE/OXIDE HARD MASK FOR METAL ETCH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/26/2001
|
Application #:
|
09203572
|
Filing Dt:
|
12/02/1998
|
|
Title:
|
INTEGRATION OF LOW-K SIOF AS INTER-LAYER DIELECTRIC
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/23/2001
|
Application #:
|
09203754
|
Filing Dt:
|
12/02/1998
|
|
Title:
|
INTEGRATION OF LOW-K SIOF FOR DAMASCENE STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/05/2000
|
Application #:
|
09203774
|
Filing Dt:
|
12/02/1998
|
|
Title:
|
ULTRA-THIN RESIST AND SILICON/OXIDE HARD MASK FOR METAL ETCH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/26/2000
|
Application #:
|
09203926
|
Filing Dt:
|
12/02/1998
|
|
Title:
|
ELECTROMIGRATION-RESISTANT COPPER MICROSTRUCTURE AND PROCESS OF MAKING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/06/2004
|
Application #:
|
09204025
|
Filing Dt:
|
12/01/1998
|
|
Title:
|
APPARATUS AND METHOD FOR CURRENT DEMAND DISTRIBUTION IN ELECTRONIC SYSTEMS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/31/2001
|
Application #:
|
09204185
|
Filing Dt:
|
12/03/1998
|
|
Title:
|
METHOD FOR FORMING ELECTROMIGRATION-RESISTANT STRUCTURES BY DOPING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/13/2001
|
Application #:
|
09204216
|
Filing Dt:
|
12/02/1998
|
|
Title:
|
ULTRA-THIN RESIST AND BARRIER METAL/OXIDE HARD MASK FOR METAL ETCH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/16/2001
|
Application #:
|
09204458
|
Filing Dt:
|
12/02/1998
|
|
Title:
|
COMPOSITE LAMINATE CIRCUIT STRUCTURE AND METHOD OF FORMING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/23/2001
|
Application #:
|
09204630
|
Filing Dt:
|
12/02/1998
|
|
Title:
|
ULTRA-THIN RESIST AND SION/OXIDE HARD MASK FOR METAL ETCH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/09/2001
|
Application #:
|
09204651
|
Filing Dt:
|
12/02/1998
|
|
Title:
|
ULTRA-THIN RESIST AND OXIDE/NITRIDE HARD MASK FOR METAL ETCH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/24/2001
|
Application #:
|
09204967
|
Filing Dt:
|
12/03/1998
|
|
Title:
|
METHOD OF MAKING AN ELEVATED SOURCE/DRAIN WITH ENHANCED GRADED SIDEWALLS FOR TRANSISTOR SCALING INTEGRATED WITH SPACER FORMATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/30/2001
|
Application #:
|
09204978
|
Filing Dt:
|
12/03/1998
|
|
Title:
|
MINIMIZING CACHE OVERHEAD BY STORING DATA FOR COMMUNICATIONS BETWEEN A PERIPHERAL DEVICE AND A HOST SYSTEM INTO SEPARATE LOCATIONS IN MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/06/2001
|
Application #:
|
09204998
|
Filing Dt:
|
12/02/1998
|
|
Title:
|
METHOD OF FORMING A MOSFET TRANSISTOR WITH A SHALLOW ABRUPT RETROGRADE DOPANT PROFILE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/27/2001
|
Application #:
|
09205010
|
Filing Dt:
|
12/04/1998
|
|
Title:
|
MARK PROTECTION WITH TRANSPARENT FILM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/26/2000
|
Application #:
|
09205068
|
Filing Dt:
|
12/04/1998
|
|
Title:
|
ANTIREFLECTIVE COATING USED IN THE FABRICATION OF MICROCIRCUIT STRUCTURES IN 0.18 MICRON AND SMALLER TECHNOLOGIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/21/1999
|
Application #:
|
09205321
|
Filing Dt:
|
12/04/1998
|
|
Title:
|
ARGON DOPED EPITAXIAL LAYERS FOR INHIBITING PUNCHTHROUGH WITHIN A SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/13/2001
|
Application #:
|
09205443
|
Filing Dt:
|
12/04/1998
|
|
Title:
|
USE OF SACRIFICIAL DIELECTRIC STRUCTURE TO FORM SEMICONDUCTOR DEVICE WITH A SELF-ALIGNED THRESHOLD ADJUST AND OVERLYING LOW-RESISTANCE GATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/28/2000
|
Application #:
|
09205444
|
Filing Dt:
|
12/04/1998
|
|
Title:
|
PROCESSOR EMPLOYING MULTIPLE REGISTER SETS TO ELIMINATE INTERRUPTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/20/2001
|
Application #:
|
09205522
|
Filing Dt:
|
12/03/1998
|
|
Title:
|
METHOD FOR FORMING A SHALLOW JUNCTION IN A SEMICONDUCTOR DEVICE USING ANTIMONY DIMER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/09/2000
|
Application #:
|
09205583
|
Filing Dt:
|
12/04/1998
|
|
Title:
|
METHOD FOR FABRICATING DUAL LAYER PROTECTIVE BARRIER COPPER METALLIZATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/19/2003
|
Application #:
|
09205589
|
Filing Dt:
|
12/04/1998
|
|
Title:
|
SINGLE POINT HIGH RESOLUTION TIME RESOLVED PHOTOEMISSION MICROSCOPY SYSTEM AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/26/2000
|
Application #:
|
09205616
|
Filing Dt:
|
12/04/1998
|
|
Title:
|
METHOD OF MANUFACTURING MOSFET WITH DIFFERENTIAL GATE OXIDE THICKNESS ON THE SAME IC CHIP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/23/2001
|
Application #:
|
09205790
|
Filing Dt:
|
12/04/1998
|
|
Title:
|
LITHOGRAPHY REFLECTIVE MASK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/11/2000
|
Application #:
|
09205791
|
Filing Dt:
|
12/04/1998
|
|
Title:
|
BACKSIDE POLISH EUV MASK AND METHOD OF MANUFACTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/05/2000
|
Application #:
|
09205897
|
Filing Dt:
|
12/04/1998
|
|
Title:
|
ILLUMINATION MODIFICATION SCHEME SYNTHESIS USING LENS CHARACTERIZATION DATA
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2001
|
Application #:
|
09205898
|
Filing Dt:
|
12/04/1998
|
|
Title:
|
METHODOLOGY FOR EXTRACTING EFFECTIVE LENS ABERRATIONS USING A NEURAL NETWORK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/07/2000
|
Application #:
|
09205934
|
Filing Dt:
|
12/04/1998
|
|
Title:
|
DRAM CELL HAVING AN ANNULAR SIGNAL TRANSFER REGION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/13/2001
|
Application #:
|
09205935
|
Filing Dt:
|
12/04/1998
|
|
Title:
|
MULTI-WAFER POLISHING TOOL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/11/2000
|
Application #:
|
09205958
|
Filing Dt:
|
12/04/1998
|
|
Title:
|
REWORKABLE EUV MASK MATERIALS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/04/2000
|
Application #:
|
09205978
|
Filing Dt:
|
12/04/1998
|
|
Title:
|
METHOD AND APPARATUS FOR OPTIMIZING MEMORY PERFORMANCE WITH OPPORTUNISTIC REFRESHING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/27/2001
|
Application #:
|
09206163
|
Filing Dt:
|
12/07/1998
|
|
Title:
|
PREVENTION OF CU DENDRITE FORMATION AND GROWTH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/23/2001
|
Application #:
|
09206169
|
Filing Dt:
|
12/07/1998
|
|
Title:
|
PREVENTING CU DENDRITE FORMATION AND GROWTH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/22/2003
|
Application #:
|
09206170
|
Filing Dt:
|
12/07/1998
|
|
Title:
|
CHEMICALLY PEVENTING CU DENDRITE FORMATION AND GROWTH BY IMMERSION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/26/2002
|
Application #:
|
09206550
|
Filing Dt:
|
12/07/1998
|
|
Title:
|
SEMICONDUCTOR TOPOGRAPHY HAVING IMPROVED ACTIVE DEVICE ISOLATION AND REDUCED DOPANT MIGRATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/26/2000
|
Application #:
|
09206669
|
Filing Dt:
|
12/07/1998
|
|
Title:
|
METHOD FOR FORMING CONFORMAL BARRIER LAYERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/31/2000
|
Application #:
|
09206951
|
Filing Dt:
|
12/08/1998
|
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING WITHOUT DAMAGING HSQ LAYER AND METAL PATTERN UTILIZING MULTIPLE DIELECTRIC LAYERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/20/2001
|
Application #:
|
09207318
|
Filing Dt:
|
12/07/1998
|
|
Title:
|
CHEMICALLY PREVENTING COPPER DENDRITE FORMATION AND GROWTH BY SPRAYING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/01/2001
|
Application #:
|
09207675
|
Filing Dt:
|
12/09/1998
|
|
Title:
|
HIGH DENSITY CAPPING LAYERS WITH IMPROVED ADHESION TO COPPER INTERCONNECTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/27/2001
|
Application #:
|
09207676
|
Filing Dt:
|
12/09/1998
|
|
Title:
|
H2 DIFFUSION BARRIER FORMATION BY NITROGEN INCORPORATION IN OXIDE LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/05/2001
|
Application #:
|
09207680
|
Filing Dt:
|
12/09/1998
|
|
Title:
|
METHOD OF FORMING COPPER/COPPER ALLOY INTERCONNECTION WITH REDUCED ELECTROMIGRATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/21/2003
|
Application #:
|
09207971
|
Filing Dt:
|
12/09/1998
|
|
Title:
|
METHOD AND SYSTEM FOR PAGE-STATE SENSITIVE MEMORY CONTROL AND ACCESS IN DATA PROCESSING SYSTEMS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/17/2001
|
Application #:
|
09208305
|
Filing Dt:
|
12/09/1998
|
|
Title:
|
METHOD AND SYSTEM FOR ORIGIN-SENSITIVE MEMORY CONTROL AND ACCESS IN DATA PROCESSING SYSTEMS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/01/2001
|
Application #:
|
09208569
|
Filing Dt:
|
12/09/1998
|
|
Title:
|
METHOD AND SYSTEM FOR GENERATING AND UTILIZING SPECULATIVE MEMORY ACCESS REQUESTS IN DATA PROCESSING SYSTEMS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/19/1999
|
Application #:
|
09208597
|
Filing Dt:
|
12/08/1998
|
|
Title:
|
MANUFACTURABLE CAPPING LAYER FOR THE FABRICATION OF COBALT SALICIDE STRUCTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/20/2001
|
Application #:
|
09208713
|
Filing Dt:
|
12/09/1998
|
|
Title:
|
METHOD AND SYSTEM FOR SELECTIVELY DISCONNECTING A REDUNDANT POWER DISTRIBUTION NETWORK TO IDENTIFY A SITE OF A SHORT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/04/2001
|
Application #:
|
09208909
|
Filing Dt:
|
12/10/1998
|
|
Title:
|
PROGRAMMABLE STATE MACHINE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/04/2003
|
Application #:
|
09209119
|
Filing Dt:
|
12/10/1998
|
|
Title:
|
INITIALIZING AND SAVING PERIPHERAL DEVICE CONFIGURATION STATES OF A MICROCONTROLLER USING A UTILITY PROGRAM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/26/2002
|
Application #:
|
09209190
|
Filing Dt:
|
12/10/1998
|
|
Title:
|
METHOD AND APPARATUS FOR SAVING AND LOADING PERIPHERAL DEVICE STATES OF A MICROCONTROLLER VIA A SCAN PATH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/23/2000
|
Application #:
|
09209413
|
Filing Dt:
|
12/10/1998
|
|
Title:
|
METHOD AND APPARATUS FOR PREVENTING FORMATION OF BLACK SILICON ON EDGES OF WAFERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/07/2003
|
Application #:
|
09217367
|
Filing Dt:
|
12/21/1998
|
|
Title:
|
FLEXIBLE PROBE/PROBE RESPONSE ROUTING FOR MAINTAINING COHERENCY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2001
|
Application #:
|
09217649
|
Filing Dt:
|
12/21/1998
|
|
Title:
|
MESSAGING SCHEME TO MAINTAIN CACHE COHERENCY AND CONSERVE SYSTEM MEMORY BANDWIDTH DURING A MEMORY READ OPERATION IN A MULTIPROCESSING COMPUTER SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/05/2000
|
Application #:
|
09224766
|
Filing Dt:
|
01/04/1999
|
|
Title:
|
ESD PROTECTION CIRCUIT FOR MULTIPLE POWER SUUPLY ENVIRONMENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/15/2002
|
Application #:
|
09224820
|
Filing Dt:
|
01/04/1999
|
|
Title:
|
ADDRESS SPACE CONVERSION TO RETAIN SOFTWARE COMPATIBILITY IN NEW ARCHITECTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/26/2001
|
Application #:
|
09224821
|
Filing Dt:
|
01/04/1999
|
|
Title:
|
COLLATION OF INTERRUPT CONTROL DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/04/2002
|
Application #:
|
09224822
|
Filing Dt:
|
01/04/1999
|
|
Title:
|
BANK HISTORY TABLE FOR IMPROVED PRE-CHARGE SCHEDULING OF RANDOM ACCESS MEMORY BANKS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/11/2001
|
Application #:
|
09225175
|
Filing Dt:
|
01/04/1999
|
|
Title:
|
METHOD OF DEFINING COPPER SEED LAYER FOR SELECTIVE ELECTROLESS PLATING PROCESSING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/29/2003
|
Application #:
|
09225219
|
Filing Dt:
|
01/04/1999
|
|
Publication #:
|
|
Pub Dt:
|
10/10/2002
| | | | |
|
Title:
|
NETWORK TRANSCEIVER FOR STEERING NETWORK DATA TO SELECTED PATHS BASED ON DETERMINED LINK SPEEDS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/18/2000
|
Application #:
|
09225339
|
Filing Dt:
|
01/05/1999
|
|
Title:
|
BLAZED GRATING MEASUREMENTS OF LITHOGRAPHIC LENS ABERATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/24/2010
|
Application #:
|
09225388
|
Filing Dt:
|
01/05/1999
|
|
Title:
|
METHOD AND APPARATUS FOR PATTERN MATCHING ON SINGLE AND MULTIPLE PATTERN STRUCTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/15/2000
|
Application #:
|
09225539
|
Filing Dt:
|
01/05/1999
|
|
Title:
|
METHOD OF FORMING RELIABLE COPPER INTERCONNECTS WITH IMPROVED HOLE FILLING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/20/2000
|
Application #:
|
09225541
|
Filing Dt:
|
01/05/1999
|
|
Title:
|
LOW DIELECTRIC SEMICONDUCTOR DEVICE WITH RIGID LINED INTERCONNECTION SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/03/2001
|
Application #:
|
09225542
|
Filing Dt:
|
01/05/1999
|
|
Title:
|
DUAL DAMASCENE ARRANGEMENT FOR METAL INTERCONNECTION WITH LOW K DIELECTRIC CONSTANT MATERIALS IN DIELECTRIC LAYERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/18/2000
|
Application #:
|
09225595
|
Filing Dt:
|
01/06/1999
|
|
Title:
|
PROCESS FOR FABRICATING A SEMICONDUCTOR STRUCTURE HAVING A SELF-ALIGNED SPACER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/15/2000
|
Application #:
|
09225597
|
Filing Dt:
|
01/06/1999
|
|
Title:
|
APPARATUS AND METHOD FOR CONTROLLING POLISHING OF INTEGRATED CIRCUIT SUBSTRATES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/27/2000
|
Application #:
|
09225644
|
Filing Dt:
|
01/05/1999
|
|
Title:
|
SEMICONDUCTOR INTERCONNECT INTERFACE PROCESSING BY HIGH PRESSURE DEPOSITION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/16/2001
|
Application #:
|
09225649
|
Filing Dt:
|
01/05/1999
|
|
Title:
|
GRADED COMPOUND SEED LAYERS FOR SEMICONDUCTORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2001
|
Application #:
|
09225982
|
Filing Dt:
|
01/05/1999
|
|
Title:
|
PHYSICAL RENAME REGISTER FOR EFFICIENTLY STORING FLOATING POINT, INTEGER CONDITION CODE, AND MULTIMEDIA VALUES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/13/2001
|
Application #:
|
09226564
|
Filing Dt:
|
01/07/1999
|
|
Title:
|
HIGH PERFORMANCE TRANSISTOR FABRICATED ON A DIELECTRIC FILM AND METHOD OF MAKING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/25/2000
|
Application #:
|
09226765
|
Filing Dt:
|
01/06/1999
|
|
Title:
|
DUAL DAMASCENE STRUCTURE FORMED IN A SINGLE PHOTORESIST FILM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/03/2000
|
Application #:
|
09226881
|
Filing Dt:
|
01/07/1999
|
|
Title:
|
ULTRA SHALLOW EXTENSION FORMATION USING DISPOSABLE SPACERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/15/2001
|
Application #:
|
09227067
|
Filing Dt:
|
01/05/1999
|
|
Title:
|
SEMICONDUCTOR INTERCONNECT INTERFACE PROCESSING BY HIGH TEMPERATURE DEPOSITION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/27/2001
|
Application #:
|
09227695
|
Filing Dt:
|
01/08/1999
|
|
Title:
|
SOI BASED TFT HAVING A GATE INSULATION LAYER THICKER THAN THE CHANNEL REGION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/24/2004
|
Application #:
|
09228347
|
Filing Dt:
|
01/11/1999
|
|
Title:
|
METHODOLOGY AND GRAPHICAL USER INTERFACE FOR BUILDING LOGIC SYNTHESIS COMMAND SCRIPTS USING MICRO-TEMPLATES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/19/2001
|
Application #:
|
09229264
|
Filing Dt:
|
01/13/1999
|
|
Title:
|
METHOD OF FORMING SUBMICRON-DIMENSIONED METAL PATTERNS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/07/2000
|
Application #:
|
09229590
|
Filing Dt:
|
01/13/1999
|
|
Title:
|
SEMICONDUCTOR INTERCONNECT INTERFACE PROCESSING BY PULSE LASER ANNEAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/19/2000
|
Application #:
|
09231427
|
Filing Dt:
|
01/14/1999
|
|
Title:
|
METHOD OF FABRICATING A TRANSISTOR WITH A DIELECTRIC UNDERLAYER AND DEVICE INCORPORATING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/14/2003
|
Application #:
|
09233215
|
Filing Dt:
|
01/20/1999
|
|
Title:
|
MECHANISM FOR CAPTURING AND REPORTING INTERRUPT EVENTS OF DIFFERENT CLOCK DOMAINS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/18/2001
|
Application #:
|
09233259
|
Filing Dt:
|
01/19/1999
|
|
Title:
|
SYSTEM FOR CANCELING SPECULATIVELY FETCHED INSTRUCTIONS FOLLOWING A BRANCH MIS-PREDICTION IN A MICROPROCESSOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/02/2002
|
Application #:
|
09233849
|
Filing Dt:
|
01/19/1999
|
|
Title:
|
PROCESS FOR FORMING ANTI-REFLECTIVE FILM FOR SEMICONDUCTOR FABRICATION USING EXTREMELY SHORT WAVELENGTH DEEP ULTRAVIOLET PHOTOLITHOGRAPHY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/05/2000
|
Application #:
|
09234456
|
Filing Dt:
|
01/21/1999
|
|
Title:
|
INTERRUPT MANAGEMENT SYSTEM HAVING BATCH MECHANISM FOR HANDLING INTERRUPT EVENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/14/2002
|
Application #:
|
09234528
|
Filing Dt:
|
01/21/1999
|
|
Title:
|
MECHANISM TO PREVENT DATA LOSS IN CASE OF A POWER FAILURE WHILE A PC IS IN SUSPEND TO RAM STATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/18/2003
|
Application #:
|
09234767
|
Filing Dt:
|
01/21/1999
|
|
Title:
|
METHODS AND APPARATUS FOR TIMING RECOVERY FROM A SAMPLED AND EQUALIZED DATA SIGNAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/26/2001
|
Application #:
|
09234855
|
Filing Dt:
|
01/22/1999
|
|
Title:
|
CMOS TRANSISTOR DESIGN FOR SHARED N+/P+ ELECTRODE WITH ENHANCED DEVICE PERFORMANCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/2002
|
Application #:
|
09234992
|
Filing Dt:
|
01/21/1999
|
|
Title:
|
METHOD AND APPARATUS FOR MEASURING CUMULATIVE DEFECTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/12/2000
|
Application #:
|
09236025
|
Filing Dt:
|
01/22/1999
|
|
Title:
|
INSITU HARDMASK AND METAL ETCH IN A SINGLE ETCHER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/13/2003
|
Application #:
|
09236622
|
Filing Dt:
|
01/29/1999
|
|
Title:
|
AUTOMATIC DATA QUALITY ADJUSTMENT TO REDUCE RESPONSE TIME IN BROWSING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/27/2001
|
Application #:
|
09237258
|
Filing Dt:
|
01/26/1999
|
|
Title:
|
METHOD OF FORMING MULTIPLE LEVELS OF PATTERNED METALLIZATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/22/2000
|
Application #:
|
09237573
|
Filing Dt:
|
01/26/1999
|
|
Title:
|
APPARATUS FOR FORMING A COPPER INTERCONNECT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/01/2000
|
Application #:
|
09237584
|
Filing Dt:
|
01/26/1999
|
|
Title:
|
COPPER/LOW DIELECTRIC INTERCONNECT FORMATION WITH REDUCED ELECTROMIGRATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/08/2002
|
Application #:
|
09238047
|
Filing Dt:
|
01/27/1999
|
|
Title:
|
NETWORK SWITCHING SYSTEM HAVING OVERFLOW BYPASS IN INTERNAL RULES CHECKER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/22/2000
|
Application #:
|
09238051
|
Filing Dt:
|
01/27/1999
|
|
Title:
|
HIGH PLANARITY HIGH-DENSITY IN-LAID METALLIZATION PATTERNS BY DAMASCENE-CMP PROCESSING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/12/2000
|
Application #:
|
09238081
|
Filing Dt:
|
01/26/1999
|
|
Title:
|
MULTI-LAYER GATE CONDUCTOR HAVING A DIFFUSION BARRIER IN THE BOTTOM LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/14/1999
|
Application #:
|
09238359
|
Filing Dt:
|
01/27/1999
|
|
Title:
|
PRE-AMORPHIZATION PROCESS FOR SOURCE/DRAIN JUNCTION
|
|
