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Reel/Frame:	049490/0001			Pages:	892
		Recorded:	11/29/2018
Conveyance:	SECURITY AGREEMENT

Total properties: 13706
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Patent #:	7132323	Issue Dt:	11/07/2006	Application #:	10713447	Filing Dt:	11/14/2003
Publication #:	US20050106800	Pub Dt:	05/19/2005
Title:	CMOS WELL STRUCTURE AND METHOD OF FORMING THE SAME

Patent #:	7137827	Issue Dt:	11/21/2006	Application #:	10715288	Filing Dt:	11/17/2003
Publication #:	US20050106902	Pub Dt:	05/19/2005
Title:	INTERPOSER WITH ELECTRICAL CONTACT BUTTON AND METHOD

Patent #:	7602000	Issue Dt:	10/13/2009	Application #:	10715376	Filing Dt:	11/19/2003
Publication #:	US20050104101	Pub Dt:	05/19/2005
Title:	SPIN-CURRENT SWITCHED MAGNETIC MEMORY ELEMENT SUITABLE FOR CIRCUIT INTEGRATION AND METHOD OF FABRICATING THE MEMORY ELEMENT

Patent #:	7902682	Issue Dt:	03/08/2011	Application #:	10715689	Filing Dt:	11/18/2003
Publication #:	US20050104147	Pub Dt:	05/19/2005
Title:	ULTRAVIOLET ENERGY CURABLE TAPE AND METHOD OF MAKING A SEMICONDUCTOR CHIP USING THE TAPE

Patent #:	6793961	Issue Dt:	09/21/2004	Application #:	10717385	Filing Dt:	11/19/2003
Publication #:	US20040100729	Pub Dt:	05/27/2004
Title:	ENHANCEMENT OF MAGNETIZATION SWITCHING SPEED IN SOFT FERROMAGNETIC FILMS THROUGH CONTROL OF EDGE STRESS ANISOTROPY

Patent #:	7091566	Issue Dt:	08/15/2006	Application #:	10717737	Filing Dt:	11/20/2003
Publication #:	US20050110085	Pub Dt:	05/26/2005
Title:	DUAL GATE FINFET

Patent #:	7251743	Issue Dt:	07/31/2007	Application #:	10719113	Filing Dt:	11/20/2003
Publication #:	US20050114741	Pub Dt:	05/26/2005
Title:	METHOD, SYSTEM, AND PROGRAM FOR TRANSMITTING INPUT/OUTPUT REQUESTS FROM A PRIMARY CONTROLLER TO A SECONDARY CONTROLLER

Patent #:	7302603	Issue Dt:	11/27/2007	Application #:	10719180	Filing Dt:	11/20/2003
Publication #:	US20050114729	Pub Dt:	05/26/2005
Title:	HOST-INITIATED DATA RECONSTRUCTION FOR IMPROVED RAID READ OPERATIONS

Patent #:	7256455	Issue Dt:	08/14/2007	Application #:	10720166	Filing Dt:	11/25/2003
Publication #:	US20040110097	Pub Dt:	06/10/2004
Title:	DOUBLE GATE SEMICONDUCTOR DEVICE HAVING A METAL GATE

Patent #:	7111266	Issue Dt:	09/19/2006	Application #:	10720464	Filing Dt:	11/24/2003
Publication #:	US20050114814	Pub Dt:	05/26/2005
Title:	MULTIPLE VOLTAGE INTEGRATED CIRCUIT AND DESIGN METHOD THEREFOR

Patent #:	7119578	Issue Dt:	10/10/2006	Application #:	10720466	Filing Dt:	11/24/2003
Publication #:	US20050110519	Pub Dt:	05/26/2005
Title:	SINGLE SUPPLY LEVEL CONVERTER

Patent #:	7295604	Issue Dt:	11/13/2007	Application #:	10720974	Filing Dt:	11/24/2003
Publication #:	US20050111536	Pub Dt:	05/26/2005
Title:	METHOD FOR DETERMINING JITTER OF A SIGNAL IN A SERIAL LINK AND HIGH SPEED SERIAL LINK

Patent #:	7214886	Issue Dt:	05/08/2007	Application #:	10722226	Filing Dt:	11/25/2003
Publication #:	US20050109535	Pub Dt:	05/26/2005
Title:	HIGH PERFORMANCE CHIP CARRIER SUBSTRATE

Patent #:	7015580	Issue Dt:	03/21/2006	Application #:	10722704	Filing Dt:	11/25/2003
Publication #:	US20050112861	Pub Dt:	05/26/2005
Title:	ROUGHENED BONDING PAD AND BONDING WIRE SURFACES FOR LOW PRESSURE WIRE BONDING

Patent #:	7171585	Issue Dt:	01/30/2007	Application #:	10723751	Filing Dt:	11/26/2003
Publication #:	US20050132253	Pub Dt:	06/16/2005
Title:	DIAGNOSING FAULTS AND ERRORS FROM A DATA REPOSITORY USING DIRECTED GRAPHS

Patent #:	7075150	Issue Dt:	07/11/2006	Application #:	10725849	Filing Dt:	12/02/2003
Publication #:	US20050116289	Pub Dt:	06/02/2005
Title:	ULTRA-THIN SI CHANNEL MOSFET USING A SELF-ALIGNED OXYGEN IMPLANT AND DAMASCENE TECHNIQUE

Patent #:	7067902	Issue Dt:	06/27/2006	Application #:	10726140	Filing Dt:	12/02/2003
Publication #:	US20050118803	Pub Dt:	06/02/2005
Title:	BUILDING METAL PILLARS IN A CHIP FOR STRUCTURE SUPPORT

Patent #:	6967175	Issue Dt:	11/22/2005	Application #:	10726619	Filing Dt:	12/04/2003
Title:	DAMASCENE GATE SEMICONDUCTOR PROCESSING WITH LOCAL THINNING OF CHANNEL REGION

Patent #:	8069336	Issue Dt:	11/29/2011	Application #:	10726902	Filing Dt:	12/03/2003
Publication #:	US20050125632	Pub Dt:	06/09/2005
Title:	TRANSITIONING FROM INSTRUCTION CACHE TO TRACE CACHE ON LABEL BOUNDARIES

Patent #:	7045873	Issue Dt:	05/16/2006	Application #:	10728750	Filing Dt:	12/08/2003
Publication #:	US20050121699	Pub Dt:	06/09/2005
Title:	DYNAMIC THRESHOLD VOLTAGE MOSFET ON SOI

Patent #:	7183223	Issue Dt:	02/27/2007	Application #:	10728909	Filing Dt:	12/08/2003
Title:	METHODS FOR FORMING SMALL CONTACTS

Patent #:	7276787	Issue Dt:	10/02/2007	Application #:	10729254	Filing Dt:	12/05/2003
Publication #:	US20050121768	Pub Dt:	06/09/2005
Title:	SILICON CHIP CARRIER WITH CONDUCTIVE THROUGH-VIAS AND METHOD FOR FABRICATING SAME

Patent #:	7820369	Issue Dt:	10/26/2010	Application #:	10729452	Filing Dt:	12/04/2003
Publication #:	US20050123852	Pub Dt:	06/09/2005
Title:	METHOD FOR PATTERNING A LOW ACTIVATION ENERGY PHOTORESIST

Patent #:	7297811	Issue Dt:	11/20/2007	Application #:	10729453	Filing Dt:	12/04/2003
Publication #:	US20050124827	Pub Dt:	06/09/2005
Title:	PRECURSORS TO FLUOROALKANOL-CONTAINING OLEFIN MONOMERS AND ASSOCIATED METHODS OF SYNTHESIS AND USE

Patent #:	7144818	Issue Dt:	12/05/2006	Application #:	10729479	Filing Dt:	12/05/2003
Publication #:	US20050124170	Pub Dt:	06/09/2005
Title:	SEMICONDUCTOR SUBSTRATE AND PROCESSES THEREFOR

Patent #:	7287177	Issue Dt:	10/23/2007	Application #:	10729751	Filing Dt:	12/04/2003
Publication #:	US20050125707	Pub Dt:	06/09/2005
Title:	DIGITAL RELIABILITY MONITOR HAVING AUTONOMIC REPAIR AND NOTIFICATION CAPABILITY

Patent #:	8019805	Issue Dt:	09/13/2011	Application #:	10730800	Filing Dt:	12/09/2003
Title:	APPARATUS AND METHOD FOR MULTIPLE PASS EXTENDED PRECISION FLOATING POINT MULTIPLICATION

Patent #:	7071122	Issue Dt:	07/04/2006	Application #:	10730892	Filing Dt:	12/10/2003
Publication #:	US20050127417	Pub Dt:	06/16/2005
Title:	FIELD EFFECT TRANSISTOR WITH ETCHED-BACK GATE DIELECTRIC

Patent #:	7444734	Issue Dt:	11/04/2008	Application #:	10731520	Filing Dt:	12/09/2003
Publication #:	US20050122265	Pub Dt:	06/09/2005
Title:	APPARATUS AND METHODS FOR CONSTRUCTING ANTENNAS USING VIAS AS RADIATING ELEMENTS FORMED IN A SUBSTRATE

Patent #:	7388258	Issue Dt:	06/17/2008	Application #:	10732322	Filing Dt:	12/10/2003
Publication #:	US20050127362	Pub Dt:	06/16/2005
Title:	SECTIONAL FIELD EFFECT DEVICES

Patent #:	7943919	Issue Dt:	05/17/2011	Application #:	10732579	Filing Dt:	12/10/2003
Publication #:	US20050127348	Pub Dt:	06/16/2005
Title:	INTEGRATED CIRCUIT WITH UPSTANDING STYLUS

Patent #:	7928420	Issue Dt:	04/19/2011	Application #:	10732580	Filing Dt:	12/10/2003
Publication #:	US20050127349	Pub Dt:	06/16/2005
Title:	PHASE CHANGE TIP STORAGE CELL

Patent #:	7271444	Issue Dt:	09/18/2007	Application #:	10732958	Filing Dt:	12/11/2003
Publication #:	US20050127466	Pub Dt:	06/16/2005
Title:	WRAP-AROUND GATE FIELD EFFECT TRANSISTOR

Patent #:	7198995	Issue Dt:	04/03/2007	Application #:	10733378	Filing Dt:	12/12/2003
Publication #:	US20050130358	Pub Dt:	06/16/2005
Title:	STRAINED FINFETS AND METHOD OF MANUFACTURE

Patent #:	7374793	Issue Dt:	05/20/2008	Application #:	10733974	Filing Dt:	12/11/2003
Publication #:	US20050129948	Pub Dt:	06/16/2005
Title:	METHODS AND STRUCTURES FOR PROMOTING STABLE SYNTHESIS OF CARBON NANOTUBES

Patent #:	8445946	Issue Dt:	05/21/2013	Application #:	10735061	Filing Dt:	12/11/2003
Publication #:	US20050128803	Pub Dt:	06/16/2005
Title:	GATED DIODE MEMORY CELLS

Patent #:	7745775	Issue Dt:	06/29/2010	Application #:	10736424	Filing Dt:	12/15/2003
Publication #:	US20050129414	Pub Dt:	06/16/2005
Title:	TESTING OF TRANSIMPEDANCE AMPLIFIERS

Patent #:	7127699	Issue Dt:	10/24/2006	Application #:	10737626	Filing Dt:	12/16/2003
Publication #:	US20050132310	Pub Dt:	06/16/2005
Title:	METHOD FOR OPTIMIZING A NUMBER OF KERNELS USED IN A SUM OF COHERENT SOURCES FOR OPTICAL PROXIMITY CORRECTION IN AN OPTICAL MICROLITHOGRAPHY PROCESS

Patent #:	7058247	Issue Dt:	06/06/2006	Application #:	10738064	Filing Dt:	12/17/2003
Publication #:	US20050135732	Pub Dt:	06/23/2005
Title:	SILICON CARRIER FOR OPTICAL INTERCONNECT MODULES

Patent #:	6943087	Issue Dt:	09/13/2005	Application #:	10738529	Filing Dt:	12/17/2003
Title:	SEMICONDUCTOR ON INSULATOR MOSFET HAVING STRAINED SILICON CHANNEL

Patent #:	7127696	Issue Dt:	10/24/2006	Application #:	10738711	Filing Dt:	12/17/2003
Publication #:	US20050138578	Pub Dt:	06/23/2005
Title:	METHOD AND APPARATUS FOR GENERATING STEINER TREES USING SIMULTANEOUS BLOCKAGE AVOIDANCE, DELAY OPTIMIZATION AND DESIGN DENSITY MANAGEMENT

Patent #:	7137081	Issue Dt:	11/14/2006	Application #:	10738714	Filing Dt:	12/17/2003
Publication #:	US20050138589	Pub Dt:	06/23/2005
Title:	METHOD AND APPARATUS FOR PERFORMING DENSITY-BIASED BUFFER INSERTION IN AN INTEGRATED CIRCUIT DESIGN

Patent #:	7071065	Issue Dt:	07/04/2006	Application #:	10738716	Filing Dt:	12/17/2003
Title:	STRAINED SILICON PMOS HAVING SILICON GERMANIUM SOURCE/DRAIN EXTENSIONS AND METHOD FOR ITS FABRICATION

Patent #:	7395482	Issue Dt:	07/01/2008	Application #:	10739966	Filing Dt:	12/18/2003
Publication #:	US20050138518	Pub Dt:	06/23/2005
Title:	DATA STORAGE SYSTEMS

Patent #:	7482252	Issue Dt:	01/27/2009	Application #:	10740546	Filing Dt:	12/22/2003
Title:	METHOD FOR REDUCING FLOATING BODY EFFECTS IN SOI SEMICONDUCTOR DEVICE WITHOUT DEGRADING MOBILITY

Patent #:	7122437	Issue Dt:	10/17/2006	Application #:	10741203	Filing Dt:	12/19/2003
Publication #:	US20050133846	Pub Dt:	06/23/2005
Title:	DEEP TRENCH CAPACITOR WITH BURIED PLATE ELECTRODE AND ISOLATION COLLAR

Patent #:	7962459	Issue Dt:	06/14/2011	Application #:	10745044	Filing Dt:	12/23/2003
Publication #:	US20040220968	Pub Dt:	11/04/2004
Title:	METHOD OF PROVIDING CONTEXT SPECIFIC RECIPES IN A SEMICONDUCTOR FACILITY BY DEFINING PRODUCT CATEGORIES

Patent #:	8261239	Issue Dt:	09/04/2012	Application #:	10745822	Filing Dt:	12/23/2003
Publication #:	US20040194054	Pub Dt:	09/30/2004
Title:	LOCATING A TESTABLE OBJECT IN A FUNCTIONAL TESTING TOOL

Patent #:	7022596	Issue Dt:	04/04/2006	Application #:	10747680	Filing Dt:	12/30/2003
Publication #:	US20050146059	Pub Dt:	07/07/2005
Title:	METHOD FOR FORMING RECTANGULAR-SHAPED SPACERS FOR SEMICONDUCTOR DEVICES

Patent #:	7169664	Issue Dt:	01/30/2007	Application #:	10747722	Filing Dt:	12/29/2003
Publication #:	US20040251518	Pub Dt:	12/16/2004
Title:	METHOD OF REDUCING WAFER CONTAMINATION BY REMOVING UNDER-METAL LAYERS AT THE WAFER EDGE

Patent #:	7150675	Issue Dt:	12/19/2006	Application #:	10747723	Filing Dt:	12/29/2003
Publication #:	US20040242122	Pub Dt:	12/02/2004
Title:	METHOD AND SYSTEM FOR CONTROLLING THE CHEMICAL MECHANICAL POLISHING BY USING A SENSOR SIGNAL OF A PAD CONDITIONER

Patent #:	7236918	Issue Dt:	06/26/2007	Application #:	10749607	Filing Dt:	12/31/2003
Publication #:	US20050149313	Pub Dt:	07/07/2005
Title:	METHOD AND SYSTEM FOR SELECTIVE COMPILATION OF INSTRUMENTATION ENTITIES INTO A SIMULATION MODEL OF A DIGITAL DESIGN

Patent #:	6972440	Issue Dt:	12/06/2005	Application #:	10750697	Filing Dt:	01/02/2004
Publication #:	US20040140506	Pub Dt:	07/22/2004
Title:	ENHANCED T-GATE STRUCTURE FOR MODULATION DOPED FIELD EFFECT TRANSISTORS

Patent #:	8324667	Issue Dt:	12/04/2012	Application #:	10751714	Filing Dt:	01/05/2004
Publication #:	US20050145895	Pub Dt:	07/07/2005
Title:	AMPLIFIERS USING GATED DIODES

Patent #:	7705345	Issue Dt:	04/27/2010	Application #:	10751916	Filing Dt:	01/07/2004
Publication #:	US20050145941	Pub Dt:	07/07/2005
Title:	HIGH PERFORMANCE STRAINED SILICON FINFETS DEVICE AND METHOD FOR FORMING SAME

Patent #:	7351639	Issue Dt:	04/01/2008	Application #:	10753241	Filing Dt:	01/08/2004
Publication #:	US20040140529	Pub Dt:	07/22/2004
Title:	INCREASING AN ELECTRICAL RESISTANCE OF A RESISTOR BY OXIDATION OR NITRIDIZATION

Patent #:	7063931	Issue Dt:	06/20/2006	Application #:	10753989	Filing Dt:	01/08/2004
Publication #:	US20050153232	Pub Dt:	07/14/2005
Title:	POSITIVE PHOTORESIST COMPOSITION WITH A POLYMER INCLUDING A FLUOROSULFONAMIDE GROUP AND PROCESS FOR ITS USE

Patent #:	6958516	Issue Dt:	10/25/2005	Application #:	10754320	Filing Dt:	01/08/2004
Publication #:	US20050151193	Pub Dt:	07/14/2005
Title:	DISCRIMINATIVE SOI WITH OXIDE HOLES UNDERNEATH DC SOURCE/DRAIN

Patent #:	7679134	Issue Dt:	03/16/2010	Application #:	10754515	Filing Dt:	01/12/2004
Title:	FINFET DEVICE WITH MULTIPLE FIN STRUCTURES

Patent #:	7432557	Issue Dt:	10/07/2008	Application #:	10755344	Filing Dt:	01/13/2004
Title:	FINFET DEVICE WITH MULTIPLE CHANNELS

Patent #:	7462549	Issue Dt:	12/09/2008	Application #:	10755602	Filing Dt:	01/12/2004
Publication #:	US20050151222	Pub Dt:	07/14/2005
Title:	SHALLOW TRENCH ISOLATION PROCESS AND STRUCTURE WITH MINIMIZED STRAINED SILICON CONSUMPTION

Patent #:	7373484	Issue Dt:	05/13/2008	Application #:	10755692	Filing Dt:	01/12/2004
Title:	CONTROLLING WRITES TO NON-RENAMED REGISTER SPACE IN AN OUT-OF-ORDER EXECUTION MICROPROCESSOR

Patent #:	7251710	Issue Dt:	07/31/2007	Application #:	10755734	Filing Dt:	01/12/2004
Title:	CACHE MEMORY SUBSYSTEM INCLUDING A FIXED LATENCY R/W PIPELINE

Patent #:	7213126	Issue Dt:	05/01/2007	Application #:	10755742	Filing Dt:	01/12/2004
Title:	METHOD AND PROCESSOR INCLUDING LOGIC FOR STORING TRACES WITHIN A TRACE CACHE

Patent #:	7238588	Issue Dt:	07/03/2007	Application #:	10755746	Filing Dt:	01/12/2004
Publication #:	US20050095807	Pub Dt:	05/05/2005
Title:	SILICON BUFFERED SHALLOW TRENCH ISOLATION

Patent #:	7138302	Issue Dt:	11/21/2006	Application #:	10755763	Filing Dt:	01/12/2004
Publication #:	US20050153486	Pub Dt:	07/14/2005
Title:	Method of fabricating an integrated circuit channel region

Patent #:	7068865	Issue Dt:	06/27/2006	Application #:	10755816	Filing Dt:	01/12/2004
Publication #:	US20050084213	Pub Dt:	04/21/2005
Title:	METHOD AND APPARATUS FOR THERMO-OPTIC MODULATION OF OPTICAL SIGNALS

Patent #:	7361457	Issue Dt:	04/22/2008	Application #:	10755875	Filing Dt:	01/13/2004
Publication #:	US20050153215	Pub Dt:	07/14/2005
Title:	REAL-TIME CONFIGURABLE MASKING

Patent #:	6967885	Issue Dt:	11/22/2005	Application #:	10757846	Filing Dt:	01/15/2004
Publication #:	US20050157577	Pub Dt:	07/21/2005
Title:	CONCURRENT REFRESH MODE WITH DISTRIBUTED ROW ADDRESS COUNTERS IN AN EMBEDDED DRAM

Patent #:	7030468	Issue Dt:	04/18/2006	Application #:	10758724	Filing Dt:	01/16/2004
Publication #:	US20050156285	Pub Dt:	07/21/2005
Title:	LOW K AND ULTRA LOW K SICOH DIELECTRIC FILMS AND METHODS TO FORM THE SAME

Patent #:	6836017	Issue Dt:	12/28/2004	Application #:	10759170	Filing Dt:	01/20/2004
Publication #:	US20040147117	Pub Dt:	07/29/2004
Title:	PROTECTION OF LOW-K ILD DURING DAMASCENE PROCESSING WITH THIN LINER

Patent #:	7071051	Issue Dt:	07/04/2006	Application #:	10761009	Filing Dt:	01/20/2004
Title:	METHOD FOR FORMING A THIN, HIGH QUALITY BUFFER LAYER IN A FIELD EFFECT TRANSISTOR AND RELATED STRUCTURE

Patent #:	7250645	Issue Dt:	07/31/2007	Application #:	10761374	Filing Dt:	01/22/2004
Title:	REVERSED T-SHAPED FINFET

Patent #:	7189644	Issue Dt:	03/13/2007	Application #:	10763308	Filing Dt:	01/23/2004
Publication #:	US20040188766	Pub Dt:	09/30/2004
Title:	CMOS DEVICE INTEGRATION FOR LOW EXTERNAL RESISTANCE

Patent #:	6994570	Issue Dt:	02/07/2006	Application #:	10765042	Filing Dt:	01/28/2004
Publication #:	US20050164526	Pub Dt:	07/28/2005
Title:	HIGH PERFORMANCE INTERPOSER FOR A CHIP PACKAGE USING DEFORMABLE BUTTON CONTACTS

Patent #:	6958526	Issue Dt:	10/25/2005	Application #:	10766249	Filing Dt:	01/27/2004
Publication #:	US20040188674	Pub Dt:	09/30/2004
Title:	ELECTRONIC STRUCTURES WITH REDUCED CAPACITANCE

Patent #:	7425353	Issue Dt:	09/16/2008	Application #:	10768347	Filing Dt:	01/29/2004
Publication #:	US20050170212	Pub Dt:	08/04/2005
Title:	ENHANCEMENT OF MAGNETIC MEDIA RECORDING PERFORMANCE USING ION IRRADIATION TO TAILOR EXCHANGE COUPLING

Patent #:	7068138	Issue Dt:	06/27/2006	Application #:	10768773	Filing Dt:	01/29/2004
Publication #:	US20050167780	Pub Dt:	08/04/2005
Title:	HIGH Q FACTOR INTEGRATED CIRCUIT INDUCTOR

Patent #:	8217450	Issue Dt:	07/10/2012	Application #:	10770011	Filing Dt:	02/03/2004
Title:	DOUBLE-GATE SEMICONDUCTOR DEVICE WITH GATE CONTACTS FORMED ADJACENT SIDEWALLS OF A FIN

Patent #:	6855982	Issue Dt:	02/15/2005	Application #:	10770163	Filing Dt:	02/02/2004
Title:	SELF ALIGNED DOUBLE GATE TRANSISTOR HAVING A STRAINED CHANNEL REGION AND PROCESS THEREFOR

Patent #:	7568134	Issue Dt:	07/28/2009	Application #:	10770170	Filing Dt:	02/02/2004
Title:	METHOD OF EXHAUSTIVELY TESTING AN EMBEDDED ROM USING GENERATED ATPG TEST PATTERNS

Patent #:	7473566	Issue Dt:	01/06/2009	Application #:	10770682	Filing Dt:	02/03/2004
Title:	METHOD AND APPARATUS FOR CONTROLLING A FILM FORMATION PROCESS WITH MULTIPLE OBJECTIVES

Patent #:	7064067	Issue Dt:	06/20/2006	Application #:	10770905	Filing Dt:	02/02/2004
Title:	REDUCTION OF LATERAL SILICIDE GROWTH IN INTEGRATED CIRCUIT TECHNOLOGY

Patent #:	7512787	Issue Dt:	03/31/2009	Application #:	10771019	Filing Dt:	02/03/2004
Title:	RECEIVE IPSEC IN-LINE PROCESSING OF MUTABLE FIELDS FOR AH ALGORITHM

Patent #:	6856031	Issue Dt:	02/15/2005	Application #:	10771824	Filing Dt:	02/03/2004
Title:	SRAM CELL WITH WELL CONTACTS AND P+ DIFFUSION CROSSING TO GROUND OR N+ DIFFUSION CROSSING TO VDD

Patent #:	6991890	Issue Dt:	01/31/2006	Application #:	10773930	Filing Dt:	02/06/2004
Publication #:	US20050175928	Pub Dt:	08/11/2005
Title:	NEGATIVE PHOTORESIST COMPOSITION INVOLVING NON-CROSSLINKING CHEMISTRY

Patent #:	7422828	Issue Dt:	09/09/2008	Application #:	10774099	Filing Dt:	02/06/2004
Title:	MASK CD MEASUREMENT MONITOR OUTSIDE OF THE PELLICLE AREA

Patent #:	7064413	Issue Dt:	06/20/2006	Application #:	10774773	Filing Dt:	02/09/2004
Publication #:	US20040159910	Pub Dt:	08/19/2004
Title:	FIN-TYPE RESISTORS

Patent #:	7244980	Issue Dt:	07/17/2007	Application #:	10774827	Filing Dt:	02/09/2004
Publication #:	US20050176197	Pub Dt:	08/11/2005
Title:	LINE MASK DEFINED ACTIVE AREAS FOR 8F2 DRAM CELLS WITH FOLDED BIT LINES AND DEEP TRENCH PATTERNS

Patent #:	7227230	Issue Dt:	06/05/2007	Application #:	10775440	Filing Dt:	02/10/2004
Publication #:	US20040171201	Pub Dt:	09/02/2004
Title:	LOW K-GATE SPACERS BY FLUORINE IMPLANTATION

Patent #:	7183576	Issue Dt:	02/27/2007	Application #:	10775514	Filing Dt:	02/10/2004
Publication #:	US20040161875	Pub Dt:	08/19/2004
Title:	EPITAXIAL AND POLYCRYSTALLINE GROWTH OF SI1-X-YGEXCY AND SI1-YCY ALLOY LAYERS ON SI BY UHV-CVD

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100

Patent #:	7375410	Issue Dt:	05/20/2008	Application #:	10787002	Filing Dt:	02/25/2004
Publication #:	US20050184360	Pub Dt:	08/25/2005
Title:	ULTRA-THIN SOI VERTICAL BIPOLAR TRANSISTORS WITH AN INVERSION COLLECTOR ON THIN-BURIED OXIDE (BOX) FOR LOW SUBSTRATE-BIAS OPERATION AND METHODS THEREOF

Assignor

GLOBALFOUNDRIES INC.

Exec Dt:

11/27/2018

Assignee

WILMINGTON TRUST, NATIONAL ASSOCIATION

1100 NORTH MARKET STREET

WILMINGTON, DELAWARE 19801

Correspondence name and address
	CT CORPORATION
	4400 EASTON COMMONS WAY
	SUITE 125
	COLUMBUS, OH 43219

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